From 6ce53a17dde41c6602c0f3ac28304e04ecb306af Mon Sep 17 00:00:00 2001 From: Kevin Qin <36599815+Kevin99214@users.noreply.github.com> Date: Wed, 10 Apr 2024 16:09:34 -0400 Subject: [PATCH] Update SRAM.scala to improve perf on non-full sized reads Change a_sublane to not count sublanes if it's a read. Reads return full data width, no matter if the A channel size is not the data width --- src/main/scala/tilelink/SRAM.scala | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/tilelink/SRAM.scala b/src/main/scala/tilelink/SRAM.scala index f92e142ccaf..883c3e5df01 100644 --- a/src/main/scala/tilelink/SRAM.scala +++ b/src/main/scala/tilelink/SRAM.scala @@ -229,14 +229,15 @@ class TLRAM( val r_ready = !d_wb && !r_replay && (!d_full || d_ready) && (!r_respond || (!d_win && in.d.ready)) in.a.ready := !(d_full && d_wb) && (!r_full || r_ready) && (!r_full || !(r_atomic || r_sublane)) - // ignore sublane if mask is all set + // ignore sublane if it is a read or mask is all set + val a_read = in.a.bits.opcode === TLMessages.Get val a_sublane = if (eccBytes == 1) false.B else - ((in.a.bits.opcode === TLMessages.PutPartialData) && (~in.a.bits.mask.andR)) || - in.a.bits.size < log2Ceil(eccBytes).U + ~a_read && + (((in.a.bits.opcode === TLMessages.PutPartialData) && (~in.a.bits.mask.andR)) || + in.a.bits.size < log2Ceil(eccBytes).U) val a_atomic = if (!atomics) false.B else in.a.bits.opcode === TLMessages.ArithmeticData || in.a.bits.opcode === TLMessages.LogicalData - val a_read = in.a.bits.opcode === TLMessages.Get // Forward pipeline stage from R to D when (d_ready) { d_full := false.B }