diff --git a/.gitmodules b/.gitmodules
index fa1f58748ff..da3bce5d1a4 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -7,3 +7,9 @@
 [submodule "dependencies/chisel"]
 	path = dependencies/chisel
 	url = https://github.com/chipsalliance/chisel.git
+[submodule "dependencies/rvdecoderdb"]
+	path = dependencies/rvdecoderdb
+	url = https://github.com/sequencer/rvdecoderdb.git
+[submodule "dependencies/riscv-opcodes"]
+	path = dependencies/riscv-opcodes
+	url = https://github.com/riscv/riscv-opcodes.git
diff --git a/build.sc b/build.sc
index c4537a452d1..934aa5461f6 100644
--- a/build.sc
+++ b/build.sc
@@ -5,18 +5,20 @@ import coursier.maven.MavenRepository
 import $file.dependencies.hardfloat.common
 import $file.dependencies.cde.common
 import $file.dependencies.chisel.build
+import $file.dependencies.rvdecoderdb.common
 import $file.common
 
 object v {
   val scala = "2.13.12"
   // the first version in this Map is the mainly supported version which will be used to run tests
   val chiselCrossVersions = Map(
-    "3.6.0" -> (ivy"edu.berkeley.cs::chisel3:3.6.0", ivy"edu.berkeley.cs:::chisel3-plugin:3.6.0"),
-    "5.0.0" -> (ivy"org.chipsalliance::chisel:5.0.0", ivy"org.chipsalliance:::chisel-plugin:5.0.0"),
+    // "5.0.0" -> (ivy"org.chipsalliance::chisel:5.0.0", ivy"org.chipsalliance:::chisel-plugin:5.0.0"),
     // build from project from source
     "source" -> (ivy"org.chipsalliance::chisel:99", ivy"org.chipsalliance:::chisel-plugin:99"),
   )
   val mainargs = ivy"com.lihaoyi::mainargs:0.5.0"
+  val oslib = ivy"com.lihaoyi::os-lib:0.9.1"
+  val upickle = ivy"com.lihaoyi::upickle:3.1.3"
   val json4sJackson = ivy"org.json4s::json4s-jackson:4.0.5"
   val scalaReflect = ivy"org.scala-lang:scala-reflect:${scala}"
 }
@@ -75,6 +77,23 @@ trait CDE
   override def millSourcePath = os.pwd / "dependencies" / "cde" / "cde"
 }
 
+object rvdecoderdb extends RVDecoderDB
+
+trait RVDecoderDB
+  extends millbuild.dependencies.rvdecoderdb.common.RVDecoderDBJVMModule
+    with RocketChipPublishModule
+    with ScalaModule {
+
+  def scalaVersion: T[String] = T(v.scala)
+
+  def osLibIvy = v.oslib
+
+  def upickleIvy = v.upickle
+
+  override def millSourcePath = os.pwd / "dependencies" / "rvdecoderdb" / "rvdecoderdb"
+}
+
+
 object rocketchip extends Cross[RocketChip](v.chiselCrossVersions.keys.toSeq)
 
 trait RocketChip
@@ -100,6 +119,8 @@ trait RocketChip
 
   def cdeModule = cde
 
+  def rvdecoderdbModule = rvdecoderdb
+
   def mainargsIvy = v.mainargs
 
   def json4sJacksonIvy = v.json4sJackson
@@ -132,7 +153,7 @@ trait Emulator extends Cross.Module2[String, String] {
       os.proc(
         mill.util.Jvm.javaExe,
         "-jar",
-        rocketchip(v.chiselCrossVersions.keys.head).assembly().path,
+        rocketchip(v.chiselCrossVersions.keys.last).assembly().path,
         "--dir", T.dest.toString,
         "--top", top,
         config.split('_').flatMap(c => Seq("--config", c)),
@@ -232,6 +253,7 @@ trait Emulator extends Cross.Module2[String, String] {
          |  ${mfccompiler.rtls().map(_.path.toString).mkString("\n")}
          |  TOP_MODULE TestHarness
          |  PREFIX VTestHarness
+         |  TRACE
          |  VERILATOR_ARGS ${verilatorArgs().mkString(" ")}
          |)
          |""".stripMargin
@@ -242,10 +264,11 @@ trait Emulator extends Cross.Module2[String, String] {
       Seq(
         // format: off
         "-Wno-UNOPTTHREADS", "-Wno-STMTDLY", "-Wno-LATCH", "-Wno-WIDTH", "--no-timing",
-        "--x-assign unique",
+        "--x-assign 0",
+        "--x-initial 0",
         """+define+PRINTF_COND=\$c\(\"verbose\",\"&&\",\"done_reset\"\)""",
         """+define+STOP_COND=\$c\(\"done_reset\"\)""",
-        "+define+RANDOMIZE_GARBAGE_ASSIGN",
+        "+define+RANDOM=0",
         "--output-split 20000",
         "--output-split-cfuncs 20000",
         "--max-num-width 1048576",
@@ -307,8 +330,8 @@ object emulator extends Cross[Emulator](
   //
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config"),
-  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig"),
-  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config"),
+//  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig"),
+//  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config"),
 )
 
 object `runnable-riscv-test` extends mill.Cross[RiscvTest](
diff --git a/common.sc b/common.sc
index 574f0ad4310..a47ee4c1335 100644
--- a/common.sc
+++ b/common.sc
@@ -45,11 +45,14 @@ trait RocketChipModule
   // should be cde/common.sc#CDEModule
   def cdeModule: ScalaModule
 
+  // should be dependencies/rvdecoderdb/common.sc#RVDecoderDB
+  def rvdecoderdbModule: ScalaModule
+
   def mainargsIvy: Dep
 
   def json4sJacksonIvy: Dep
 
-  override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, hardfloatModule, cdeModule)
+  override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, hardfloatModule, cdeModule, rvdecoderdbModule)
 
   override def ivyDeps = T(
     super.ivyDeps() ++ Agg(
diff --git a/dependencies/riscv-opcodes b/dependencies/riscv-opcodes
new file mode 160000
index 00000000000..2c457dd5471
--- /dev/null
+++ b/dependencies/riscv-opcodes
@@ -0,0 +1 @@
+Subproject commit 2c457dd5471195c16c72981a2c8fc7b4c8564794
diff --git a/dependencies/rvdecoderdb b/dependencies/rvdecoderdb
new file mode 160000
index 00000000000..2b322c48a75
--- /dev/null
+++ b/dependencies/rvdecoderdb
@@ -0,0 +1 @@
+Subproject commit 2b322c48a7501cbadb12e8668e33683372fb61d6