From e254fff5cee7d53b4e9cd7b5685716b9e9b08eb7 Mon Sep 17 00:00:00 2001 From: Alex Swehla Date: Mon, 18 Mar 2024 18:56:40 -0700 Subject: [PATCH] Migrate diplomacy imports to standalone diplomacy Updates diplomacy imports to explicitly use standalone diplomacy module. --- src/main/scala/devices/debug/APB.scala | 9 +++-- src/main/scala/devices/debug/Custom.scala | 9 +++-- src/main/scala/devices/debug/DMI.scala | 9 +++-- src/main/scala/devices/debug/Debug.scala | 26 ++++++++------ src/main/scala/devices/debug/Periphery.scala | 25 +++++++------ src/main/scala/devices/debug/SBA.scala | 13 ++++--- src/main/scala/devices/tilelink/BootROM.scala | 12 ++++--- .../scala/devices/tilelink/BusBlocker.scala | 9 +++-- src/main/scala/devices/tilelink/CLINT.scala | 19 +++++----- .../tilelink/CanHaveBuiltInDevices.scala | 9 ++--- .../scala/devices/tilelink/ClockBlocker.scala | 14 ++++---- src/main/scala/devices/tilelink/DevNull.scala | 10 ++++-- src/main/scala/devices/tilelink/Error.scala | 9 +++-- src/main/scala/devices/tilelink/MaskROM.scala | 13 ++++--- .../scala/devices/tilelink/MasterMux.scala | 14 ++++++-- .../devices/tilelink/PhysicalFilter.scala | 14 +++++--- src/main/scala/devices/tilelink/Plic.scala | 23 +++++++----- src/main/scala/devices/tilelink/TestRAM.scala | 9 +++-- src/main/scala/devices/tilelink/Zero.scala | 7 ++-- src/main/scala/examples/ExampleDevice.scala | 6 ++-- src/main/scala/formal/FormalUtils.scala | 5 +-- src/main/scala/groundtest/Configs.scala | 3 +- src/main/scala/groundtest/DummyPTW.scala | 4 +-- .../groundtest/GroundTestSubsystem.scala | 8 +++-- src/main/scala/groundtest/TestHarness.scala | 6 ++-- src/main/scala/groundtest/Tile.scala | 6 +++- src/main/scala/groundtest/TraceGen.scala | 8 +++-- .../scala/interrupts/BlockDuringReset.scala | 5 +-- src/main/scala/interrupts/Crossing.scala | 5 +-- .../scala/interrupts/CrossingHelper.scala | 6 ++-- src/main/scala/interrupts/Nodes.scala | 6 ++-- src/main/scala/interrupts/NullIntSource.scala | 5 +-- src/main/scala/interrupts/Parameters.scala | 7 ++-- .../scala/interrupts/RegisterRouter.scala | 6 +++- src/main/scala/interrupts/Xbar.scala | 4 +-- src/main/scala/interrupts/package.scala | 10 ++++-- .../prci/BundleBridgeBlockDuringReset.scala | 10 ++++-- src/main/scala/prci/ClockDivider.scala | 8 +++-- src/main/scala/prci/ClockDomain.scala | 8 +++-- src/main/scala/prci/ClockGroup.scala | 8 +++-- src/main/scala/prci/ClockNodes.scala | 10 ++++-- src/main/scala/prci/IOHelper.scala | 5 ++- src/main/scala/prci/ResetCrossingType.scala | 6 ++-- src/main/scala/prci/ResetStretcher.scala | 7 ++-- src/main/scala/prci/ResetSynchronizer.scala | 8 +++-- src/main/scala/prci/ResetWrangler.scala | 5 +-- src/main/scala/prci/TestClockSource.scala | 7 ++-- src/main/scala/prci/package.scala | 4 ++- src/main/scala/regmapper/RegMapper.scala | 10 +++--- src/main/scala/regmapper/RegisterRouter.scala | 10 ++++-- src/main/scala/regmapper/Test.scala | 10 +++--- src/main/scala/rocket/DCache.scala | 25 ++++++++----- src/main/scala/rocket/Frontend.scala | 17 +++++---- src/main/scala/rocket/HellaCache.scala | 26 ++++++++------ src/main/scala/rocket/ICache.scala | 29 +++++++++------ src/main/scala/rocket/PMA.scala | 13 ++++--- .../scala/rocket/ScratchpadSlavePort.scala | 14 +++++--- src/main/scala/rocket/TLB.scala | 19 ++++++---- src/main/scala/rocket/TLBPermissions.scala | 6 ++-- src/main/scala/subsystem/Attachable.scala | 5 +-- .../subsystem/BankedCoherenceParams.scala | 18 +++++++--- src/main/scala/subsystem/BaseSubsystem.scala | 17 ++++++--- src/main/scala/subsystem/BusTopology.scala | 8 +++-- src/main/scala/subsystem/Cluster.scala | 20 ++++++----- src/main/scala/subsystem/Configs.scala | 22 ++++++++---- .../scala/subsystem/CrossingWrapper.scala | 17 ++++++--- src/main/scala/subsystem/FrontBus.scala | 9 ++--- .../subsystem/HasHierarchicalElements.scala | 25 ++++++++----- src/main/scala/subsystem/HasTiles.scala | 25 +++++++------ .../scala/subsystem/HierarchicalElement.scala | 17 +++++---- .../HierarchicalElementPRCIDomain.scala | 22 +++++++----- src/main/scala/subsystem/InterruptBus.scala | 13 ++++--- src/main/scala/subsystem/MemoryBus.scala | 13 ++++--- src/main/scala/subsystem/PeripheryBus.scala | 16 ++++++--- src/main/scala/subsystem/Ports.scala | 27 +++++++++++--- src/main/scala/subsystem/RTC.scala | 7 ++-- .../scala/subsystem/RocketSubsystem.scala | 13 +++---- src/main/scala/subsystem/SystemBus.scala | 17 ++++++--- src/main/scala/system/SimAXIMem.scala | 11 +++--- src/main/scala/system/TestHarness.scala | 6 ++-- src/main/scala/tile/BaseTile.scala | 28 ++++++++++----- src/main/scala/tile/BusErrorUnit.scala | 35 +++++++++---------- src/main/scala/tile/Interrupts.scala | 16 ++++++--- src/main/scala/tile/LazyRoCC.scala | 14 +++++--- src/main/scala/tile/RocketTile.scala | 26 ++++++++++---- src/main/scala/tile/TilePRCIDomain.scala | 17 +++++---- src/main/scala/tilelink/AddressAdjuster.scala | 6 +++- src/main/scala/tilelink/AsyncCrossing.scala | 10 +++--- src/main/scala/tilelink/AtomicAutomata.scala | 12 ++++--- src/main/scala/tilelink/BankBinder.scala | 7 ++-- .../scala/tilelink/BlockDuringReset.scala | 6 ++-- src/main/scala/tilelink/Broadcast.scala | 16 ++++++--- src/main/scala/tilelink/Buffer.scala | 8 +++-- src/main/scala/tilelink/BusWrapper.scala | 25 +++++++++---- src/main/scala/tilelink/CacheCork.scala | 16 ++++++--- src/main/scala/tilelink/Credited.scala | 11 +++--- src/main/scala/tilelink/CrossingHelper.scala | 11 ++++-- src/main/scala/tilelink/Delayer.scala | 5 +-- src/main/scala/tilelink/ErrorEvaluator.scala | 11 ++++-- src/main/scala/tilelink/FIFOFixer.scala | 6 +++- src/main/scala/tilelink/Filter.scala | 7 ++-- src/main/scala/tilelink/Fragmenter.scala | 13 +++++-- src/main/scala/tilelink/Fuzzer.scala | 11 ++++-- src/main/scala/tilelink/HintHandler.scala | 9 +++-- src/main/scala/tilelink/Isolation.scala | 6 ++-- src/main/scala/tilelink/Jbar.scala | 5 ++- src/main/scala/tilelink/Map.scala | 7 ++-- src/main/scala/tilelink/Monitor.scala | 9 +++-- src/main/scala/tilelink/Nodes.scala | 7 ++-- src/main/scala/tilelink/Parameters.scala | 16 +++++++-- src/main/scala/tilelink/PatternPusher.scala | 10 +++--- src/main/scala/tilelink/ProbePicker.scala | 7 ++-- src/main/scala/tilelink/RAMModel.scala | 10 ++++-- .../scala/tilelink/RationalCrossing.scala | 12 +++++-- .../scala/tilelink/RegionReplication.scala | 6 +++- src/main/scala/tilelink/RegisterRouter.scala | 13 ++++--- .../scala/tilelink/RegisterRouterTest.scala | 8 +++-- src/main/scala/tilelink/SRAM.scala | 14 +++++--- src/main/scala/tilelink/SourceShrinker.scala | 11 ++++-- src/main/scala/tilelink/ToAHB.scala | 18 ++++++---- src/main/scala/tilelink/ToAPB.scala | 15 +++++--- src/main/scala/tilelink/ToAXI4.scala | 19 ++++++---- src/main/scala/tilelink/WidthWidget.scala | 11 +++--- src/main/scala/tilelink/Xbar.scala | 9 +++-- src/main/scala/tilelink/package.scala | 7 ++-- src/main/scala/unittest/TestGenerator.scala | 3 +- src/main/scala/util/Annotations.scala | 8 +++-- src/main/scala/util/PSDTestMode.scala | 4 ++- 128 files changed, 993 insertions(+), 514 deletions(-) diff --git a/src/main/scala/devices/debug/APB.scala b/src/main/scala/devices/debug/APB.scala index 8191bb65835..8397eae8fc2 100644 --- a/src/main/scala/devices/debug/APB.scala +++ b/src/main/scala/devices/debug/APB.scala @@ -1,10 +1,13 @@ // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug + import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.regmapper._ -import freechips.rocketchip.amba.apb.{APBRegisterNode} +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.amba.apb.APBRegisterNode +import freechips.rocketchip.diplomacy.AddressSet +import freechips.rocketchip.regmapper.RegField case object APBDebugRegistersKey extends Field[Map[Int, Seq[RegField]]](Map()) diff --git a/src/main/scala/devices/debug/Custom.scala b/src/main/scala/devices/debug/Custom.scala index 64e3f944ca0..b359c01be10 100644 --- a/src/main/scala/devices/debug/Custom.scala +++ b/src/main/scala/devices/debug/Custom.scala @@ -3,10 +3,13 @@ package freechips.rocketchip.devices.debug import chisel3._ +import chisel3.experimental._ import chisel3.util._ -import chisel3.experimental.SourceInfo -import freechips.rocketchip.diplomacy._ -import org.chipsalliance.cde.config.Parameters + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ +import org.chipsalliance.diplomacy.nodes._ case class DebugCustomParams( addrs: List[Int], diff --git a/src/main/scala/devices/debug/DMI.scala b/src/main/scala/devices/debug/DMI.scala index 014b838bfc6..eeffdc2917c 100644 --- a/src/main/scala/devices/debug/DMI.scala +++ b/src/main/scala/devices/debug/DMI.scala @@ -4,10 +4,13 @@ package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ + import org.chipsalliance.cde.config._ -import freechips.rocketchip.util._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.TransferSizes +import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters, TLMasterToSlaveTransferSizes} +import freechips.rocketchip.util.ParameterizedBundle /** Constant values used by both Debug Bus Response & Request */ diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index d8f8371fd79..23f06224c4d 100755 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -5,24 +5,28 @@ package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ + import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.regmapper._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.amba.apb.{APBFanout, APBToTL} +import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule} +import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError} +import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice} +import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode} +import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.rocket.{CSRs, Instructions} import freechips.rocketchip.tile.MaxHartIdBits -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ -import freechips.rocketchip.devices.debug.systembusaccess._ -import freechips.rocketchip.devices.tilelink.TLBusBypass -import freechips.rocketchip.amba.apb.{APBToTL, APBFanout} +import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar} +import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle} + +import freechips.rocketchip.util.SeqBoolBitwiseOps +import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.BooleanToAugmentedBoolean object DsbBusConsts { def sbAddrWidth = 12 - def sbIdWidth = 10 - + def sbIdWidth = 10 } object DsbRegAddrs{ diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index fcf5826dc0b..a7c1ea1d3f7 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -3,18 +3,21 @@ package freechips.rocketchip.devices.debug import chisel3._ -import chisel3.experimental.{IntParam, noPrefix} +import chisel3.experimental._ import chisel3.util._ -import chisel3.util.HasBlackBoxResource -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.amba.apb._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.jtag._ -import freechips.rocketchip.util._ -import freechips.rocketchip.prci.{ClockSinkParameters, ClockSinkNode} -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts.{NullIntSyncSource, IntSyncXbar} + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters} +import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource} +import freechips.rocketchip.jtag.JTAGIO +import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters} +import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation} +import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget} +import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg} + +import freechips.rocketchip.util.BooleanToAugmentedBoolean /** Protocols used for communicating with external debugging tools */ sealed trait DebugExportProtocol diff --git a/src/main/scala/devices/debug/SBA.scala b/src/main/scala/devices/debug/SBA.scala index f35b27ac05a..118b880b5e8 100644 --- a/src/main/scala/devices/debug/SBA.scala +++ b/src/main/scala/devices/debug/SBA.scala @@ -4,13 +4,16 @@ package freechips.rocketchip.devices.debug.systembusaccess import chisel3._ import chisel3.util._ -import freechips.rocketchip.amba._ + import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.regmapper._ -import freechips.rocketchip.tilelink._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} +import freechips.rocketchip.devices.debug.{DebugModuleKey, RWNotify, SBCSFields, WNotifyVal} +import freechips.rocketchip.diplomacy.TransferSizes +import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType} +import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters} import freechips.rocketchip.util.property -import freechips.rocketchip.devices.debug._ object SystemBusAccessState extends scala.Enumeration { type SystemBusAccessState = Value diff --git a/src/main/scala/devices/tilelink/BootROM.scala b/src/main/scala/devices/tilelink/BootROM.scala index 2bbcb16be97..a7af5079ffb 100644 --- a/src/main/scala/devices/tilelink/BootROM.scala +++ b/src/main/scala/devices/tilelink/BootROM.scala @@ -3,11 +3,15 @@ package freechips.rocketchip.devices.tilelink import chisel3._ -import chisel3.util.log2Ceil -import org.chipsalliance.cde.config.{Field, Parameters} +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, RegionType, Resource, SimpleDevice, TransferSizes} import freechips.rocketchip.subsystem._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ +import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters} import java.nio.ByteBuffer import java.nio.file.{Files, Paths} diff --git a/src/main/scala/devices/tilelink/BusBlocker.scala b/src/main/scala/devices/tilelink/BusBlocker.scala index e86505826c2..b17c4a76708 100644 --- a/src/main/scala/devices/tilelink/BusBlocker.scala +++ b/src/main/scala/devices/tilelink/BusBlocker.scala @@ -3,10 +3,13 @@ package freechips.rocketchip.devices.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp, SimpleDevice} + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc} -import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode, TLBusWrapper, TLNameNode, TLNode} +import freechips.rocketchip.tilelink.{TLBusWrapper, TLFragmenter, TLNameNode, TLNode, TLRegisterNode} /** Parameterize a BasicBusBlocker. * diff --git a/src/main/scala/devices/tilelink/CLINT.scala b/src/main/scala/devices/tilelink/CLINT.scala index 4b533d912f8..25263adc0c9 100644 --- a/src/main/scala/devices/tilelink/CLINT.scala +++ b/src/main/scala/devices/tilelink/CLINT.scala @@ -3,14 +3,17 @@ package freechips.rocketchip.devices.tilelink import chisel3._ -import chisel3.util.ShiftRegister -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.regmapper._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, Resource, SimpleDevice} +import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} +import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} +import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} +import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} +import freechips.rocketchip.util.Annotated object CLINTConsts { diff --git a/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala b/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala index 96ba3def845..6fad3f637d0 100644 --- a/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala +++ b/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala @@ -2,9 +2,11 @@ package freechips.rocketchip.devices.tilelink -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} +import freechips.rocketchip.tilelink.{HasTLBusParams, TLBuffer, TLCacheCork, TLCacheCorkParams, TLFragmenter, TLOutwardNode, TLTempNode} case class BuiltInZeroDeviceParams( addr: AddressSet, @@ -63,4 +65,3 @@ object BuiltInDevices { trait CanHaveBuiltInDevices { def builtInDevices: BuiltInDevices } - diff --git a/src/main/scala/devices/tilelink/ClockBlocker.scala b/src/main/scala/devices/tilelink/ClockBlocker.scala index 9076b6b08b0..866cbbebd7f 100644 --- a/src/main/scala/devices/tilelink/ClockBlocker.scala +++ b/src/main/scala/devices/tilelink/ClockBlocker.scala @@ -3,12 +3,14 @@ package freechips.rocketchip.devices.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.prci._ -import freechips.rocketchip.regmapper._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice} +import freechips.rocketchip.prci.ClockAdapterNode +import freechips.rocketchip.regmapper.{RegField, RegFieldDesc} +import freechips.rocketchip.tilelink.TLRegisterNode +import freechips.rocketchip.util.ClockGate /** This device extends a basic bus blocker by allowing it to gate the clocks of the device * whose tilelink port is being blocked. For now it is only possible to block diff --git a/src/main/scala/devices/tilelink/DevNull.scala b/src/main/scala/devices/tilelink/DevNull.scala index 8b2eab69901..2fd212526af 100644 --- a/src/main/scala/devices/tilelink/DevNull.scala +++ b/src/main/scala/devices/tilelink/DevNull.scala @@ -2,9 +2,13 @@ package freechips.rocketchip.devices.tilelink -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, HasClockDomainCrossing, RegionType, SimpleDevice, TransferSizes} +import freechips.rocketchip.tilelink.{TLManagerNode, TLSlaveParameters, TLSlavePortParameters} + +import freechips.rocketchip.tilelink.TLClockDomainCrossing case class DevNullParams( address: Seq[AddressSet], diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala index dd6541d20f8..4f0ab91e5ab 100644 --- a/src/main/scala/devices/tilelink/Error.scala +++ b/src/main/scala/devices/tilelink/Error.scala @@ -4,9 +4,12 @@ package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.SimpleDevice +import freechips.rocketchip.tilelink.{TLArbiter, TLMessages, TLPermissions} /** Adds a /dev/null slave that generates TL error response messages */ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) diff --git a/src/main/scala/devices/tilelink/MaskROM.scala b/src/main/scala/devices/tilelink/MaskROM.scala index f4169a85a84..dce6b19efee 100644 --- a/src/main/scala/devices/tilelink/MaskROM.scala +++ b/src/main/scala/devices/tilelink/MaskROM.scala @@ -4,11 +4,16 @@ package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, RegionType, SimpleDevice, TransferSizes} import freechips.rocketchip.subsystem.{Attachable, HierarchicalLocation, TLBusWrapperLocation} -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ +import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters, TLWidthWidget} +import freechips.rocketchip.util.{ROMConfig, ROMGenerator} + +import freechips.rocketchip.util.DataToAugmentedData case class MaskROMParams(address: BigInt, name: String, depth: Int = 2048, width: Int = 32) diff --git a/src/main/scala/devices/tilelink/MasterMux.scala b/src/main/scala/devices/tilelink/MasterMux.scala index 3ebedcde084..c1ddf82477b 100644 --- a/src/main/scala/devices/tilelink/MasterMux.scala +++ b/src/main/scala/devices/tilelink/MasterMux.scala @@ -3,9 +3,17 @@ package freechips.rocketchip.devices.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} +import freechips.rocketchip.tilelink.{ + LFSR64, TLBundleA, TLBundleC, TLBundleE, TLClientNode, TLCustomNode, TLFilter, TLFragmenter, + TLFuzzer, TLMasterParameters, TLMasterPortParameters, TLPermissions, TLRAM, TLRAMModel, + TLSlaveParameters, TLSlavePortParameters +} class MasterMuxNode(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(implicit valName: ValName) extends TLCustomNode { diff --git a/src/main/scala/devices/tilelink/PhysicalFilter.scala b/src/main/scala/devices/tilelink/PhysicalFilter.scala index 1c52bffca83..94fb61b706f 100644 --- a/src/main/scala/devices/tilelink/PhysicalFilter.scala +++ b/src/main/scala/devices/tilelink/PhysicalFilter.scala @@ -4,11 +4,15 @@ package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.regmapper._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice} +import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} +import freechips.rocketchip.tilelink.{TLAdapterNode, TLMessages, TLPermissions, TLRegisterNode} + +import freechips.rocketchip.util.DataToAugmentedData case class DevicePMPParams(addressBits: Int, pageBits: Int) diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala index 8d87e74f37b..ff632c6fc1c 100644 --- a/src/main/scala/devices/tilelink/Plic.scala +++ b/src/main/scala/devices/tilelink/Plic.scala @@ -3,19 +3,24 @@ package freechips.rocketchip.devices.tilelink import chisel3._ +import chisel3.experimental._ import chisel3.util._ -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.regmapper._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ -import freechips.rocketchip.util.property -import chisel3.experimental.SourceInfo + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice} +import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} +import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn} +import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} +import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} +import freechips.rocketchip.util.{Annotated, MuxT, property} import scala.math.min +import freechips.rocketchip.util.UIntToAugmentedUInt +import freechips.rocketchip.util.SeqToAugmentedSeq + class GatewayPLICIO extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) diff --git a/src/main/scala/devices/tilelink/TestRAM.scala b/src/main/scala/devices/tilelink/TestRAM.scala index 9fcb9a02d12..a209cfa90f2 100644 --- a/src/main/scala/devices/tilelink/TestRAM.scala +++ b/src/main/scala/devices/tilelink/TestRAM.scala @@ -4,9 +4,12 @@ package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, MemoryDevice, RegionType, TransferSizes} +import freechips.rocketchip.tilelink.{TLDelayer, TLFuzzer, TLManagerNode, TLMessages, TLRAMModel, TLSlaveParameters, TLSlavePortParameters} // Do not use this for synthesis! Only for simulation. class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, trackCorruption: Boolean = true)(implicit p: Parameters) extends LazyModule diff --git a/src/main/scala/devices/tilelink/Zero.scala b/src/main/scala/devices/tilelink/Zero.scala index 2d542b99b86..8a7d0b1d843 100644 --- a/src/main/scala/devices/tilelink/Zero.scala +++ b/src/main/scala/devices/tilelink/Zero.scala @@ -4,8 +4,11 @@ package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, RegionType, SimpleDevice} import freechips.rocketchip.tilelink.TLMessages /** This /dev/null device accepts single beat gets/puts, as well as atomics. diff --git a/src/main/scala/examples/ExampleDevice.scala b/src/main/scala/examples/ExampleDevice.scala index ffdb69f8d2c..7358c6bdcdd 100644 --- a/src/main/scala/examples/ExampleDevice.scala +++ b/src/main/scala/examples/ExampleDevice.scala @@ -3,10 +3,12 @@ package freechips.rocketchip.examples import chisel3._ -import org.chipsalliance.cde.config.Parameters + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.amba.ahb.HasAHBControlRegMap import freechips.rocketchip.amba.axi4.HasAXI4ControlRegMap -import freechips.rocketchip.diplomacy.LazyModuleImp import freechips.rocketchip.interrupts.HasInterruptSources import freechips.rocketchip.tilelink.HasTLControlRegMap import freechips.rocketchip.regmapper.{IORegisterRouter, RegisterRouterParams, RegField, RegFieldDesc} diff --git a/src/main/scala/formal/FormalUtils.scala b/src/main/scala/formal/FormalUtils.scala index 2df69574d58..07922d789fc 100644 --- a/src/main/scala/formal/FormalUtils.scala +++ b/src/main/scala/formal/FormalUtils.scala @@ -2,9 +2,10 @@ package freechips.rocketchip.formal import chisel3._ -import chisel3.util._ import chisel3.experimental.{SourceInfo, SourceLine} -import org.chipsalliance.cde.config.Field +import chisel3.util._ + +import org.chipsalliance.cde.config._ sealed abstract class MonitorDirection(name: String) { override def toString: String = name diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index cf7a283e732..997abc2e52d 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -3,7 +3,8 @@ package freechips.rocketchip.groundtest -import org.chipsalliance.cde.config.Config +import org.chipsalliance.cde.config._ + import freechips.rocketchip.devices.tilelink.{CLINTKey, PLICKey} import freechips.rocketchip.devices.debug.{DebugModuleKey} import freechips.rocketchip.subsystem._ diff --git a/src/main/scala/groundtest/DummyPTW.scala b/src/main/scala/groundtest/DummyPTW.scala index ce95b826d83..4dadd95a739 100644 --- a/src/main/scala/groundtest/DummyPTW.scala +++ b/src/main/scala/groundtest/DummyPTW.scala @@ -4,9 +4,9 @@ package freechips.rocketchip.groundtest import chisel3._ -import chisel3.util.{RRArbiter, Valid, log2Up, RegEnable} +import chisel3.util._ -import org.chipsalliance.cde.config.Parameters +import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tile.CoreModule import freechips.rocketchip.util.ParameterizedBundle diff --git a/src/main/scala/groundtest/GroundTestSubsystem.scala b/src/main/scala/groundtest/GroundTestSubsystem.scala index 09f5c733929..11263966ebf 100644 --- a/src/main/scala/groundtest/GroundTestSubsystem.scala +++ b/src/main/scala/groundtest/GroundTestSubsystem.scala @@ -3,8 +3,12 @@ package freechips.rocketchip.groundtest import chisel3._ -import org.chipsalliance.cde.config.{Parameters} -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.AddressSet + import freechips.rocketchip.interrupts._ import freechips.rocketchip.tile.{NMI} import freechips.rocketchip.devices.tilelink.{CLINTConsts} diff --git a/src/main/scala/groundtest/TestHarness.scala b/src/main/scala/groundtest/TestHarness.scala index 2db67efbee7..348df5beb50 100644 --- a/src/main/scala/groundtest/TestHarness.scala +++ b/src/main/scala/groundtest/TestHarness.scala @@ -3,8 +3,10 @@ package freechips.rocketchip.groundtest import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy.LazyModule + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.system.SimAXIMem class TestHarness(implicit p: Parameters) extends Module { diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala index de84bed5645..6ce5d1f44a3 100644 --- a/src/main/scala/groundtest/Tile.scala +++ b/src/main/scala/groundtest/Tile.scala @@ -4,8 +4,12 @@ package freechips.rocketchip.groundtest import chisel3._ + import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{ClockCrossingType, SimpleDevice} import freechips.rocketchip.interrupts._ import freechips.rocketchip.rocket.{BuildHellaCache, DCache, DCacheModule, ICacheParams, NonBlockingDCache, NonBlockingDCacheModule, RocketCoreParams} import freechips.rocketchip.tile._ diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala index a41c55007b5..130dd80a72a 100644 --- a/src/main/scala/groundtest/TraceGen.scala +++ b/src/main/scala/groundtest/TraceGen.scala @@ -20,9 +20,11 @@ package freechips.rocketchip.groundtest import chisel3._ -import chisel3.util.{log2Up, MuxLookup, Cat, log2Ceil, Enum} -import org.chipsalliance.cde.config.{Parameters} -import freechips.rocketchip.diplomacy.{ClockCrossingType} +import chisel3.util._ + +import org.chipsalliance.cde.config._ + +import freechips.rocketchip.diplomacy.ClockCrossingType import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ diff --git a/src/main/scala/interrupts/BlockDuringReset.scala b/src/main/scala/interrupts/BlockDuringReset.scala index 35692c57360..a94c295b062 100644 --- a/src/main/scala/interrupts/BlockDuringReset.scala +++ b/src/main/scala/interrupts/BlockDuringReset.scala @@ -2,8 +2,9 @@ package freechips.rocketchip.interrupts -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.util.BlockDuringReset /** BlockDuringReset ensures that no interrupt is raised while reset is raised. */ diff --git a/src/main/scala/interrupts/Crossing.scala b/src/main/scala/interrupts/Crossing.scala index b113dfdc538..79260aa1c34 100644 --- a/src/main/scala/interrupts/Crossing.scala +++ b/src/main/scala/interrupts/Crossing.scala @@ -4,9 +4,10 @@ package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} -import freechips.rocketchip.diplomacy._ @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule diff --git a/src/main/scala/interrupts/CrossingHelper.scala b/src/main/scala/interrupts/CrossingHelper.scala index 814e13fe39b..3270b0fc58b 100644 --- a/src/main/scala/interrupts/CrossingHelper.scala +++ b/src/main/scala/interrupts/CrossingHelper.scala @@ -2,8 +2,10 @@ package freechips.rocketchip.interrupts -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{CrossingType, ClockCrossingType, NoCrossing, AsynchronousCrossing, RationalCrossing, SynchronousCrossing, CreditedCrossing} import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing} import freechips.rocketchip.util.CreditedDelay diff --git a/src/main/scala/interrupts/Nodes.scala b/src/main/scala/interrupts/Nodes.scala index 25a5cd48354..d2b18122f96 100644 --- a/src/main/scala/interrupts/Nodes.scala +++ b/src/main/scala/interrupts/Nodes.scala @@ -4,8 +4,10 @@ package freechips.rocketchip.interrupts import chisel3._ import chisel3.experimental.SourceInfo -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.nodes._ object IntImp extends SimpleNodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, Vec[Bool]] { diff --git a/src/main/scala/interrupts/NullIntSource.scala b/src/main/scala/interrupts/NullIntSource.scala index ec2528aa70b..dc388960313 100644 --- a/src/main/scala/interrupts/NullIntSource.scala +++ b/src/main/scala/interrupts/NullIntSource.scala @@ -3,8 +3,9 @@ package freechips.rocketchip.interrupts import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ /** Useful for stubbing out parts of an interrupt interface where certain devices might be missing */ class NullIntSource(num: Int = 1, ports: Int = 1, sources: Int = 1)(implicit p: Parameters) extends LazyModule diff --git a/src/main/scala/interrupts/Parameters.scala b/src/main/scala/interrupts/Parameters.scala index d1c300241cf..e6a86e41ace 100644 --- a/src/main/scala/interrupts/Parameters.scala +++ b/src/main/scala/interrupts/Parameters.scala @@ -3,8 +3,11 @@ package freechips.rocketchip.interrupts import chisel3.experimental.SourceInfo -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.Resource // A potentially empty half-open range; [start, end) case class IntRange(start: Int, end: Int) diff --git a/src/main/scala/interrupts/RegisterRouter.scala b/src/main/scala/interrupts/RegisterRouter.scala index 419ec135d27..7a74b8f73c1 100644 --- a/src/main/scala/interrupts/RegisterRouter.scala +++ b/src/main/scala/interrupts/RegisterRouter.scala @@ -3,7 +3,11 @@ package freechips.rocketchip.interrupts import chisel3._ -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.Resource + import freechips.rocketchip.regmapper._ /** Mix this trait into a RegisterRouter to be able to attach its interrupt sources to an interrupt bus */ diff --git a/src/main/scala/interrupts/Xbar.scala b/src/main/scala/interrupts/Xbar.scala index b2560106b61..d9f72e27485 100644 --- a/src/main/scala/interrupts/Xbar.scala +++ b/src/main/scala/interrupts/Xbar.scala @@ -2,8 +2,8 @@ package freechips.rocketchip.interrupts -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ class IntXbar()(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/interrupts/package.scala b/src/main/scala/interrupts/package.scala index a29898210ba..7b92a3bb7ee 100644 --- a/src/main/scala/interrupts/package.scala +++ b/src/main/scala/interrupts/package.scala @@ -2,9 +2,13 @@ package freechips.rocketchip -import chisel3.{Bool, Vec} -import freechips.rocketchip.diplomacy.{HasClockDomainCrossing, _} -import freechips.rocketchip.prci.{HasResetDomainCrossing} +import chisel3._ + +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.HasClockDomainCrossing +import freechips.rocketchip.prci.HasResetDomainCrossing package object interrupts { diff --git a/src/main/scala/prci/BundleBridgeBlockDuringReset.scala b/src/main/scala/prci/BundleBridgeBlockDuringReset.scala index 88baf78bfba..7bb37f98ace 100644 --- a/src/main/scala/prci/BundleBridgeBlockDuringReset.scala +++ b/src/main/scala/prci/BundleBridgeBlockDuringReset.scala @@ -3,9 +3,13 @@ package freechips.rocketchip.prci import chisel3._ -import org.chipsalliance.cde.config.{Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.diplomacy.BundleBridgeNexus.fillN + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import org.chipsalliance.diplomacy.bundlebridge.BundleBridgeNexus.fillN + import freechips.rocketchip.util.{BlockDuringReset, Blockable} object BundleBridgeBlockDuringReset { diff --git a/src/main/scala/prci/ClockDivider.scala b/src/main/scala/prci/ClockDivider.scala index ceb91078f73..8c913f04c8c 100644 --- a/src/main/scala/prci/ClockDivider.scala +++ b/src/main/scala/prci/ClockDivider.scala @@ -2,9 +2,11 @@ package freechips.rocketchip.prci import chisel3._ -import chisel3.util.isPow2 -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.util.{ClockDivider3, Pow2ClockDivider} /* An example clock adapter that divides all clocks passed through this node by an integer factor diff --git a/src/main/scala/prci/ClockDomain.scala b/src/main/scala/prci/ClockDomain.scala index 7bc10c69470..8304d6178af 100644 --- a/src/main/scala/prci/ClockDomain.scala +++ b/src/main/scala/prci/ClockDomain.scala @@ -1,8 +1,12 @@ package freechips.rocketchip.prci import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ + +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{HasClockDomainCrossing, HasDomainCrossing} abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { diff --git a/src/main/scala/prci/ClockGroup.scala b/src/main/scala/prci/ClockGroup.scala index f4c648bafe2..2c7d879a594 100644 --- a/src/main/scala/prci/ClockGroup.scala +++ b/src/main/scala/prci/ClockGroup.scala @@ -1,8 +1,12 @@ // See LICENSE.SiFive for license details. package freechips.rocketchip.prci -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( diff --git a/src/main/scala/prci/ClockNodes.scala b/src/main/scala/prci/ClockNodes.scala index 16a9e01c894..08697e5aeb8 100644 --- a/src/main/scala/prci/ClockNodes.scala +++ b/src/main/scala/prci/ClockNodes.scala @@ -2,8 +2,14 @@ package freechips.rocketchip.prci import chisel3.experimental.SourceInfo -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ + +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.FixedClockResource object ClockImp extends SimpleNodeImp[ClockSourceParameters, ClockSinkParameters, ClockEdgeParameters, ClockBundle] { diff --git a/src/main/scala/prci/IOHelper.scala b/src/main/scala/prci/IOHelper.scala index e33e618103b..b176ee9722a 100644 --- a/src/main/scala/prci/IOHelper.scala +++ b/src/main/scala/prci/IOHelper.scala @@ -3,7 +3,10 @@ package freechips.rocketchip.prci import chisel3._ -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{ClockCrossingType, SynchronousCrossing} object IOHelper { diff --git a/src/main/scala/prci/ResetCrossingType.scala b/src/main/scala/prci/ResetCrossingType.scala index dd37db2ee9d..4147196be9f 100644 --- a/src/main/scala/prci/ResetCrossingType.scala +++ b/src/main/scala/prci/ResetCrossingType.scala @@ -1,8 +1,10 @@ // See LICENSE.SiFive for license details. package freechips.rocketchip.prci -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy.{CrossingType, HasDomainCrossing, LazyModule} +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{CrossingType, HasDomainCrossing} trait HasResetDomainCrossing extends HasDomainCrossing { this: LazyModule => type DomainCrossingType = ResetCrossingType diff --git a/src/main/scala/prci/ResetStretcher.scala b/src/main/scala/prci/ResetStretcher.scala index 747e93281fa..03956fa1e4b 100644 --- a/src/main/scala/prci/ResetStretcher.scala +++ b/src/main/scala/prci/ResetStretcher.scala @@ -2,9 +2,10 @@ package freechips.rocketchip.prci import chisel3._ -import chisel3.util.log2Ceil -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, ValName} +import chisel3.util._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ /** This adapter takes an input reset and stretches it. * diff --git a/src/main/scala/prci/ResetSynchronizer.scala b/src/main/scala/prci/ResetSynchronizer.scala index 9bb6c5aea31..c66ce4576a7 100644 --- a/src/main/scala/prci/ResetSynchronizer.scala +++ b/src/main/scala/prci/ResetSynchronizer.scala @@ -1,9 +1,11 @@ // See LICENSE for license details. package freechips.rocketchip.prci -import org.chipsalliance.cde.config.{Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util.{ResetCatchAndSync} +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.util.ResetCatchAndSync /** * Synchronizes the reset of a diplomatic clock-reset pair to its accompanying clock. diff --git a/src/main/scala/prci/ResetWrangler.scala b/src/main/scala/prci/ResetWrangler.scala index 3f59bc3d183..59b289bc3e6 100644 --- a/src/main/scala/prci/ResetWrangler.scala +++ b/src/main/scala/prci/ResetWrangler.scala @@ -4,8 +4,9 @@ package freechips.rocketchip.prci import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.util.{AsyncResetReg, ResetCatchAndSync} class ResetWrangler(debounceNs: Double = 100000)(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/prci/TestClockSource.scala b/src/main/scala/prci/TestClockSource.scala index 440c77f893e..6889908b0d2 100644 --- a/src/main/scala/prci/TestClockSource.scala +++ b/src/main/scala/prci/TestClockSource.scala @@ -1,10 +1,11 @@ package freechips.rocketchip.prci import chisel3._ -import chisel3.util.HasBlackBoxInline +import chisel3.util._ import chisel3.experimental.DoubleParam -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ class ClockSourceIO extends Bundle { val power = Input(Bool()) diff --git a/src/main/scala/prci/package.scala b/src/main/scala/prci/package.scala index 864126a03f2..13e09161ebf 100644 --- a/src/main/scala/prci/package.scala +++ b/src/main/scala/prci/package.scala @@ -2,7 +2,9 @@ package freechips.rocketchip -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.{ClockCrossingType, AsynchronousCrossing} package object prci { diff --git a/src/main/scala/regmapper/RegMapper.scala b/src/main/scala/regmapper/RegMapper.scala index 78361ef9406..b892cc866f6 100644 --- a/src/main/scala/regmapper/RegMapper.scala +++ b/src/main/scala/regmapper/RegMapper.scala @@ -4,13 +4,13 @@ package freechips.rocketchip.regmapper import chisel3._ import chisel3.experimental.SourceInfo -import chisel3.util.{DecoupledIO, Decoupled, Queue, Cat, FillInterleaved, UIntToOH} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ -import freechips.rocketchip.util.property +import chisel3.util._ -// A bus agnostic register interface to a register-based device +import freechips.rocketchip.diplomacy.AddressDecoder + +import freechips.rocketchip.util.{BundleFieldBase, BundleMap, MuxSeq, ReduceOthers, property} +// A bus agnostic register interface to a register-based device case class RegMapperParams(indexBits: Int, maskBits: Int, extraFields: Seq[BundleFieldBase] = Nil) class RegMapperInput(val params: RegMapperParams) extends Bundle diff --git a/src/main/scala/regmapper/RegisterRouter.scala b/src/main/scala/regmapper/RegisterRouter.scala index 0bd43a7fd06..f6c8e680201 100644 --- a/src/main/scala/regmapper/RegisterRouter.scala +++ b/src/main/scala/regmapper/RegisterRouter.scala @@ -3,9 +3,13 @@ package freechips.rocketchip.regmapper import chisel3._ -import chisel3.util.{isPow2} -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, Description, Device, SimpleDevice, ResourceBindings, ResourceValue, HasClockDomainCrossing} /** Parameters which apply to any RegisterRouter. */ case class RegisterRouterParams( diff --git a/src/main/scala/regmapper/Test.scala b/src/main/scala/regmapper/Test.scala index 57c5c7ec583..0faedd84cfb 100644 --- a/src/main/scala/regmapper/Test.scala +++ b/src/main/scala/regmapper/Test.scala @@ -3,10 +3,12 @@ package freechips.rocketchip.regmapper import chisel3._ -import chisel3.util.{Cat, log2Ceil} -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy.LazyModuleImp -import freechips.rocketchip.util.{Pow2ClockDivider} +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.util.Pow2ClockDivider object LFSR16Seed { diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 232c7b68cfd..c2dc4843b98 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -4,16 +4,23 @@ package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ -import freechips.rocketchip.amba._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ -import freechips.rocketchip.util.property -import chisel3.{DontCare, WireInit, dontTouch, withClock} import chisel3.experimental.SourceInfo -import TLMessages._ + +import org.chipsalliance.cde.config._ + +import freechips.rocketchip.amba.AMBAProt +import freechips.rocketchip.diplomacy.{ClockCrossingType, RationalCrossing, SynchronousCrossing, BufferParams, AsynchronousCrossing, CreditedCrossing} +import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} +import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions} +import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck} +import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property} + +import freechips.rocketchip.util.BooleanToAugmentedBoolean +import freechips.rocketchip.util.UIntToAugmentedUInt +import freechips.rocketchip.util.UIntIsOneOf +import freechips.rocketchip.util.IntToAugmentedInt +import freechips.rocketchip.util.SeqToAugmentedSeq +import freechips.rocketchip.util.SeqBoolBitwiseOps // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits trait InlineInstance { self: chisel3.experimental.BaseModule => diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index 30297c5033c..760b15196fd 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -5,14 +5,17 @@ package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ -import chisel3.{withClock,withReset} import chisel3.experimental.SourceInfo + import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink.{TLWidthWidget} -import freechips.rocketchip.util._ -import freechips.rocketchip.util.property +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.tile.{CoreBundle, BaseTile} +import freechips.rocketchip.tilelink.{TLWidthWidget, TLEdgeOut} +import freechips.rocketchip.util.{ClockGate, ShiftQueue, property} + +import freechips.rocketchip.util.UIntToAugmentedUInt class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) { val pc = UInt(vaddrBitsExtended.W) @@ -80,7 +83,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) with HasL1ICacheParameters { val io = IO(new FrontendBundle(outer)) val io_reset_vector = outer.resetVectorSinkNode.bundle - implicit val edge = outer.masterNode.edges.out(0) + implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0) val icache = outer.icache.module require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes) diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index cdad4b8e13b..f0d7bdf8d0b 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -3,15 +3,21 @@ package freechips.rocketchip.rocket -import chisel3._ -import chisel3.util.{isPow2,log2Ceil,log2Up,Decoupled,Valid} -import chisel3.dontTouch -import freechips.rocketchip.amba._ -import org.chipsalliance.cde.config.{Parameters, Field} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ +import chisel3.{dontTouch, _} +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.amba.AMBAProtField +import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} +import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} +import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} +import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} + +import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} + import scala.collection.mutable.ListBuffer case class DCacheParams( @@ -231,7 +237,7 @@ class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { - implicit val edge = outer.node.edges.out(0) + implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 3090ca4f99d..f94e145472c 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -3,18 +3,25 @@ package freechips.rocketchip.rocket -import chisel3._ -import chisel3.util.{Cat, Decoupled, Mux1H, OHToUInt, RegEnable, Valid, isPow2, log2Ceil, log2Up, PopCount} -import freechips.rocketchip.amba._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util.{DescribedSRAM, _} -import freechips.rocketchip.util.property -import chisel3.experimental.SourceInfo -import chisel3.dontTouch +import chisel3.{dontTouch, _} +import chisel3.util._ import chisel3.util.random.LFSR +import chisel3.experimental.SourceInfo + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} +import freechips.rocketchip.diplomacy.{IdRange, SimpleDevice, ResourceBindings, Description, AddressSet, Binding, ResourceAddress, ResourceString, ResourceValue, RegionType, TransferSizes} +import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, TileKey, LookupByHartId} +import freechips.rocketchip.tilelink.{TLClientNode, TLMasterPortParameters, TLManagerNode, TLSlavePortParameters, TLSlaveParameters, TLMasterParameters, TLHints} +import freechips.rocketchip.util.{Code, CanHaveErrors, DescribedSRAM, RandomReplacement, Split, IdentityCode, property} + +import freechips.rocketchip.util.BooleanToAugmentedBoolean +import freechips.rocketchip.util.UIntToAugmentedUInt +import freechips.rocketchip.util.SeqToAugmentedSeq +import freechips.rocketchip.util.OptionUIntToAugmentedOptionUInt /** Parameter of [[ICache]]. * diff --git a/src/main/scala/rocket/PMA.scala b/src/main/scala/rocket/PMA.scala index 5ebbaa6fd61..b2144e6b38a 100644 --- a/src/main/scala/rocket/PMA.scala +++ b/src/main/scala/rocket/PMA.scala @@ -5,16 +5,15 @@ package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ +import chisel3.experimental.SourceInfo -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.subsystem.CacheBlockBytes +import org.chipsalliance.cde.config._ + +import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType +import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ -import freechips.rocketchip.util.property -import freechips.rocketchip.devices.debug.DebugModuleKey -import chisel3.experimental.SourceInfo +import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters} class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index a2a0b9d37f5..64ce50c0b70 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -4,10 +4,16 @@ package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes, SimpleDevice} + +import freechips.rocketchip.tilelink.{TLManagerNode, TLSlavePortParameters, TLSlaveParameters, TLBundleA, TLMessages, TLAtomics} + +import freechips.rocketchip.util.UIntIsOneOf +import freechips.rocketchip.util.DataToAugmentedData /* This adapter converts between diplomatic TileLink and non-diplomatic HellaCacheIO */ class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAtomics: Boolean)(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index faa2521b0d1..27ef9f008b0 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -5,16 +5,23 @@ package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ +import chisel3.experimental.SourceInfo -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.subsystem.CacheBlockBytes +import org.chipsalliance.cde.config._ + +import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType +import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ -import freechips.rocketchip.util.property -import freechips.rocketchip.devices.debug.DebugModuleKey -import chisel3.experimental.SourceInfo +import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} + +import freechips.rocketchip.util.BooleanToAugmentedBoolean +import freechips.rocketchip.util.IntToAugmentedInt +import freechips.rocketchip.util.UIntToAugmentedUInt +import freechips.rocketchip.util.UIntIsOneOf +import freechips.rocketchip.util.SeqToAugmentedSeq +import freechips.rocketchip.util.SeqBoolBitwiseOps case object PgLevels extends Field[Int](2) case object ASIdBits extends Field[Int](0) diff --git a/src/main/scala/rocket/TLBPermissions.scala b/src/main/scala/rocket/TLBPermissions.scala index 28df63183b7..899bc7c33ca 100644 --- a/src/main/scala/rocket/TLBPermissions.scala +++ b/src/main/scala/rocket/TLBPermissions.scala @@ -3,10 +3,10 @@ package freechips.rocketchip.rocket import chisel3._ -import chisel3.util.isPow2 +import chisel3.util._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ +import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} +import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined diff --git a/src/main/scala/subsystem/Attachable.scala b/src/main/scala/subsystem/Attachable.scala index 06f2269421f..9f3f720a04a 100644 --- a/src/main/scala/subsystem/Attachable.scala +++ b/src/main/scala/subsystem/Attachable.scala @@ -2,8 +2,9 @@ package freechips.rocketchip.subsystem -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy.{LazyModule, LazyScope} +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.prci.ClockGroupNode import freechips.rocketchip.tilelink.TLBusWrapper import freechips.rocketchip.util.{Location, LocationMap} diff --git a/src/main/scala/subsystem/BankedCoherenceParams.scala b/src/main/scala/subsystem/BankedCoherenceParams.scala index 84a7d015c37..235cd1eebbd 100644 --- a/src/main/scala/subsystem/BankedCoherenceParams.scala +++ b/src/main/scala/subsystem/BankedCoherenceParams.scala @@ -2,13 +2,21 @@ package freechips.rocketchip.subsystem -import chisel3.util.isPow2 +import chisel3.util._ + import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.devices.tilelink.BuiltInDevices -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ +import freechips.rocketchip.diplomacy.AddressSet +import freechips.rocketchip.interrupts.IntOutwardNode +import freechips.rocketchip.tilelink.{ + TLBroadcast, HasTLBusParams, BroadcastFilter, TLBusWrapper, TLBusWrapperInstantiationLike, + TLJbar, TLEdge, TLOutwardNode, TLTempNode, TLInwardNode, BankBinder, TLBroadcastParams, + TLBroadcastControlParams, TLBuffer, TLFragmenter, TLNameNode +} +import freechips.rocketchip.util.Location + import CoherenceManagerWrapper._ /** Global cache coherence granularity, which applies to all caches, for now. */ diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala index f3290acbb53..fc8e3513452 100644 --- a/src/main/scala/subsystem/BaseSubsystem.scala +++ b/src/main/scala/subsystem/BaseSubsystem.scala @@ -2,13 +2,20 @@ package freechips.rocketchip.subsystem -import chisel3.{Flipped, IO} +import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.prci._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{ + BindingScope, DTS, DTB, ResourceBinding, JSON, ResourceInt, + DTSModel, DTSCompat, DTSTimebase, ResourceString, Resource, + ResourceAnchors, AddressMapEntry, AddressRange +} +import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockGroupAggregator, ClockGroupSourceNode, ClockGroupSourceParameters} import freechips.rocketchip.tilelink.TLBusWrapper -import freechips.rocketchip.util._ +import freechips.rocketchip.util.{Location, ElaborationArtefacts, PlusArgArtefacts, RecordMap, Annotated} case object SubsystemDriveClockGroupsFromIO extends Field[Boolean](true) case class TLNetworkTopologyLocated(where: HierarchicalLocation) extends Field[Seq[CanInstantiateWithinContextThatHasTileLinkLocations with CanConnectWithinContextThatHasTileLinkLocations]] diff --git a/src/main/scala/subsystem/BusTopology.scala b/src/main/scala/subsystem/BusTopology.scala index a9d77b5b127..aadc6858c75 100644 --- a/src/main/scala/subsystem/BusTopology.scala +++ b/src/main/scala/subsystem/BusTopology.scala @@ -2,9 +2,11 @@ package freechips.rocketchip.subsystem -import org.chipsalliance.cde.config.Field -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.{ClockCrossingType, NoCrossing, SynchronousCrossing} +import freechips.rocketchip.tilelink.{TLBusWrapper, TLBusWrapperTopology, TLBusWrapperConnection} import freechips.rocketchip.util.Location // These fields control parameters of the five traditional tilelink bus wrappers. diff --git a/src/main/scala/subsystem/Cluster.scala b/src/main/scala/subsystem/Cluster.scala index 7e2ca886a17..3e63ba31f77 100644 --- a/src/main/scala/subsystem/Cluster.scala +++ b/src/main/scala/subsystem/Cluster.scala @@ -3,16 +3,18 @@ package freechips.rocketchip.subsystem import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.prci._ -import freechips.rocketchip.tile.{RocketTile, NMI, TraceBundle} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tilelink._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.devices.debug.{TLDebugModule} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.util._ +import freechips.rocketchip.diplomacy.{ClockCrossingType, NoCrossing, FlipRendering} +import freechips.rocketchip.interrupts.{IntIdentityNode, IntSyncIdentityNode, NullIntSource} +import freechips.rocketchip.prci.{ClockSinkParameters, ClockGroupIdentityNode, BundleBridgeBlockDuringReset} +import freechips.rocketchip.tile.{RocketTile, NMI, TraceBundle} +import freechips.rocketchip.tilelink.TLWidthWidget +import freechips.rocketchip.util.TraceCoreInterface + import scala.collection.immutable.SortedMap case class ClustersLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachCluster]](Nil) diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala index 5e232cac639..273ad9c069c 100644 --- a/src/main/scala/subsystem/Configs.scala +++ b/src/main/scala/subsystem/Configs.scala @@ -4,13 +4,23 @@ package freechips.rocketchip.subsystem import chisel3.util._ + import org.chipsalliance.cde.config._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.util._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.devices.debug.{DebugModuleKey, DefaultDebugModuleParams, ExportDebug, JTAG, APB} +import freechips.rocketchip.devices.tilelink.{ + BuiltInErrorDeviceParams, BootROMLocated, BootROMParams, CLINTKey, DevNullDevice, CLINTParams, PLICKey, PLICParams, DevNullParams +} +import freechips.rocketchip.diplomacy.{ + AddressSet, SynchronousCrossing, AsynchronousCrossing, RationalCrossing, MonitorsEnabled, + DTSModel, DTSCompat, DTSTimebase, ClockCrossingType, BigIntHexContext +} +import freechips.rocketchip.rocket.{PgLevels, RocketCoreParams, MulDivParams, DCacheParams, ICacheParams, BTBParams, DebugROBParams} +import freechips.rocketchip.tile.{ + XLen, MaxHartIdBits, RocketTileParams, BuildRoCC, AccumulatorExample, OpcodeSet, TranslatorExample, CharacterCountExample, BlackBoxExample +} +import freechips.rocketchip.util.ClockGateModelFile class BaseSubsystemConfig extends Config ((site, here, up) => { // Tile parameters diff --git a/src/main/scala/subsystem/CrossingWrapper.scala b/src/main/scala/subsystem/CrossingWrapper.scala index 435a90a7b74..518dd003c1d 100644 --- a/src/main/scala/subsystem/CrossingWrapper.scala +++ b/src/main/scala/subsystem/CrossingWrapper.scala @@ -2,13 +2,20 @@ package freechips.rocketchip.subsystem -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.interrupts._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.amba.axi4.{AXI4InwardNode, AXI4OutwardNode} +import freechips.rocketchip.diplomacy.{ClockCrossingType, HasClockDomainCrossing} +import freechips.rocketchip.tilelink.{TLInwardNode, TLOutwardNode} +import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode} import freechips.rocketchip.prci.{HasResetDomainCrossing, ResetCrossingType} +import freechips.rocketchip.tilelink.TLClockDomainCrossing +import freechips.rocketchip.tilelink.TLResetDomainCrossing +import freechips.rocketchip.interrupts.IntClockDomainCrossing +import freechips.rocketchip.interrupts.IntResetDomainCrossing + @deprecated("Only use this trait if you are confident you island will only ever be crossed to a single clock", "rocket-chip 1.3") trait HasCrossing extends CrossesToOnlyOneClockDomain { this: LazyModule => } diff --git a/src/main/scala/subsystem/FrontBus.scala b/src/main/scala/subsystem/FrontBus.scala index 001af15452e..e968246a130 100644 --- a/src/main/scala/subsystem/FrontBus.scala +++ b/src/main/scala/subsystem/FrontBus.scala @@ -2,10 +2,11 @@ package freechips.rocketchip.subsystem -import org.chipsalliance.cde.config.{Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.devices.tilelink.{BuiltInErrorDeviceParams, BuiltInZeroDeviceParams, BuiltInDevices, HasBuiltInDeviceParams} +import freechips.rocketchip.tilelink.{HasTLBusParams, TLBusWrapper, TLBusWrapperInstantiationLike, HasTLXbarPhy} import freechips.rocketchip.util.{Location} case class FrontBusParams( diff --git a/src/main/scala/subsystem/HasHierarchicalElements.scala b/src/main/scala/subsystem/HasHierarchicalElements.scala index 63f2ff14f18..ffb30d51e95 100644 --- a/src/main/scala/subsystem/HasHierarchicalElements.scala +++ b/src/main/scala/subsystem/HasHierarchicalElements.scala @@ -3,17 +3,24 @@ package freechips.rocketchip.subsystem import chisel3._ -import chisel3.dontTouch -import org.chipsalliance.cde.config.{Field, Parameters} + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.devices.debug.{TLDebugModule, HasPeripheryDebug} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ +import freechips.rocketchip.devices.tilelink.{BasicBusBlocker, BasicBusBlockerParams, CLINT, TLPLIC, CLINTConsts} +import freechips.rocketchip.diplomacy.ClockCrossingType +import freechips.rocketchip.interrupts.{ + IntNode, IntSyncNode, IntEphemeralNode, NullIntSource, IntNexusNode, IntSourcePortParameters, + IntSourceParameters, IntSinkPortParameters, IntSinkParameters, IntSyncIdentityNode, NullIntSyncSource +} +import freechips.rocketchip.tile.{TileParams, TilePRCIDomain, BaseTile, NMI, TraceBundle} +import freechips.rocketchip.tilelink.{TLNode, TLBuffer, TLCacheCork, TLTempNode, TLFragmenter} import freechips.rocketchip.prci.{ClockGroup, ResetCrossingType, ClockGroupNode, ClockDomain} -import freechips.rocketchip.util._ -import freechips.rocketchip.rocket.{TracedInstruction} +import freechips.rocketchip.rocket.TracedInstruction +import freechips.rocketchip.util.TraceCoreInterface + import scala.collection.immutable.SortedMap /** A default implementation of parameterizing the connectivity of the port where the tile is the master. diff --git a/src/main/scala/subsystem/HasTiles.scala b/src/main/scala/subsystem/HasTiles.scala index ff06ccff4a6..40b201db46e 100644 --- a/src/main/scala/subsystem/HasTiles.scala +++ b/src/main/scala/subsystem/HasTiles.scala @@ -3,17 +3,20 @@ package freechips.rocketchip.subsystem import chisel3._ -import chisel3.dontTouch -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{TLDebugModule} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.prci._ -import freechips.rocketchip.util._ -import freechips.rocketchip.rocket.{TracedInstruction} + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.devices.debug.TLDebugModule +import freechips.rocketchip.diplomacy.{DisableMonitors, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing, FlipRendering} +import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink} +import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq} +import freechips.rocketchip.tilelink.TLWidthWidget +import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset} +import freechips.rocketchip.rocket.TracedInstruction +import freechips.rocketchip.util.TraceCoreInterface + import scala.collection.immutable.SortedMap /** Entry point for Config-uring the presence of Tiles */ diff --git a/src/main/scala/subsystem/HierarchicalElement.scala b/src/main/scala/subsystem/HierarchicalElement.scala index 18a7c189f3e..67d23ad451a 100644 --- a/src/main/scala/subsystem/HierarchicalElement.scala +++ b/src/main/scala/subsystem/HierarchicalElement.scala @@ -3,16 +3,15 @@ package freechips.rocketchip.subsystem import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.prci._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.devices.debug.TLDebugModule +import freechips.rocketchip.diplomacy.{BufferParams, ClockCrossingType} +import freechips.rocketchip.interrupts.IntXbar +import freechips.rocketchip.prci.{ClockSinkParameters, ResetCrossingType} import freechips.rocketchip.tile.{LookupByHartIdImpl, TraceBundle} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ -import freechips.rocketchip.devices.debug.{TLDebugModule} -import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.tilelink.{TLNode, TLIdentityNode, TLXbar, TLBuffer, TLInwardNode, TLOutwardNode} trait HierarchicalElementParams { val baseName: String // duplicated instances shouuld share a base name diff --git a/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala b/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala index a76b7c43402..dd4cfb37a61 100644 --- a/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala +++ b/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala @@ -3,17 +3,21 @@ package freechips.rocketchip.subsystem import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.prci._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.devices.debug.TLDebugModule +import freechips.rocketchip.diplomacy.{ClockCrossingType, DisableMonitors, FlipRendering} +import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode} +import freechips.rocketchip.prci.{ResetCrossingType, ResetDomain, ClockSinkNode, ClockSinkParameters, ClockIdentityNode, FixedClockBroadcast, ClockDomain} import freechips.rocketchip.tile.{RocketTile, TraceBundle} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.devices.debug.{TLDebugModule} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.util.{TraceCoreInterface} +import freechips.rocketchip.tilelink.{TLInwardNode, TLOutwardNode} +import freechips.rocketchip.util.TraceCoreInterface +import freechips.rocketchip.tilelink.TLClockDomainCrossing +import freechips.rocketchip.tilelink.TLResetDomainCrossing +import freechips.rocketchip.interrupts.IntClockDomainCrossing +import freechips.rocketchip.interrupts.IntResetDomainCrossing /** A wrapper containing all logic within a managed reset domain for a element. * diff --git a/src/main/scala/subsystem/InterruptBus.scala b/src/main/scala/subsystem/InterruptBus.scala index 2815e3f0866..c911901aced 100644 --- a/src/main/scala/subsystem/InterruptBus.scala +++ b/src/main/scala/subsystem/InterruptBus.scala @@ -3,10 +3,15 @@ package freechips.rocketchip.subsystem import chisel3._ -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.prci.{ClockSinkDomain} + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{ClockCrossingType, AsynchronousCrossing, RationalCrossing, Device, DeviceInterrupts, Description, ResourceBindings} +import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode, IntXbar, IntNameNode, IntSourceNode, IntSourcePortSimple} +import freechips.rocketchip.prci.ClockSinkDomain + +import freechips.rocketchip.interrupts.IntClockDomainCrossing /** Collects interrupts from internal and external devices and feeds them into the PLIC */ class InterruptBusWrapper(implicit p: Parameters) extends ClockSinkDomain { diff --git a/src/main/scala/subsystem/MemoryBus.scala b/src/main/scala/subsystem/MemoryBus.scala index 03b8bb22d4b..b8b4e9919a4 100644 --- a/src/main/scala/subsystem/MemoryBus.scala +++ b/src/main/scala/subsystem/MemoryBus.scala @@ -3,10 +3,15 @@ package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.devices.tilelink.{BuiltInDevices, HasBuiltInDeviceParams, BuiltInErrorDeviceParams, BuiltInZeroDeviceParams} +import freechips.rocketchip.tilelink.{ + ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, + TLBusWrapperInstantiationLike, RegionReplicator, TLXbar, TLInwardNode, + TLOutwardNode, ProbePicker, TLEdge, TLFIFOFixer +} +import freechips.rocketchip.util.Location /** Parameterization of the memory-side bus created for each memory channel */ case class MemoryBusParams( diff --git a/src/main/scala/subsystem/PeripheryBus.scala b/src/main/scala/subsystem/PeripheryBus.scala index 830e4480925..6b0a66f9987 100644 --- a/src/main/scala/subsystem/PeripheryBus.scala +++ b/src/main/scala/subsystem/PeripheryBus.scala @@ -2,11 +2,17 @@ package freechips.rocketchip.subsystem -import org.chipsalliance.cde.config.{Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices} +import freechips.rocketchip.diplomacy.BufferParams +import freechips.rocketchip.tilelink.{ + RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, + TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode, + TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge +} +import freechips.rocketchip.util.Location case class BusAtomics( arithmetic: Boolean = true, diff --git a/src/main/scala/subsystem/Ports.scala b/src/main/scala/subsystem/Ports.scala index 634583bea61..5fed06a2e23 100644 --- a/src/main/scala/subsystem/Ports.scala +++ b/src/main/scala/subsystem/Ports.scala @@ -4,11 +4,28 @@ package freechips.rocketchip.subsystem import chisel3._ -import org.chipsalliance.cde.config.Field -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.util._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.amba.axi4.{ + AXI4SlaveNode, AXI4SlavePortParameters, AXI4SlaveParameters, AXI4UserYanker, AXI4Buffer, + AXI4Deinterleaver, AXI4IdIndexer, AXI4MasterNode, AXI4MasterPortParameters, AXI4ToTL, + AXI4Fragmenter, AXI4MasterParameters +} +import freechips.rocketchip.diplomacy.{ + MemoryDevice, AddressSet, RegionType, TransferSizes, SimpleBus, IdRange, BufferParams +} +import freechips.rocketchip.tilelink.{ + TLXbar, RegionReplicator, ReplicatedRegion, TLWidthWidget, TLFilter, TLToAXI4, TLBuffer, + TLFIFOFixer, TLSlavePortParameters, TLManagerNode, TLSlaveParameters, TLClientNode, + TLSourceShrinker, TLMasterParameters, TLMasterPortParameters +} +import freechips.rocketchip.util.StringToAugmentedString + +import freechips.rocketchip.tilelink.TLClockDomainCrossing +import freechips.rocketchip.tilelink.TLResetDomainCrossing /** Specifies the size and width of external memory ports */ case class MasterPortParams( diff --git a/src/main/scala/subsystem/RTC.scala b/src/main/scala/subsystem/RTC.scala index 2c67d453577..ec6470f6f3b 100644 --- a/src/main/scala/subsystem/RTC.scala +++ b/src/main/scala/subsystem/RTC.scala @@ -3,8 +3,11 @@ package freechips.rocketchip.subsystem import chisel3._ -import chisel3.util.Counter -import freechips.rocketchip.diplomacy.{LazyRawModuleImp, DTSTimebase} +import chisel3.util._ + +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.DTSTimebase import freechips.rocketchip.devices.tilelink.{CLINTAttachKey, CanHavePeripheryCLINT} trait HasRTCModuleImp extends LazyRawModuleImp { diff --git a/src/main/scala/subsystem/RocketSubsystem.scala b/src/main/scala/subsystem/RocketSubsystem.scala index df9987e0530..1fb0e73fade 100644 --- a/src/main/scala/subsystem/RocketSubsystem.scala +++ b/src/main/scala/subsystem/RocketSubsystem.scala @@ -2,13 +2,14 @@ package freechips.rocketchip.subsystem -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing} -import freechips.rocketchip.tile._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug} -import freechips.rocketchip.util.{HasCoreMonitorBundles} +import org.chipsalliance.cde.config._ + +import freechips.rocketchip.devices.debug.HasPeripheryDebug import freechips.rocketchip.devices.tilelink.{CanHavePeripheryCLINT, CanHavePeripheryPLIC} +import freechips.rocketchip.diplomacy.{SynchronousCrossing, ClockCrossingType} +import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing} +import freechips.rocketchip.tile.{RocketTile, RocketTileParams} +import freechips.rocketchip.util.HasCoreMonitorBundles case class RocketCrossingParams( crossingType: ClockCrossingType = SynchronousCrossing(), diff --git a/src/main/scala/subsystem/SystemBus.scala b/src/main/scala/subsystem/SystemBus.scala index 3d8f98203fb..c80bb793b92 100644 --- a/src/main/scala/subsystem/SystemBus.scala +++ b/src/main/scala/subsystem/SystemBus.scala @@ -2,11 +2,18 @@ package freechips.rocketchip.subsystem -import org.chipsalliance.cde.config.{Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.devices.tilelink.{ + BuiltInDevices, BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams +} +import freechips.rocketchip.tilelink.{ + TLArbiter, RegionReplicator, ReplicatedRegion, HasTLBusParams, TLBusWrapper, + TLBusWrapperInstantiationLike, TLXbar, TLEdge, TLInwardNode, TLOutwardNode, + TLFIFOFixer, TLTempNode +} +import freechips.rocketchip.util.Location case class SystemBusParams( beatBytes: Int, diff --git a/src/main/scala/system/SimAXIMem.scala b/src/main/scala/system/SimAXIMem.scala index a0238522641..f0a08e6d5b8 100644 --- a/src/main/scala/system/SimAXIMem.scala +++ b/src/main/scala/system/SimAXIMem.scala @@ -3,10 +3,13 @@ package freechips.rocketchip.system // TODO this should really be in a testharness package import chisel3._ -import freechips.rocketchip.amba._ -import freechips.rocketchip.amba.axi4._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.amba.AMBACorrupt +import freechips.rocketchip.amba.axi4.{AXI4RAM, AXI4MasterNode, AXI4EdgeParameters, AXI4Xbar, AXI4Buffer, AXI4Fragmenter} +import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MMIOPort, CanHaveMasterAXI4MemPort, ExtBus, ExtMem} /** Memory with AXI port for use in elaboratable test harnesses. diff --git a/src/main/scala/system/TestHarness.scala b/src/main/scala/system/TestHarness.scala index 788716258f1..80c711880aa 100644 --- a/src/main/scala/system/TestHarness.scala +++ b/src/main/scala/system/TestHarness.scala @@ -3,9 +3,11 @@ package freechips.rocketchip.system import chisel3._ -import org.chipsalliance.cde.config.Parameters + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.devices.debug.Debug -import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.util.AsyncResetReg class TestHarness()(implicit p: Parameters) extends Module { diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 76c8f7b1137..114c4fdcb40 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -4,15 +4,27 @@ package freechips.rocketchip.tile import chisel3._ import chisel3.util.{log2Ceil, log2Up} + import org.chipsalliance.cde.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.diplomacy._ - -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ -import freechips.rocketchip.prci.{ClockSinkParameters} +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.bundlebridge._ + + +import freechips.rocketchip.diplomacy.{ClockCrossingType, PropertyMap, PropertyOption, ResourceReference, DTSTimebase} +import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode} +import freechips.rocketchip.rocket.{ICacheParams, DCacheParams, BTBParams, PgLevels, ASIdBits, VMIdBits, TraceAux, BPWatch} +import freechips.rocketchip.subsystem.{ + HierarchicalElementParams, InstantiableHierarchicalElementParams, HierarchicalElementCrossingParamsLike, + CacheBlockBytes, SystemBusKey, BaseHierarchicalElement, InsertTimingClosureRegistersOnHartIds, BaseHierarchicalElementModuleImp +} +import freechips.rocketchip.tilelink.{TLEphemeralNode, TLOutwardNode, TLNode, TLFragmenter, EarlyAck, TLWidthWidget, TLManagerParameters, ManagerUnification} +import freechips.rocketchip.prci.ClockSinkParameters +import freechips.rocketchip.util.{TraceCoreParams, TraceCoreInterface} + +import freechips.rocketchip.diplomacy.BigIntToProperty +import freechips.rocketchip.diplomacy.IntToProperty +import freechips.rocketchip.diplomacy.StringToProperty +import freechips.rocketchip.util.BooleanToAugmentedBoolean case object TileVisibilityNodeKey extends Field[TLEphemeralNode] case object TileKey extends Field[TileParams] diff --git a/src/main/scala/tile/BusErrorUnit.scala b/src/main/scala/tile/BusErrorUnit.scala index 65c91b38e21..33a0bc1538b 100644 --- a/src/main/scala/tile/BusErrorUnit.scala +++ b/src/main/scala/tile/BusErrorUnit.scala @@ -3,17 +3,16 @@ package freechips.rocketchip.tile import chisel3._ -import chisel3.util.log2Ceil -// TODO: remove this import -import chisel3.util.ImplicitConversions._ -import chisel3.util.Valid -import chisel3.DontCare +import chisel3.util._ + import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.rocket._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.regmapper._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.rocket.{DCacheErrors, ICacheErrors} +import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice} +import freechips.rocketchip.regmapper.{DescribedReg, RegField, RegFieldDesc, RegFieldGroup} +import freechips.rocketchip.tilelink.TLRegisterNode +import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.property trait BusErrors extends Bundle { @@ -95,17 +94,17 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit new_value := DontCare for ((((s, en), acc), i) <- (sources zip enable zip accrued).zipWithIndex; if s.nonEmpty) { when (s.get.valid) { - acc := true + acc := true.B when (en) { - cause_wen := true - new_cause := i + cause_wen := true.B + new_cause := i.asUInt new_value := s.get.bits } property.cover(en, s"BusErrorCause_$i", s"Core;;BusErrorCause $i covered") } } - when (cause === 0 && cause_wen) { + when (cause === 0.asUInt && cause_wen) { cause := new_cause value := new_value } @@ -129,10 +128,10 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit // hardwire mask bits for unsupported sources to 0 for ((s, i) <- sources.zipWithIndex; if s.isEmpty) { - enable(i) := false - global_interrupt(i) := false - accrued(i) := false - local_interrupt(i) := false + enable(i) := false.B + global_interrupt(i) := false.B + accrued(i) := false.B + local_interrupt(i) := false.B } } } diff --git a/src/main/scala/tile/Interrupts.scala b/src/main/scala/tile/Interrupts.scala index 1efdde5983c..f6e392c7384 100644 --- a/src/main/scala/tile/Interrupts.scala +++ b/src/main/scala/tile/Interrupts.scala @@ -3,11 +3,17 @@ package freechips.rocketchip.tile import chisel3._ -import chisel3.util.{RegEnable, log2Ceil} -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ +import chisel3.util._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ + +import freechips.rocketchip.diplomacy.{Device, DeviceSnippet, Description, ResourceBinding, ResourceInt} +import freechips.rocketchip.interrupts.{IntIdentityNode, IntSinkNode, IntSinkPortSimple, IntSourceNode, IntSourcePortSimple} +import freechips.rocketchip.util.CanHaveErrors + +import freechips.rocketchip.diplomacy.IntToProperty +import freechips.rocketchip.diplomacy.StringToProperty +import freechips.rocketchip.util.BooleanToAugmentedBoolean class NMI(val w: Int) extends Bundle { val rnmi = Bool() diff --git a/src/main/scala/tile/LazyRoCC.scala b/src/main/scala/tile/LazyRoCC.scala index eb2ea1a92d9..d218d44bb85 100644 --- a/src/main/scala/tile/LazyRoCC.scala +++ b/src/main/scala/tile/LazyRoCC.scala @@ -5,12 +5,18 @@ package freechips.rocketchip.tile import chisel3._ import chisel3.util._ -import chisel3.util.HasBlackBoxResource import chisel3.experimental.IntParam + import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tilelink._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.rocket.{ + MStatus, HellaCacheIO, TLBPTWIO, CanHavePTW, CanHavePTWModule, + SimpleHellaCacheIF, M_XRD, PTE, PRV, M_SZ +} +import freechips.rocketchip.tilelink.{ + TLNode, TLIdentityNode, TLClientNode, TLMasterParameters, TLMasterPortParameters +} import freechips.rocketchip.util.InOrderArbiter case object BuildRoCC extends Field[Seq[Parameters => LazyRoCC]](Nil) diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 9d4c460d68a..ceee449f5e1 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -4,15 +4,27 @@ package freechips.rocketchip.tile import chisel3._ + import org.chipsalliance.cde.config._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.rocket._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.devices.tilelink.{BasicBusBlockerParams, BasicBusBlocker} +import freechips.rocketchip.diplomacy.{ + AddressSet, ClockCrossingType, DisableMonitors, SimpleDevice, Description, + ResourceAnchors, ResourceBindings, ResourceBinding, Resource, ResourceAddress, + RationalCrossing, BufferParams +} +import freechips.rocketchip.interrupts.IntIdentityNode +import freechips.rocketchip.tilelink.{TLIdentityNode, TLBuffer} +import freechips.rocketchip.rocket.{ + RocketCoreParams, ICacheParams, DCacheParams, BTBParams, HasHellaCache, + HasICacheFrontend, ScratchpadSlavePort, HasICacheFrontendModule, Rocket +} import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike -import freechips.rocketchip.util._ -import freechips.rocketchip.prci.{ClockSinkParameters} +import freechips.rocketchip.prci.ClockSinkParameters +import freechips.rocketchip.util.Annotated + +import freechips.rocketchip.util.BooleanToAugmentedBoolean case class RocketTileBoundaryBufferParams(force: Boolean = false) diff --git a/src/main/scala/tile/TilePRCIDomain.scala b/src/main/scala/tile/TilePRCIDomain.scala index d4066a63473..80c31f5a4d7 100644 --- a/src/main/scala/tile/TilePRCIDomain.scala +++ b/src/main/scala/tile/TilePRCIDomain.scala @@ -2,15 +2,14 @@ package freechips.rocketchip.tile -import chisel3.Vec -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.prci._ -import freechips.rocketchip.rocket.{TracedInstruction} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util.{TraceCoreInterface} +import chisel3._ + +import org.chipsalliance.cde.config._ + +import freechips.rocketchip.prci.ClockSinkParameters +import freechips.rocketchip.rocket.TracedInstruction +import freechips.rocketchip.subsystem.{HierarchicalElementCrossingParamsLike, HierarchicalElementPRCIDomain} +import freechips.rocketchip.util.TraceCoreInterface /** A wrapper containing all logic necessary to safely place a tile diff --git a/src/main/scala/tilelink/AddressAdjuster.scala b/src/main/scala/tilelink/AddressAdjuster.scala index d4a1fc7bbf1..c9de5710ed2 100644 --- a/src/main/scala/tilelink/AddressAdjuster.scala +++ b/src/main/scala/tilelink/AddressAdjuster.scala @@ -4,8 +4,12 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ + import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.AddressSet class AddressAdjuster( val params: ReplicatedRegion, // only devices in this region get adjusted diff --git a/src/main/scala/tilelink/AsyncCrossing.scala b/src/main/scala/tilelink/AsyncCrossing.scala index f974cf3e270..cadca7c34f5 100644 --- a/src/main/scala/tilelink/AsyncCrossing.scala +++ b/src/main/scala/tilelink/AsyncCrossing.scala @@ -3,11 +3,13 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, AsynchronousCrossing, NodeHandle} import freechips.rocketchip.subsystem.CrossingWrapper -import freechips.rocketchip.util._ -import freechips.rocketchip.util.property +import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/tilelink/AtomicAutomata.scala b/src/main/scala/tilelink/AtomicAutomata.scala index 37211ba8f99..ad573b718e5 100644 --- a/src/main/scala/tilelink/AtomicAutomata.scala +++ b/src/main/scala/tilelink/AtomicAutomata.scala @@ -3,11 +3,15 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} +import freechips.rocketchip.util.leftOR + import scala.math.{min,max} -import chisel3.util.{PriorityMux, Cat, FillInterleaved, Mux1H, MuxLookup, log2Up} // Ensures that all downstream RW managers support Atomic operations. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. diff --git a/src/main/scala/tilelink/BankBinder.scala b/src/main/scala/tilelink/BankBinder.scala index 8859123754d..21b32729a3d 100644 --- a/src/main/scala/tilelink/BankBinder.scala +++ b/src/main/scala/tilelink/BankBinder.scala @@ -2,8 +2,11 @@ package freechips.rocketchip.tilelink -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} case class BankBinderNode(mask: BigInt)(implicit valName: ValName) extends TLCustomNode { diff --git a/src/main/scala/tilelink/BlockDuringReset.scala b/src/main/scala/tilelink/BlockDuringReset.scala index ec676b6fff4..4dc6b2c29ce 100644 --- a/src/main/scala/tilelink/BlockDuringReset.scala +++ b/src/main/scala/tilelink/BlockDuringReset.scala @@ -3,8 +3,10 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.util.BlockDuringReset /** BlockDuringReset ensures that no channel admits to be ready or valid while reset is raised. */ diff --git a/src/main/scala/tilelink/Broadcast.scala b/src/main/scala/tilelink/Broadcast.scala index 0e69bd5d60f..8bfeba5c1c0 100644 --- a/src/main/scala/tilelink/Broadcast.scala +++ b/src/main/scala/tilelink/Broadcast.scala @@ -4,12 +4,18 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.regmapper._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.amba.AMBAProt +import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, IdRange, RegionType, SimpleDevice, TransferSizes} +import freechips.rocketchip.regmapper.RegField +import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple} +import freechips.rocketchip.util.leftOR + +import freechips.rocketchip.util.DataToAugmentedData + import scala.math.{min,max} case class TLBroadcastControlParams( diff --git a/src/main/scala/tilelink/Buffer.scala b/src/main/scala/tilelink/Buffer.scala index 8f43017028c..4bcf2ef50b3 100644 --- a/src/main/scala/tilelink/Buffer.scala +++ b/src/main/scala/tilelink/Buffer.scala @@ -3,8 +3,12 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, diff --git a/src/main/scala/tilelink/BusWrapper.scala b/src/main/scala/tilelink/BusWrapper.scala index b07844cef6a..c5793feea57 100644 --- a/src/main/scala/tilelink/BusWrapper.scala +++ b/src/main/scala/tilelink/BusWrapper.scala @@ -4,15 +4,28 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.{AddressSet, ClockCrossingType, NoCrossing, NoHandle, NodeHandle, NodeBinding} // TODO This class should be moved to package subsystem to resolve // the dependency awkwardness of the following imports -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.prci._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.util._ +import freechips.rocketchip.devices.tilelink.{BuiltInDevices, CanHaveBuiltInDevices} +import freechips.rocketchip.prci.{ + ClockParameters, ClockDomain, ClockGroup, ClockGroupAggregator, ClockSinkNode, + FixedClockBroadcast, ClockGroupEdgeParameters, ClockSinkParameters, ClockSinkDomain, + ClockGroupEphemeralNode, asyncMux +} +import freechips.rocketchip.subsystem.{ + HasTileLinkLocations, CanConnectWithinContextThatHasTileLinkLocations, + CanInstantiateWithinContextThatHasTileLinkLocations +} +import freechips.rocketchip.util.Location /** Specifies widths of various attachement points in the SoC */ trait HasTLBusParams { diff --git a/src/main/scala/tilelink/CacheCork.scala b/src/main/scala/tilelink/CacheCork.scala index 8ba1e4b9d7f..a8518d97dee 100644 --- a/src/main/scala/tilelink/CacheCork.scala +++ b/src/main/scala/tilelink/CacheCork.scala @@ -4,10 +4,18 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ -import TLMessages._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{IdRange, RegionType, TransferSizes} +import freechips.rocketchip.tilelink.TLMessages.{ + AcquireBlock, AcquirePerm, Get, PutFullData, PutPartialData, Release, + ReleaseData, Grant, GrantData, AccessAck, AccessAckData, ReleaseAck +} +import freechips.rocketchip.util.IDPool + +import freechips.rocketchip.util.DataToAugmentedData case class TLCacheCorkParams( unsafe: Boolean = false, diff --git a/src/main/scala/tilelink/Credited.scala b/src/main/scala/tilelink/Credited.scala index 30c73486012..f88586a04bf 100644 --- a/src/main/scala/tilelink/Credited.scala +++ b/src/main/scala/tilelink/Credited.scala @@ -3,11 +3,14 @@ package freechips.rocketchip.tilelink import chisel3._ -import chisel3.util.Decoupled -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, CreditedCrossing} import freechips.rocketchip.subsystem.CrossingWrapper -import freechips.rocketchip.util._ +import freechips.rocketchip.util.{CreditedDelay, CreditedIO} class TLCreditedBuffer(delay: TLCreditedDelay)(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/tilelink/CrossingHelper.scala b/src/main/scala/tilelink/CrossingHelper.scala index 52d96d6f432..e2f2059c7de 100644 --- a/src/main/scala/tilelink/CrossingHelper.scala +++ b/src/main/scala/tilelink/CrossingHelper.scala @@ -2,9 +2,14 @@ package freechips.rocketchip.tilelink -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.prci._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{ + AsynchronousCrossing, CrossingType, ClockCrossingType, NoCrossing, + RationalCrossing, CreditedCrossing, SynchronousCrossing +} +import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing} trait TLOutwardCrossingHelper { type HelperCrossingType <: CrossingType diff --git a/src/main/scala/tilelink/Delayer.scala b/src/main/scala/tilelink/Delayer.scala index 58d08e4bc48..bb984787938 100644 --- a/src/main/scala/tilelink/Delayer.scala +++ b/src/main/scala/tilelink/Delayer.scala @@ -4,8 +4,9 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ // q is the probability to delay a request class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule diff --git a/src/main/scala/tilelink/ErrorEvaluator.scala b/src/main/scala/tilelink/ErrorEvaluator.scala index 533cae0475f..e8931e9c650 100644 --- a/src/main/scala/tilelink/ErrorEvaluator.scala +++ b/src/main/scala/tilelink/ErrorEvaluator.scala @@ -3,9 +3,14 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.AddressSet +import freechips.rocketchip.util.UIntToOH1 + +import freechips.rocketchip.util.DataToAugmentedData // Check if a request satisfies some interesting property class RequestPattern(test: TLBundleA => Bool) diff --git a/src/main/scala/tilelink/FIFOFixer.scala b/src/main/scala/tilelink/FIFOFixer.scala index 6085f3cc242..efa0e966b46 100644 --- a/src/main/scala/tilelink/FIFOFixer.scala +++ b/src/main/scala/tilelink/FIFOFixer.scala @@ -4,8 +4,12 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ + import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.util.property class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule diff --git a/src/main/scala/tilelink/Filter.scala b/src/main/scala/tilelink/Filter.scala index fcc59dc5eb5..cd6ab212d2a 100644 --- a/src/main/scala/tilelink/Filter.scala +++ b/src/main/scala/tilelink/Filter.scala @@ -3,8 +3,11 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes} class TLFilter( mfilter: TLFilter.ManagerFilter = TLFilter.mIdentity, diff --git a/src/main/scala/tilelink/Fragmenter.scala b/src/main/scala/tilelink/Fragmenter.scala index e82a24e743e..a9f77c15ec0 100644 --- a/src/main/scala/tilelink/Fragmenter.scala +++ b/src/main/scala/tilelink/Fragmenter.scala @@ -4,11 +4,18 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} +import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} + import scala.math.min +import freechips.rocketchip.util.DataToAugmentedData + object EarlyAck { sealed trait T case object AllPuts extends T diff --git a/src/main/scala/tilelink/Fuzzer.scala b/src/main/scala/tilelink/Fuzzer.scala index 878b4ae744d..0dbf21fc831 100644 --- a/src/main/scala/tilelink/Fuzzer.scala +++ b/src/main/scala/tilelink/Fuzzer.scala @@ -4,9 +4,14 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, IdRange} +import freechips.rocketchip.util.{leftOR, UIntToOH1} + +import freechips.rocketchip.util.DataToAugmentedData class IDMapGenerator(numIds: Int) extends Module { require (numIds > 0) diff --git a/src/main/scala/tilelink/HintHandler.scala b/src/main/scala/tilelink/HintHandler.scala index 3b581a84621..982a1461d81 100644 --- a/src/main/scala/tilelink/HintHandler.scala +++ b/src/main/scala/tilelink/HintHandler.scala @@ -3,9 +3,12 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, RegionType, IdRange, TransferSizes} +import freechips.rocketchip.util.Repeater import freechips.rocketchip.devices.tilelink.TLROM // Acks Hints for managers that don't support them or Acks all Hints if !passthrough diff --git a/src/main/scala/tilelink/Isolation.scala b/src/main/scala/tilelink/Isolation.scala index 44154313c4c..90ebe4dd07a 100644 --- a/src/main/scala/tilelink/Isolation.scala +++ b/src/main/scala/tilelink/Isolation.scala @@ -3,8 +3,10 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.util.AsyncBundle // READ the comments in the TLIsolation object before you instantiate this module diff --git a/src/main/scala/tilelink/Jbar.scala b/src/main/scala/tilelink/Jbar.scala index c4ce2396fdc..084af313489 100644 --- a/src/main/scala/tilelink/Jbar.scala +++ b/src/main/scala/tilelink/Jbar.scala @@ -3,8 +3,11 @@ package freechips.rocketchip.tilelink import chisel3._ + import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.AddressSet class TLJbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/tilelink/Map.scala b/src/main/scala/tilelink/Map.scala index a37bb04f5bc..b3578c05a0f 100644 --- a/src/main/scala/tilelink/Map.scala +++ b/src/main/scala/tilelink/Map.scala @@ -3,8 +3,11 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.AddressSet // Moves the AddressSets of slave devices around // Combine with TLFilter to remove slaves or reduce their size diff --git a/src/main/scala/tilelink/Monitor.scala b/src/main/scala/tilelink/Monitor.scala index 013912a562d..e076656c3f5 100644 --- a/src/main/scala/tilelink/Monitor.scala +++ b/src/main/scala/tilelink/Monitor.scala @@ -5,10 +5,13 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ + +import freechips.rocketchip.diplomacy.EnableMonitors +import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg -import freechips.rocketchip.formal._ case class TLMonitorArgs(edge: TLEdge) diff --git a/src/main/scala/tilelink/Nodes.scala b/src/main/scala/tilelink/Nodes.scala index ddf4cfb0440..6b193f8ec0b 100644 --- a/src/main/scala/tilelink/Nodes.scala +++ b/src/main/scala/tilelink/Nodes.scala @@ -4,8 +4,11 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.nodes._ + import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) diff --git a/src/main/scala/tilelink/Parameters.scala b/src/main/scala/tilelink/Parameters.scala index f4dbc185d8c..b3cedc679e1 100644 --- a/src/main/scala/tilelink/Parameters.scala +++ b/src/main/scala/tilelink/Parameters.scala @@ -5,9 +5,19 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.{ + AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, + IdRange, RegionType, Resource, ResourceAddress, ResourcePermissions, TransferSizes +} +import freechips.rocketchip.util.{ + AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, + CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct +} + import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel diff --git a/src/main/scala/tilelink/PatternPusher.scala b/src/main/scala/tilelink/PatternPusher.scala index 7276d6ea48b..08e9eaba740 100644 --- a/src/main/scala/tilelink/PatternPusher.scala +++ b/src/main/scala/tilelink/PatternPusher.scala @@ -4,9 +4,11 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.util.DataToAugmentedData trait Pattern { def address: BigInt @@ -73,7 +75,7 @@ class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameter } val (plegal, pbits) = pattern.map(_.bits(edgeOut)).unzip - assert (end || VecInit(plegal)(step), s"Pattern pusher ${name} tried to push an illegal request") + assert (end || VecInit(plegal)(step), s"Pattern pusher ${this.name} tried to push an illegal request") a.valid := io.run && ready && !end && !flight a.bits := VecInit(pbits)(step) diff --git a/src/main/scala/tilelink/ProbePicker.scala b/src/main/scala/tilelink/ProbePicker.scala index 7b902b771c2..abb4e70f583 100644 --- a/src/main/scala/tilelink/ProbePicker.scala +++ b/src/main/scala/tilelink/ProbePicker.scala @@ -4,8 +4,11 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, IdRange} /* A ProbePicker is used to unify multiple cache banks into one logical cache */ class ProbePicker(implicit p: Parameters) extends LazyModule diff --git a/src/main/scala/tilelink/RAMModel.scala b/src/main/scala/tilelink/RAMModel.scala index 46c02cdd804..4a785242906 100644 --- a/src/main/scala/tilelink/RAMModel.scala +++ b/src/main/scala/tilelink/RAMModel.scala @@ -4,9 +4,13 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.util.{CRC, UIntToOH1} + +import freechips.rocketchip.util.DataToAugmentedData // We detect concurrent puts that put memory into an undefined state. // put0, put0Ack, put1, put1Ack => ok: defined diff --git a/src/main/scala/tilelink/RationalCrossing.scala b/src/main/scala/tilelink/RationalCrossing.scala index e39860e3797..3dd7ad289b9 100644 --- a/src/main/scala/tilelink/RationalCrossing.scala +++ b/src/main/scala/tilelink/RationalCrossing.scala @@ -10,9 +10,15 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} +import freechips.rocketchip.util.{ + FromRational, ToRational, RationalDirection, Symmetric, FastToSlow, SlowToFast, Pow2ClockDivider, ClockDivider3 +} + class TLRationalCrossingSource(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/tilelink/RegionReplication.scala b/src/main/scala/tilelink/RegionReplication.scala index 567b120ae71..396f5052562 100644 --- a/src/main/scala/tilelink/RegionReplication.scala +++ b/src/main/scala/tilelink/RegionReplication.scala @@ -3,8 +3,12 @@ package freechips.rocketchip.tilelink import chisel3._ + import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.AddressSet /* Address inside the 'local' space are replicated to fill the 'remote' space. */ diff --git a/src/main/scala/tilelink/RegisterRouter.scala b/src/main/scala/tilelink/RegisterRouter.scala index d76dbe3d63d..1f761782aae 100644 --- a/src/main/scala/tilelink/RegisterRouter.scala +++ b/src/main/scala/tilelink/RegisterRouter.scala @@ -4,11 +4,14 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import chisel3.RawModule -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.regmapper._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.{AddressSet, Device, TransferSizes, Resource, NoCrossing, ResourceBindings} +import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} +import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min diff --git a/src/main/scala/tilelink/RegisterRouterTest.scala b/src/main/scala/tilelink/RegisterRouterTest.scala index 238c8d7a730..d3a64055f69 100644 --- a/src/main/scala/tilelink/RegisterRouterTest.scala +++ b/src/main/scala/tilelink/RegisterRouterTest.scala @@ -3,10 +3,12 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + import freechips.rocketchip.regmapper.{RRTest0, RRTest1} -import freechips.rocketchip.unittest._ +import freechips.rocketchip.unittest.{UnitTest, UnitTestModule} class TLRRTest0(address: BigInt)(implicit p: Parameters) extends RRTest0(address) diff --git a/src/main/scala/tilelink/SRAM.scala b/src/main/scala/tilelink/SRAM.scala index f92e142ccaf..550bfc0ea70 100644 --- a/src/main/scala/tilelink/SRAM.scala +++ b/src/main/scala/tilelink/SRAM.scala @@ -4,10 +4,16 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ -import freechips.rocketchip.util.property + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.bundlebridge._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, Device, DeviceRegName, DiplomaticSRAM, RegionType, TransferSizes, HasJustOneSeqMem} +import freechips.rocketchip.util.{CanHaveErrors, ECCParams, property, SECDEDCode} + +import freechips.rocketchip.util.DataToAugmentedData +import freechips.rocketchip.util.BooleanToAugmentedBoolean class TLRAMErrors(val params: ECCParams, val addrBits: Int) extends Bundle with CanHaveErrors { val correctable = (params.code.canCorrect && params.notifyErrors).option(Valid(UInt(addrBits.W))) diff --git a/src/main/scala/tilelink/SourceShrinker.scala b/src/main/scala/tilelink/SourceShrinker.scala index 16fac848d60..c72d42f3e85 100644 --- a/src/main/scala/tilelink/SourceShrinker.scala +++ b/src/main/scala/tilelink/SourceShrinker.scala @@ -4,9 +4,14 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.IdRange +import freechips.rocketchip.util.leftOR + +import freechips.rocketchip.util.DataToAugmentedData class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/tilelink/ToAHB.scala b/src/main/scala/tilelink/ToAHB.scala index 5f960aa944c..a5267704295 100644 --- a/src/main/scala/tilelink/ToAHB.scala +++ b/src/main/scala/tilelink/ToAHB.scala @@ -4,13 +4,17 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import freechips.rocketchip.amba._ -import freechips.rocketchip.amba.ahb._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ -import AHBParameters._ -import chisel3.util.{RegEnable, Queue, Cat, log2Ceil} + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} +import freechips.rocketchip.amba.ahb.{AHBImpMaster, AHBParameters, AHBMasterParameters, AHBMasterPortParameters} +import freechips.rocketchip.amba.ahb.AHBParameters.{BURST_INCR, BURST_SINGLE, TRANS_NONSEQ, TRANS_SEQ, TRANS_IDLE, TRANS_BUSY, PROT_DEFAULT} +import freechips.rocketchip.diplomacy.TransferSizes +import freechips.rocketchip.util.{BundleMap, UIntToOH1} case class TLToAHBNode(supportHints: Boolean)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AHBImpMaster)( dFn = { cp => diff --git a/src/main/scala/tilelink/ToAPB.scala b/src/main/scala/tilelink/ToAPB.scala index 91c172d658a..8b045144fd3 100644 --- a/src/main/scala/tilelink/ToAPB.scala +++ b/src/main/scala/tilelink/ToAPB.scala @@ -3,13 +3,18 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.amba.apb._ -import freechips.rocketchip.amba._ -import APBParameters._ import chisel3.util._ +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.TransferSizes +import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} +import freechips.rocketchip.amba.apb.{APBImp, APBMasterParameters, APBMasterPortParameters} +import freechips.rocketchip.amba.apb.APBParameters.PROT_DEFAULT + case class TLToAPBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, APBImp)( dFn = { cp => APBMasterPortParameters( diff --git a/src/main/scala/tilelink/ToAXI4.scala b/src/main/scala/tilelink/ToAXI4.scala index 5aa6426f84a..a01ad75cf7a 100644 --- a/src/main/scala/tilelink/ToAXI4.scala +++ b/src/main/scala/tilelink/ToAXI4.scala @@ -3,12 +3,19 @@ package freechips.rocketchip.tilelink import chisel3._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ -import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.amba._ -import chisel3.util.{log2Ceil, UIntToOH, Queue, Decoupled, Cat} +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField} +import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp} +import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange} +import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1} + +import freechips.rocketchip.util.DataToAugmentedData class AXI4TLStateBundle(val sourceBits: Int) extends Bundle { val size = UInt(4.W) diff --git a/src/main/scala/tilelink/WidthWidget.scala b/src/main/scala/tilelink/WidthWidget.scala index 514f0c5a9ef..022a386c0b6 100644 --- a/src/main/scala/tilelink/WidthWidget.scala +++ b/src/main/scala/tilelink/WidthWidget.scala @@ -3,10 +3,13 @@ package freechips.rocketchip.tilelink import chisel3._ -import chisel3.util.{DecoupledIO, log2Ceil, Cat, RegEnable} -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.AddressSet +import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule diff --git a/src/main/scala/tilelink/Xbar.scala b/src/main/scala/tilelink/Xbar.scala index 1d6a82bbdc6..13f51f1cd7e 100644 --- a/src/main/scala/tilelink/Xbar.scala +++ b/src/main/scala/tilelink/Xbar.scala @@ -4,9 +4,12 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.{Field, Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} +import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout diff --git a/src/main/scala/tilelink/package.scala b/src/main/scala/tilelink/package.scala index 6afc522d813..c93afea09c4 100644 --- a/src/main/scala/tilelink/package.scala +++ b/src/main/scala/tilelink/package.scala @@ -2,8 +2,11 @@ package freechips.rocketchip -import freechips.rocketchip.diplomacy.{HasClockDomainCrossing, _} -import freechips.rocketchip.prci.{HasResetDomainCrossing} +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.nodes._ + +import freechips.rocketchip.diplomacy.HasClockDomainCrossing +import freechips.rocketchip.prci.HasResetDomainCrossing package object tilelink { diff --git a/src/main/scala/unittest/TestGenerator.scala b/src/main/scala/unittest/TestGenerator.scala index 9440ebad0d6..d38fe9fc30c 100644 --- a/src/main/scala/unittest/TestGenerator.scala +++ b/src/main/scala/unittest/TestGenerator.scala @@ -3,8 +3,9 @@ package freechips.rocketchip.unittest import chisel3._ + import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ abstract class LazyUnitTest(implicit p: Parameters) extends LazyModule { self => diff --git a/src/main/scala/util/Annotations.scala b/src/main/scala/util/Annotations.scala index 6cb8a4be85d..9039ccd4116 100644 --- a/src/main/scala/util/Annotations.scala +++ b/src/main/scala/util/Annotations.scala @@ -4,11 +4,13 @@ package freechips.rocketchip.util import chisel3._ import chisel3.experimental.{annotate, ChiselAnnotation} -import chisel3.RawModule + import firrtl.annotations._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.regmapper._ +import org.chipsalliance.diplomacy + +import freechips.rocketchip.diplomacy.{AddressRange, AddressSet, AddressMapEntry, ResourcePermissions} +import freechips.rocketchip.regmapper.{RegField, RegFieldDescSer, RegistersSer} import org.json4s.JsonDSL._ import org.json4s.jackson.JsonMethods.{pretty, render} diff --git a/src/main/scala/util/PSDTestMode.scala b/src/main/scala/util/PSDTestMode.scala index 1ca26d79596..30c97a9078c 100644 --- a/src/main/scala/util/PSDTestMode.scala +++ b/src/main/scala/util/PSDTestMode.scala @@ -3,8 +3,10 @@ package freechips.rocketchip.util import chisel3._ + import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy.{BundleBridgeEphemeralNode, ValName} +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.bundlebridge._ case object IncludePSDTest extends Field[Boolean](false) case object PSDTestModeBroadcastKey extends Field(