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How to check resultdata #57

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chenyuanyping opened this issue Dec 17, 2024 · 10 comments
Open

How to check resultdata #57

chenyuanyping opened this issue Dec 17, 2024 · 10 comments
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@chenyuanyping
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Case: out/v128x32machine/tests/stage1/vaadd_vv-0.S
It seems that the final results were not checked and compared.
vadd_vv

@ksco
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ksco commented Dec 17, 2024

The final assembly is in stage2, not stage1.

@chenyuanyping
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chenyuanyping commented Dec 17, 2024

Thanks for the answer. I also want to know the function of the .word command.
And When I generated stage2, the following error occurred
stage2

@ksco
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ksco commented Dec 18, 2024

Can you try XLEN=64 to see if it's working? Maybe something is wrong under XLEN=32?

@chenyuanyping
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I have tried and the error occurs as follows
RISCV_ERROR

@ksco
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ksco commented Dec 18, 2024

Maybe something is wrong with your setup, check how we did this in the CI, refer to https://github.com/chipsalliance/riscv-vector-tests/blob/main/.github/workflows/build-and-test.yml.

@chenyuanyping
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Thanks,I will try

@ksco
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ksco commented Dec 18, 2024

Oh, about the magic .word, check the "How it works" section in README. We modified spike to add a "magic" instruction which generates reference result checking code, and then merged back to the original assembly file.

@chenyuanyping
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thanks for modified. I tried VLEN=128,XLEN=64 and it passed, but when I tried VLEN=128,XLEN=32, it gave the error as below
image

@chenyuanyping
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I run
make generate-stage1 --environment-overrides VLEN=128 XLEN=32
make all -j128 --environment-overrides VLEN=128 XLEN=32

@ksco
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ksco commented Dec 18, 2024

It seems XLEN=32 was not well tested in some cases, I'll check later.

@ksco ksco self-assigned this Dec 18, 2024
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