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Fix RV32 support #75

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Fix RV32 support

Fix RV32 support #75

Run time

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Job Run time
generate-config
9s
build-spike / Build Spike
9s
generate-code (riscv_arithmetic_basic_test, uvm)
1m 23s
generate-code (riscv_rand_instr_test, uvm)
1m 21s
generate-code (riscv_jump_stress_test, uvm)
1m 24s
generate-code (riscv_loop_test, uvm)
1m 19s
generate-code (riscv_rand_jump_test, uvm)
1m 22s
generate-code (riscv_mmu_stress_test, uvm)
1m 25s
generate-code (riscv_no_fence_test, uvm)
1m 20s
generate-code (riscv_illegal_instr_test, uvm)
1m 23s
generate-code (riscv_ebreak_test, uvm)
1m 22s
generate-code (riscv_ebreak_debug_mode_test, uvm)
1m 27s
generate-code (riscv_full_interrupt_test, uvm)
1m 20s
generate-code (riscv_unaligned_load_store_test, uvm)
1m 42s
generate-code (riscv_non_compressed_instr_test, uvm)
1m 23s
generate-code (riscv_hint_instr_test, uvm)
1m 24s
generate-code (riscv_pmp_test, uvm)
1m 24s
generate-code (riscv_arithmetic_basic_test, pyflow)
1m 24s
run-tests (riscv_arithmetic_basic_test, uvm)
59s
run-tests (riscv_rand_instr_test, uvm)
1m 8s
run-tests (riscv_jump_stress_test, uvm)
51s
run-tests (riscv_loop_test, uvm)
1m 16s
run-tests (riscv_rand_jump_test, uvm)
1m 23s
run-tests (riscv_mmu_stress_test, uvm)
1m 12s
run-tests (riscv_no_fence_test, uvm)
58s
run-tests (riscv_illegal_instr_test, uvm)
1m 2s
run-tests (riscv_ebreak_test, uvm)
50s
run-tests (riscv_ebreak_debug_mode_test, uvm)
1m 8s
run-tests (riscv_full_interrupt_test, uvm)
59s
run-tests (riscv_unaligned_load_store_test, uvm)
1m 4s
run-tests (riscv_non_compressed_instr_test, uvm)
1m 7s
run-tests (riscv_hint_instr_test, uvm)
52s
run-tests (riscv_pmp_test, uvm)
1m 6s
run-tests (riscv_arithmetic_basic_test, pyflow)
1m 6s
39m 42s