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Merge pull request #956 from antmicro/ci-matrix #110

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Merge pull request #956 from antmicro/ci-matrix

Merge pull request #956 from antmicro/ci-matrix #110

Run time

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Job Run time
generate-config
6s
build-spike / Build Spike
8m 0s
generate-code (riscv_arithmetic_basic_test, uvm)
3m 15s
generate-code (riscv_rand_instr_test, uvm)
3m 8s
generate-code (riscv_jump_stress_test, uvm)
3m 11s
generate-code (riscv_loop_test, uvm)
3m 21s
generate-code (riscv_rand_jump_test, uvm)
3m 11s
generate-code (riscv_mmu_stress_test, uvm)
3m 9s
generate-code (riscv_no_fence_test, uvm)
3m 20s
generate-code (riscv_illegal_instr_test, uvm)
3m 13s
generate-code (riscv_ebreak_test, uvm)
3m 21s
generate-code (riscv_ebreak_debug_mode_test, uvm)
3m 9s
generate-code (riscv_full_interrupt_test, uvm)
3m 14s
generate-code (riscv_unaligned_load_store_test, uvm)
3m 11s
generate-code (riscv_non_compressed_instr_test, uvm)
3m 25s
generate-code (riscv_hint_instr_test, uvm)
3m 17s
generate-code (riscv_pmp_test, uvm)
6m 18s
generate-code (riscv_arithmetic_basic_test, pyflow)
3m 37s
run-tests (riscv_arithmetic_basic_test, uvm)
40s
run-tests (riscv_rand_instr_test, uvm)
41s
run-tests (riscv_jump_stress_test, uvm)
47s
run-tests (riscv_loop_test, uvm)
37s
run-tests (riscv_rand_jump_test, uvm)
38s
run-tests (riscv_mmu_stress_test, uvm)
42s
run-tests (riscv_no_fence_test, uvm)
49s
run-tests (riscv_illegal_instr_test, uvm)
45s
run-tests (riscv_ebreak_test, uvm)
58s
run-tests (riscv_ebreak_debug_mode_test, uvm)
38s
run-tests (riscv_full_interrupt_test, uvm)
41s
run-tests (riscv_unaligned_load_store_test, uvm)
38s
run-tests (riscv_non_compressed_instr_test, uvm)
48s
run-tests (riscv_hint_instr_test, uvm)
37s
run-tests (riscv_pmp_test, uvm)
46s
run-tests (riscv_arithmetic_basic_test, pyflow)
47s
1h 14m 58s