From 810204ed7d191bb58219a5662c410409dae172c9 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Wed, 29 May 2024 23:43:58 -0700 Subject: [PATCH 1/3] add test for FlatIO port ordering --- .../chiselTests/experimental/FlatIOSpec.scala | 53 +++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala index ae38e17bb36..631865679db 100644 --- a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala +++ b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala @@ -6,9 +6,12 @@ import chisel3._ import chisel3.util.Valid import circt.stage.ChiselStage.emitCHIRRTL import chisel3.experimental.Analog -import chiselTests.ChiselFlatSpec +import chiselTests.{ChiselFlatSpec, MatchesAndOmits} +import chisel3.reflect.DataMirror +import scala.collection.immutable.SeqMap +import circt.stage.ChiselStage -class FlatIOSpec extends ChiselFlatSpec { +class FlatIOSpec extends ChiselFlatSpec with MatchesAndOmits { behavior.of("FlatIO") it should "create ports without a prefix" in { @@ -36,7 +39,7 @@ class FlatIOSpec extends ChiselFlatSpec { chirrtl should include("connect out.valid, valid") } - it should "dynamically indexing Vecs inside of FlatIOs" in { + it should "support dynamically indexing Vecs inside of FlatIOs" in { class MyModule extends RawModule { val io = FlatIO(new Bundle { val addr = Input(UInt(2.W)) @@ -76,4 +79,48 @@ class FlatIOSpec extends ChiselFlatSpec { chirrtl should include("output a : UInt<1>") chirrtl should include("output b : UInt<2>[2]") } + + it should "maintain port order for Bundles" in { + class MyBundle extends Bundle { + val foo = Bool() + val bar = Bool() + } + class MyModule extends Module { + val io = IO(Input(new MyBundle)) + } + class MyFlatIOModule extends Module { + val io = FlatIO(Input(new MyBundle)) + } + + matchesAndOmits( + ChiselStage.emitSystemVerilog( + new MyModule + ) + )("io_foo,")("io_bar,") + + matchesAndOmits( + ChiselStage.emitSystemVerilog(new MyFlatIOModule) + )("foo,")("bar,") + } + + it should "maintain port order for Records" in { + class MyRecord extends Record { + val elements = SeqMap("foo" -> Bool(), "bar" -> Bool()) + } + class MyModule extends Module { + val io = IO(Input(new MyRecord)) + } + class MyFlatIOModule extends Module { + val io = FlatIO(Input(new MyRecord)) + } + matchesAndOmits( + ChiselStage.emitSystemVerilog( + new MyModule + ) + )("io_bar,")("io_foo,") + matchesAndOmits( + ChiselStage.emitSystemVerilog(new MyFlatIOModule) + )("bar,")("foo,") + } + } From 92ea454ae562a499fa1ea2637c63bc821afb41bf Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Wed, 29 May 2024 23:49:14 -0700 Subject: [PATCH 2/3] Update src/test/scala/chiselTests/experimental/FlatIOSpec.scala --- src/test/scala/chiselTests/experimental/FlatIOSpec.scala | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala index 631865679db..ebe5f00d6e5 100644 --- a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala +++ b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala @@ -93,9 +93,7 @@ class FlatIOSpec extends ChiselFlatSpec with MatchesAndOmits { } matchesAndOmits( - ChiselStage.emitSystemVerilog( - new MyModule - ) + ChiselStage.emitSystemVerilog(new MyModule) )("io_foo,")("io_bar,") matchesAndOmits( From 430bcc2d22403c7ef183e47c616872d40b0404a9 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Wed, 29 May 2024 23:49:49 -0700 Subject: [PATCH 3/3] Update src/test/scala/chiselTests/experimental/FlatIOSpec.scala --- src/test/scala/chiselTests/experimental/FlatIOSpec.scala | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala index ebe5f00d6e5..13e309e5a9b 100644 --- a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala +++ b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala @@ -112,9 +112,7 @@ class FlatIOSpec extends ChiselFlatSpec with MatchesAndOmits { val io = FlatIO(Input(new MyRecord)) } matchesAndOmits( - ChiselStage.emitSystemVerilog( - new MyModule - ) + ChiselStage.emitSystemVerilog(new MyModule) )("io_bar,")("io_foo,") matchesAndOmits( ChiselStage.emitSystemVerilog(new MyFlatIOModule)