From fddf41af5a96cf9e2ace67ce84d990df808f5872 Mon Sep 17 00:00:00 2001
From: Deborah Soung <debs@sifive.com>
Date: Wed, 9 Oct 2024 10:29:44 -0700
Subject: [PATCH] Support creation of `Path`s from `HasTarget`s (#4455)

---
 core/src/main/scala/chisel3/properties/Path.scala      | 10 ++++++++++
 .../scala/chiselTests/properties/PropertySpec.scala    | 10 +++++++---
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/core/src/main/scala/chisel3/properties/Path.scala b/core/src/main/scala/chisel3/properties/Path.scala
index abc05e4236..371e727de1 100644
--- a/core/src/main/scala/chisel3/properties/Path.scala
+++ b/core/src/main/scala/chisel3/properties/Path.scala
@@ -92,6 +92,16 @@ object Path {
     }
   }
 
+  /** Construct a Path that refers to a HasTarget
+    */
+  def apply(hasTarget: HasTarget): Path = {
+    new TargetPath {
+      private val scope = Module.currentModule
+      def toTarget():   IsMember = hasTarget.toRelativeTarget(scope)
+      def isMemberPath: Boolean = false
+    }
+  }
+
   /** Construct a Path from a target
     */
   def apply(target: IsMember): Path = apply(target, false)
diff --git a/src/test/scala/chiselTests/properties/PropertySpec.scala b/src/test/scala/chiselTests/properties/PropertySpec.scala
index a18d1601b4..cf4b3fcccc 100644
--- a/src/test/scala/chiselTests/properties/PropertySpec.scala
+++ b/src/test/scala/chiselTests/properties/PropertySpec.scala
@@ -164,17 +164,19 @@ class PropertySpec extends ChiselFlatSpec with MatchesAndOmits {
   }
 
   it should "support path as a Property literal" in {
-    val chirrtl = ChiselStage.emitCHIRRTL(new RawModule {
+    val chirrtl = ChiselStage.emitCHIRRTL(new Module {
       val propOutA = IO(Output(Property[Path]()))
       val propOutB = IO(Output(Property[Path]()))
       val propOutC = IO(Output(Property[Path]()))
       val propOutD = IO(Output(Property[Path]()))
       val propOutE = IO(Output(Property[Path]()))
+      val propOutF = IO(Output(Property[Path]()))
       override def desiredName = "Top"
-      val inst = Module(new RawModule {
+      val inst = Module(new Module {
         val localPropOut = IO(Output(Property[Path]()))
         val data = WireInit(false.B)
         val mem = SyncReadMem(1, Bool())
+        val sram = chisel3.util.SRAM(1, Bool(), 1, 1, 0)
         localPropOut := Property(Path(data))
         override def desiredName = "Foo"
       })
@@ -183,6 +185,7 @@ class PropertySpec extends ChiselFlatSpec with MatchesAndOmits {
       propOutC := Property(inst.mem)
       propOutD := Property(this)
       propOutE := inst.localPropOut
+      propOutF := Property(Path(inst.sram.underlying.get))
     })
     matchesAndOmits(chirrtl)(
       """propassign localPropOut, path("OMReferenceTarget:~Top|Foo>data")""",
@@ -190,7 +193,8 @@ class PropertySpec extends ChiselFlatSpec with MatchesAndOmits {
       """propassign propOutB, path("OMReferenceTarget:~Top|Top/inst:Foo>data")""",
       """propassign propOutC, path("OMReferenceTarget:~Top|Top/inst:Foo>mem")""",
       """propassign propOutD, path("OMInstanceTarget:~Top|Top")""",
-      """propassign propOutE, inst.localPropOut"""
+      """propassign propOutE, inst.localPropOut""",
+      """propassign propOutF, path("OMReferenceTarget:~Top|Top/inst:Foo>sram_sram")"""
     )()
   }