From 01b4f66c8ad5caefd608f988964ac6caffb73741 Mon Sep 17 00:00:00 2001
From: unlsycn <unlsycn@unlsycn.com>
Date: Mon, 2 Dec 2024 16:19:07 +0000
Subject: [PATCH] feat: add SRAMBlackBox

Signed-off-by: unlsycn <unlsycn@unlsycn.com>
---
 src/main/scala-2/chisel3/util/SRAM.scala | 115 +++++++++++++++++++++++
 1 file changed, 115 insertions(+)

diff --git a/src/main/scala-2/chisel3/util/SRAM.scala b/src/main/scala-2/chisel3/util/SRAM.scala
index b9e216c112..df414e65db 100644
--- a/src/main/scala-2/chisel3/util/SRAM.scala
+++ b/src/main/scala-2/chisel3/util/SRAM.scala
@@ -18,6 +18,7 @@ import chisel3.properties.Class.ClassDefinitionOps
 import chisel3.properties.{Class, ClassType, Path, Property}
 
 import scala.collection.immutable.{ListMap, VectorMap}
+import chisel3.util.experimental.{CIRCTSRAMInterface, CIRCTSRAMParameter}
 
 /** A bundle of signals representing a memory read port.
   *
@@ -200,6 +201,120 @@ case class BinaryMemoryFile(path: String) extends MemoryFile(MemoryLoadFileType.
   */
 case class HexMemoryFile(path: String) extends MemoryFile(MemoryLoadFileType.Hex)
 
+class SRAMBlackbox(parameter: CIRCTSRAMParameter)
+    extends FixedIOExtModule(new CIRCTSRAMInterface(parameter))
+    with HasExtModuleInline { self =>
+
+  private val verilogInterface: String =
+    (Seq.tabulate(parameter.write)(idx =>
+      Seq(
+        s"// Write Port $idx",
+        s"input [${log2Ceil(parameter.depth) - 1}:0] W${idx}_addr",
+        s"input W${idx}_en",
+        s"input W${idx}_clk",
+        s"input [${parameter.width - 1}:0] W${idx}_data"
+      ) ++
+        Option.when(parameter.masked)(s"input [${parameter.width / parameter.maskGranularity - 1}:0] W${idx}_mask")
+    ) ++
+      Seq.tabulate(parameter.read)(idx =>
+        Seq(
+          s"// Read Port $idx",
+          s"input [${log2Ceil(parameter.depth) - 1}:0] R${idx}_addr",
+          s"input R${idx}_en",
+          s"input R${idx}_clk",
+          s"output [${parameter.width - 1}:0] R${idx}_data"
+        )
+      ) ++
+      Seq.tabulate(parameter.readwrite)(idx =>
+        Seq(
+          s"// ReadWrite Port $idx",
+          s"input [${log2Ceil(parameter.depth) - 1}:0] RW${idx}_addr",
+          s"input RW${idx}_en",
+          s"input RW${idx}_clk",
+          s"input RW${idx}_wmode",
+          s"input [${parameter.width - 1}:0] RW${idx}_wdata",
+          s"output [${parameter.width - 1}:0] RW${idx}_rdata"
+        ) ++ Option
+          .when(parameter.masked)(
+            s"input [${parameter.width / parameter.maskGranularity - 1}:0] RW${idx}_wmask"
+          )
+      )).flatten.mkString(",\n")
+
+  private val rLogic = Seq
+    .tabulate(parameter.read) { idx =>
+      val prefix = s"R${idx}"
+      Seq(
+        s"reg _${prefix}_en;",
+        s"reg [${log2Ceil(parameter.depth) - 1}:0] _${prefix}_addr;"
+      ) ++
+        Seq(
+          s"always @(posedge ${prefix}_clk) begin // ${prefix}",
+          s"_${prefix}_en <= ${prefix}_en;",
+          s"_${prefix}_addr <= ${prefix}_addr;",
+          s"end // ${prefix}"
+        ) ++
+        Some(s"assign ${prefix}_data = _${prefix}_en ? Memory[_${prefix}_addr] : ${parameter.width}'bx;")
+    }
+    .flatten
+
+  private val wLogic = Seq
+    .tabulate(parameter.write) { idx =>
+      val prefix = s"W${idx}"
+      Seq(s"always @(posedge ${prefix}_clk) begin // ${prefix}") ++
+        (if (parameter.masked)
+           Seq.tabulate(parameter.width / parameter.maskGranularity)(i =>
+             s"if (${prefix}_en & ${prefix}_wmask[${i}]) Memory[${prefix}_addr][${i * parameter.maskGranularity} +: ${parameter.maskGranularity}] <= ${prefix}_wdata[${(i + 1) * parameter.maskGranularity - 1}:${i * parameter.maskGranularity}];"
+           )
+         else
+           Seq(s"if (${prefix}_en) Memory[${prefix}_addr] <= ${prefix}_data;")) ++
+        Seq(s"end // ${prefix}")
+    }
+    .flatten
+
+  private val rwLogic = Seq
+    .tabulate(parameter.readwrite) { idx =>
+      val prefix = s"RW${idx}"
+      Seq(
+        s"reg [${log2Ceil(parameter.depth) - 1}:0] _${prefix}_raddr;",
+        s"reg _${prefix}_ren;",
+        s"reg _${prefix}_rmode;"
+      ) ++
+        Seq(s"always @(posedge ${prefix}_clk) begin // ${prefix}") ++
+        Seq(
+          s"_${prefix}_raddr <= ${prefix}_addr;",
+          s"_${prefix}_ren <= ${prefix}_en;",
+          s"_${prefix}_rmode <= ${prefix}_wmode;"
+        ) ++
+        (if (parameter.masked)
+           Seq.tabulate(parameter.width / parameter.maskGranularity)(i =>
+             s"if(${prefix}_en & ${prefix}_wmask[${i}] & ${prefix}_wmode) Memory[${prefix}_addr][${i * parameter.maskGranularity} +: ${parameter.maskGranularity}] <= ${prefix}_wdata[${(i + 1) * parameter.maskGranularity - 1}:${i * parameter.maskGranularity}];"
+           )
+         else
+           Seq(s"if (${prefix}_en & ${prefix}_wmode) Memory[${prefix}_addr] <= ${prefix}_wdata;")) ++
+        Seq(s"end // ${prefix}") ++
+        Seq(
+          s"assign ${prefix}_rdata = _${prefix}_ren & ~_${prefix}_rmode ? Memory[_${prefix}_raddr] : ${parameter.width}'bx;"
+        )
+    }
+    .flatten
+
+  private val logic =
+    (Seq(s"reg [${parameter.width - 1}:0] Memory[0:${parameter.depth - 1}];") ++ wLogic ++ rLogic ++ rwLogic)
+      .mkString("\n")
+
+  override def desiredName = parameter.moduleName
+
+  setInline(
+    desiredName + ".sv",
+    s"""module ${parameter.moduleName}(
+       |${verilogInterface}
+       |);
+       |${logic}
+       |endmodule
+       |""".stripMargin
+  )
+}
+
 object SRAM {
 
   /** Generates a memory within the current module, connected to an explicit number