diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash index 5bfe0bb06..2cb812ff4 100644 --- a/.github/workflow_metadata/pr_hash +++ b/.github/workflow_metadata/pr_hash @@ -1 +1 @@ -cd58ccb29bee90c2bcddb5f0ff09f4fb9562ea9b6ed0300a3cc9b0503eb675e8b4040d5674510cdd4d9d68be275f5bbc \ No newline at end of file +4728a2efeb9500d84266322c96de495e0f68008b89cd1f904d80278204eb3c85f632cd345a024cd70b2374e236799542 \ No newline at end of file diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp index 6d63013bc..d28916aaf 100644 --- a/.github/workflow_metadata/pr_timestamp +++ b/.github/workflow_metadata/pr_timestamp @@ -1 +1 @@ -1731437165 \ No newline at end of file +1731535119 \ No newline at end of file diff --git a/src/integration/test_suites/includes/defines.h b/src/integration/test_suites/includes/defines.h index e41dfbe52..7cadffeae 100644 --- a/src/integration/test_suites/includes/defines.h +++ b/src/integration/test_suites/includes/defines.h @@ -16,175 +16,182 @@ //******************************************************************************** // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -// This is an automatically generated file by cwhitehead on Tue Nov 8 13:38:06 PST 2022 +// This is an automatically generated file by cwhitehead on Wed Nov 13 10:25:09 PST 2024 // -// cmd: veer -target=default_ahb --iccm_region=0x4 -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=128 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=iccm_enable=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_offset=0x0 -set=iccm_size=128 -set=iccm_num_banks=4 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -fpga_optimize=0 -snapshot=iccm_dccm_diff_region +// cmd: veer -target=default_ahb -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=128 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_enable=1 -set=iccm_num_banks=4 -set=iccm_region=0x4 -set=iccm_offset=0x0 -set=iccm_size=128 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -set=pmp_entries=64 -set=reset_vec=0x00000000 -fpga_optimize=0 -snapshot=20241113_cptra_dis_smepmp // -#ifndef RV_RESET_VEC -#define RV_RESET_VEC 0x00000000 +#ifndef RV_DEFINES +#define RV_DEFINES + +#define RV_BITMANIP_ZBA 1 +#define RV_BITMANIP_ZBB 1 +#define RV_BITMANIP_ZBC 1 +#define RV_BITMANIP_ZBE 0 +#define RV_BITMANIP_ZBF 0 +#define RV_BITMANIP_ZBP 0 +#define RV_BITMANIP_ZBR 0 +#define RV_BITMANIP_ZBS 1 +#define RV_DIV_BIT 4 +#define RV_DIV_NEW 1 +#define RV_DMA_BUF_DEPTH 5 +#define RV_FAST_INTERRUPT_REDIRECT 1 +#define RV_ICCM_ONLY 1 +#define RV_LSU2DMA 0 +#define RV_LSU_NUM_NBLOAD 4 +#define RV_LSU_NUM_NBLOAD_WIDTH 2 +#define RV_LSU_STBUF_DEPTH 4 +#define RV_TIMER_LEGAL_EN 1 +#define RV_DCCM_BANK_BITS 2 +#define RV_DCCM_BITS 17 +#define RV_DCCM_BYTE_WIDTH 4 +#define RV_DCCM_DATA_CELL ram_8192x39 +#define RV_DCCM_DATA_WIDTH 32 +#define RV_DCCM_EADR 0x5001ffff +#define RV_DCCM_ECC_WIDTH 7 +#define RV_DCCM_ENABLE 1 +#define RV_DCCM_FDATA_WIDTH 39 +#define RV_DCCM_INDEX_BITS 13 +#define RV_DCCM_NUM_BANKS 4 +#define RV_DCCM_NUM_BANKS_4 +#define RV_DCCM_OFFSET 0x00000 +#define RV_DCCM_REGION 0x5 +#define RV_DCCM_RESERVED 0x1400 +#define RV_DCCM_ROWS 8192 +#define RV_DCCM_SADR 0x50000000 +#define RV_DCCM_SIZE 128 +#define RV_DCCM_SIZE_128 +#define RV_DCCM_WIDTH_BITS 2 +#define RV_LSU_SB_BITS 17 +#define RV_ICCM_BANK_BITS 2 +#define RV_ICCM_BANK_HI 3 +#define RV_ICCM_BANK_INDEX_LO 4 +#define RV_ICCM_BITS 17 +#define RV_ICCM_DATA_CELL ram_8192x39 +#define RV_ICCM_EADR 0x4001ffff +#define RV_ICCM_ECC_WIDTH 7 +#define RV_ICCM_ENABLE 1 +#define RV_ICCM_INDEX_BITS 13 +#define RV_ICCM_NUM_BANKS 4 +#define RV_ICCM_NUM_BANKS_4 +#define RV_ICCM_OFFSET 0x0 +#define RV_ICCM_REGION 0x4 +#define RV_ICCM_RESERVED 0x1000 +#define RV_ICCM_ROWS 8192 +#define RV_ICCM_SADR 0x40000000 +#define RV_ICCM_SIZE 128 +#define RV_ICCM_SIZE_128 +#define RV_DEBUG_SB_MEM 0xc0580000 +#ifndef RV_EXTERNAL_DATA +#define RV_EXTERNAL_DATA 0xe0580000 #endif -#define RV_TARGET default_ahb -#define RV_INST_ACCESS_MASK4 0xffffffff -#define RV_DATA_ACCESS_MASK1 0xffffffff -#define RV_DATA_ACCESS_ENABLE5 0x0 -#define RV_INST_ACCESS_ADDR3 0x00000000 -#define RV_DATA_ACCESS_MASK4 0xffffffff -#define RV_INST_ACCESS_MASK1 0xffffffff -#define RV_INST_ACCESS_ENABLE5 0x0 +#define RV_EXTERNAL_DATA_1 0xd0000000 +#ifndef RV_SERIALIO +#define RV_SERIALIO 0xf0580000 +#endif +#define RV_UNUSED_REGION0 0xb0000000 +#define RV_UNUSED_REGION1 0xa0000000 +#define RV_UNUSED_REGION2 0x90000000 +#define RV_UNUSED_REGION3 0x80000000 +#define RV_UNUSED_REGION4 0x70000000 +#define RV_UNUSED_REGION5 0x30000000 +#define RV_UNUSED_REGION6 0x20000000 +#define RV_UNUSED_REGION7 0x10000000 +#ifndef RV_NMI_VEC +#define RV_NMI_VEC 0x11110000 +#endif +#define RV_PIC_BASE_ADDR 0x60000000 +#define RV_PIC_BITS 15 +#define RV_PIC_INT_WORDS 1 +#define RV_PIC_MEIE_COUNT 31 +#define RV_PIC_MEIE_MASK 0x1 +#define RV_PIC_MEIE_OFFSET 0x2000 +#define RV_PIC_MEIGWCLR_COUNT 31 +#define RV_PIC_MEIGWCLR_MASK 0x0 +#define RV_PIC_MEIGWCLR_OFFSET 0x5000 +#define RV_PIC_MEIGWCTRL_COUNT 31 +#define RV_PIC_MEIGWCTRL_MASK 0x3 +#define RV_PIC_MEIGWCTRL_OFFSET 0x4000 +#define RV_PIC_MEIP_COUNT 1 +#define RV_PIC_MEIP_MASK 0x0 +#define RV_PIC_MEIP_OFFSET 0x1000 +#define RV_PIC_MEIPL_COUNT 31 +#define RV_PIC_MEIPL_MASK 0xf +#define RV_PIC_MEIPL_OFFSET 0x0000 +#define RV_PIC_MEIPT_COUNT 31 +#define RV_PIC_MEIPT_MASK 0x0 +#define RV_PIC_MEIPT_OFFSET 0x3004 +#define RV_PIC_MPICCFG_COUNT 1 +#define RV_PIC_MPICCFG_MASK 0x1 +#define RV_PIC_MPICCFG_OFFSET 0x3000 +#define RV_PIC_OFFSET 0 +#define RV_PIC_REGION 0x6 +#define RV_PIC_SIZE 32 +#define RV_PIC_TOTAL_INT 31 +#define RV_PIC_TOTAL_INT_PLUS1 32 +#define RV_DATA_ACCESS_ADDR0 0x00000000 +#define RV_DATA_ACCESS_ADDR1 0x00000000 +#define RV_DATA_ACCESS_ADDR2 0x00000000 #define RV_DATA_ACCESS_ADDR3 0x00000000 +#define RV_DATA_ACCESS_ADDR4 0x00000000 +#define RV_DATA_ACCESS_ADDR5 0x00000000 +#define RV_DATA_ACCESS_ADDR6 0x00000000 +#define RV_DATA_ACCESS_ADDR7 0x00000000 +#define RV_DATA_ACCESS_ENABLE0 0x0 #define RV_DATA_ACCESS_ENABLE1 0x0 -#define RV_INST_ACCESS_ENABLE7 0x0 -#define RV_INST_ACCESS_ENABLE1 0x0 -#define RV_DATA_ACCESS_ENABLE7 0x0 -#define RV_DATA_ACCESS_ENABLE4 0x0 +#define RV_DATA_ACCESS_ENABLE2 0x0 #define RV_DATA_ACCESS_ENABLE3 0x0 -#define RV_INST_ACCESS_ENABLE0 0x0 -#define RV_INST_ACCESS_ENABLE4 0x0 -#define RV_INST_ACCESS_ENABLE3 0x0 -#define RV_DATA_ACCESS_ENABLE0 0x0 -#define RV_INST_ACCESS_ENABLE6 0x0 +#define RV_DATA_ACCESS_ENABLE4 0x0 +#define RV_DATA_ACCESS_ENABLE5 0x0 +#define RV_DATA_ACCESS_ENABLE6 0x0 +#define RV_DATA_ACCESS_ENABLE7 0x0 +#define RV_DATA_ACCESS_MASK0 0xffffffff +#define RV_DATA_ACCESS_MASK1 0xffffffff +#define RV_DATA_ACCESS_MASK2 0xffffffff #define RV_DATA_ACCESS_MASK3 0xffffffff -#define RV_DATA_ACCESS_ADDR4 0x00000000 +#define RV_DATA_ACCESS_MASK4 0xffffffff +#define RV_DATA_ACCESS_MASK5 0xffffffff +#define RV_DATA_ACCESS_MASK6 0xffffffff +#define RV_DATA_ACCESS_MASK7 0xffffffff +#define RV_INST_ACCESS_ADDR0 0x00000000 #define RV_INST_ACCESS_ADDR1 0x00000000 -#define RV_DATA_ACCESS_ENABLE6 0x0 -#define RV_INST_ACCESS_MASK3 0xffffffff +#define RV_INST_ACCESS_ADDR2 0x00000000 +#define RV_INST_ACCESS_ADDR3 0x00000000 #define RV_INST_ACCESS_ADDR4 0x00000000 -#define RV_DATA_ACCESS_ADDR1 0x00000000 -#define RV_DATA_ACCESS_ADDR5 0x00000000 #define RV_INST_ACCESS_ADDR5 0x00000000 -#define RV_INST_ACCESS_ADDR2 0x00000000 -#define RV_INST_ACCESS_MASK7 0xffffffff #define RV_INST_ACCESS_ADDR6 0x00000000 -#define RV_DATA_ACCESS_ADDR0 0x00000000 -#define RV_DATA_ACCESS_ADDR6 0x00000000 -#define RV_DATA_ACCESS_MASK7 0xffffffff -#define RV_DATA_ACCESS_ADDR2 0x00000000 -#define RV_INST_ACCESS_ADDR0 0x00000000 -#define RV_DATA_ACCESS_ADDR7 0x00000000 -#define RV_DATA_ACCESS_MASK2 0xffffffff -#define RV_DATA_ACCESS_MASK6 0xffffffff -#define RV_INST_ACCESS_MASK0 0xffffffff #define RV_INST_ACCESS_ADDR7 0x00000000 -#define RV_INST_ACCESS_MASK6 0xffffffff +#define RV_INST_ACCESS_ENABLE0 0x0 +#define RV_INST_ACCESS_ENABLE1 0x0 +#define RV_INST_ACCESS_ENABLE2 0x0 +#define RV_INST_ACCESS_ENABLE3 0x0 +#define RV_INST_ACCESS_ENABLE4 0x0 +#define RV_INST_ACCESS_ENABLE5 0x0 +#define RV_INST_ACCESS_ENABLE6 0x0 +#define RV_INST_ACCESS_ENABLE7 0x0 +#define RV_INST_ACCESS_MASK0 0xffffffff +#define RV_INST_ACCESS_MASK1 0xffffffff #define RV_INST_ACCESS_MASK2 0xffffffff -#define RV_DATA_ACCESS_MASK0 0xffffffff -#define RV_DATA_ACCESS_ENABLE2 0x0 +#define RV_INST_ACCESS_MASK3 0xffffffff +#define RV_INST_ACCESS_MASK4 0xffffffff #define RV_INST_ACCESS_MASK5 0xffffffff -#define RV_INST_ACCESS_ENABLE2 0x0 -#define RV_DATA_ACCESS_MASK5 0xffffffff -#define RV_PIC_TOTAL_INT 31 -#define RV_PIC_SIZE 32 -#define RV_PIC_TOTAL_INT_PLUS1 32 -#define RV_PIC_MEIPL_OFFSET 0x0000 -#define RV_PIC_MPICCFG_MASK 0x1 -#define RV_PIC_MEIPL_MASK 0xf -#define RV_PIC_BASE_ADDR 0x60000000 -#define RV_PIC_MEIPT_MASK 0x0 -#define RV_PIC_MEIPT_OFFSET 0x3004 -#define RV_PIC_MEIE_COUNT 31 -#define RV_PIC_MEIP_OFFSET 0x1000 -#define RV_PIC_BITS 15 -#define RV_PIC_MPICCFG_COUNT 1 -#define RV_PIC_INT_WORDS 1 -#define RV_PIC_MEIE_MASK 0x1 -#define RV_PIC_REGION 0x6 -#define RV_PIC_MEIE_OFFSET 0x2000 -#define RV_PIC_MEIP_MASK 0x0 -#define RV_PIC_MEIGWCLR_MASK 0x0 -#define RV_PIC_MEIPL_COUNT 31 -#define RV_PIC_MEIGWCTRL_MASK 0x3 -#define RV_PIC_MEIPT_COUNT 31 -#define RV_PIC_MEIGWCTRL_COUNT 31 -#define RV_PIC_OFFSET 0 -#define RV_PIC_MEIP_COUNT 1 -#define RV_PIC_MEIGWCLR_OFFSET 0x5000 -#define RV_PIC_MEIGWCLR_COUNT 31 -#define RV_PIC_MEIGWCTRL_OFFSET 0x4000 -#define RV_PIC_MPICCFG_OFFSET 0x3000 -#define RV_LDERR_ROLLBACK 1 +#define RV_INST_ACCESS_MASK6 0xffffffff +#define RV_INST_ACCESS_MASK7 0xffffffff +#define RV_PMP_ENTRIES 64 +#ifndef RV_RESET_VEC +#define RV_RESET_VEC 0x00000000 +#endif +#define RV_TARGET default_ahb #define CPU_TOP `RV_TOP.veer -#define RV_EXT_DATAWIDTH 64 -#define RV_ASSERT_ON -#define RV_STERR_ROLLBACK 0 #define RV_TOP `TOP.rvtop -#define RV_BUILD_AHB_LITE 1 -#define CLOCK_PERIOD 100 #define SDVT_AHB 1 #define TOP tb_top +#define RV_BUILD_AHB_LITE 1 +#define CLOCK_PERIOD 100 #define RV_EXT_ADDRWIDTH 32 -#ifndef RV_NMI_VEC -#define RV_NMI_VEC 0x11110000 -#endif -#define RV_ICCM_NUM_BANKS_4 -#define RV_ICCM_BANK_INDEX_LO 4 -#define RV_ICCM_RESERVED 0x1000 -#define RV_ICCM_SIZE_128 -#define RV_ICCM_SADR 0x40000000 -#define RV_ICCM_EADR 0x4001ffff -#define RV_ICCM_OFFSET 0x0 -#define RV_ICCM_SIZE 128 -#define RV_ICCM_BANK_HI 3 -#define RV_ICCM_NUM_BANKS 4 -#define RV_ICCM_INDEX_BITS 13 -#define RV_ICCM_ENABLE 1 -#define RV_ICCM_BITS 17 -#define RV_ICCM_ROWS 8192 -#define RV_ICCM_REGION 0x4 -#define RV_ICCM_DATA_CELL ram_8192x39 -#define RV_ICCM_BANK_BITS 2 -#define RV_LSU_STBUF_DEPTH 4 -#define RV_TIMER_LEGAL_EN 1 -#define RV_BITMANIP_ZBA 1 -#define RV_BITMANIP_ZBS 1 -#define RV_BITMANIP_ZBR 0 -#define RV_LSU_NUM_NBLOAD 4 -#define RV_BITMANIP_ZBB 1 -#define RV_BITMANIP_ZBP 0 -#define RV_BITMANIP_ZBE 0 -#define RV_FAST_INTERRUPT_REDIRECT 1 -#define RV_DIV_NEW 1 -#define RV_LSU_NUM_NBLOAD_WIDTH 2 -#define RV_DIV_BIT 4 -#define RV_BITMANIP_ZBC 1 -#define RV_BITMANIP_ZBF 0 -#define RV_ICCM_ONLY 1 -#define RV_DMA_BUF_DEPTH 5 -#define RV_LSU2DMA 0 -#ifndef RV_SERIALIO -#define RV_SERIALIO 0xf0580000 -#endif -#define RV_UNUSED_REGION1 0xa0000000 -#define RV_UNUSED_REGION0 0xb0000000 -#define RV_UNUSED_REGION2 0x90000000 -#define RV_DEBUG_SB_MEM 0xc0580000 -#define RV_EXTERNAL_DATA_1 0xd0000000 -#define RV_UNUSED_REGION4 0x70000000 -#define RV_UNUSED_REGION6 0x20000000 -#ifndef RV_EXTERNAL_DATA -#define RV_EXTERNAL_DATA 0xe0580000 -#endif -#define RV_UNUSED_REGION3 0x80000000 -#define RV_UNUSED_REGION5 0x30000000 -#define RV_UNUSED_REGION7 0x10000000 -#define RV_LSU_SB_BITS 17 -#define RV_DCCM_SADR 0x50000000 -#define RV_DCCM_RESERVED 0x1400 -#define RV_DCCM_SIZE_128 -#define RV_DCCM_DATA_WIDTH 32 -#define RV_DCCM_EADR 0x5001ffff -#define RV_DCCM_WIDTH_BITS 2 -#define RV_DCCM_SIZE 128 -#define RV_DCCM_OFFSET 0x00000 -#define RV_DCCM_BYTE_WIDTH 4 -#define RV_DCCM_ECC_WIDTH 7 -#define RV_DCCM_NUM_BANKS_4 -#define RV_DCCM_FDATA_WIDTH 39 -#define RV_DCCM_BITS 17 -#define RV_DCCM_ROWS 8192 -#define RV_DCCM_DATA_CELL ram_8192x39 -#define RV_DCCM_REGION 0x5 -#define RV_DCCM_BANK_BITS 2 -#define RV_DCCM_NUM_BANKS 4 -#define RV_DCCM_ENABLE 1 -#define RV_DCCM_INDEX_BITS 13 +#define RV_EXT_DATAWIDTH 64 +#define RV_LDERR_ROLLBACK 1 +#define RV_STERR_ROLLBACK 0 +#define RV_ASSERT_ON #define RV_XLEN 32 + +#endif // RV_DEFINES diff --git a/src/riscv_core/veer_el2/rtl/common_defines.sv b/src/riscv_core/veer_el2/rtl/common_defines.sv index 07d6623d8..bf10f8dba 100644 --- a/src/riscv_core/veer_el2/rtl/common_defines.sv +++ b/src/riscv_core/veer_el2/rtl/common_defines.sv @@ -16,9 +16,9 @@ // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -// This is an automatically generated file by cwhitehead on Wed Nov 6 18:02:24 PST 2024 +// This is an automatically generated file by cwhitehead on Wed Nov 13 10:25:09 PST 2024 // -// cmd: veer -target=default_ahb -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=128 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_enable=1 -set=iccm_num_banks=4 -set=iccm_region=0x4 -set=iccm_offset=0x0 -set=iccm_size=128 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -set=user_mode=1 -set=pmp_entries=64 -set=smepmp=1 -set=reset_vec=0x00000000 -fpga_optimize=0 -snapshot=20241106_cptra_en_pmp +// cmd: veer -target=default_ahb -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=128 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_enable=1 -set=iccm_num_banks=4 -set=iccm_region=0x4 -set=iccm_offset=0x0 -set=iccm_size=128 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -set=pmp_entries=64 -set=reset_vec=0x00000000 -fpga_optimize=0 -snapshot=20241106_cptra_en_pmp // `ifndef RV_COMMON_DEFINES `define RV_COMMON_DEFINES @@ -79,7 +79,6 @@ `define RV_LSU_NUM_NBLOAD_WIDTH 2 `define RV_LSU_STBUF_DEPTH 4 `define RV_TIMER_LEGAL_EN 1 -`define RV_USER_MODE 1 `define RV_DCCM_BANK_BITS 2 `define RV_DCCM_BITS 17 `define RV_DCCM_BYTE_WIDTH 4 @@ -246,7 +245,6 @@ `define RV_INST_ACCESS_MASK6 'hffffffff `define RV_INST_ACCESS_MASK7 'hffffffff `define RV_PMP_ENTRIES 64 -`define RV_SMEPMP 1 `define REGWIDTH 32 `define RV_RESET_VEC 'h00000000 `define RV_RET_STACK_SIZE 8 diff --git a/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv b/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv index 1dc734d3a..3459843d7 100644 --- a/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv @@ -110,7 +110,7 @@ module el2_dec_pmp_ctl `ifdef RV_SMEPMP assign csr_wdata = raw_wdata & 8'b10011111; `else - assign csr_wdata = (raw_wdata & 8'b00000001) ? (raw_wdata & 8'b10011111) : (raw_wdata & 8'b10011101); + assign csr_wdata = raw_wdata[0] ? (raw_wdata & 8'b10011111) : (raw_wdata & 8'b10011101); `endif rvdffe #(8) pmpcfg_ff (.*, .clk(free_l2clk), diff --git a/src/riscv_core/veer_el2/rtl/el2_param.vh b/src/riscv_core/veer_el2/rtl/el2_param.vh index eab3a4837..36a7b1507 100644 --- a/src/riscv_core/veer_el2/rtl/el2_param.vh +++ b/src/riscv_core/veer_el2/rtl/el2_param.vh @@ -189,8 +189,8 @@ parameter el2_param_t pt = '{ SB_BUS_ID : 5'h01 , SB_BUS_PRTY : 6'h02 , SB_BUS_TAG : 8'h01 , - SMEPMP : 1'h1 , + SMEPMP : 4'h0 , TIMER_LEGAL_EN : 5'h01 , - USER_MODE : 1'h1 + USER_MODE : 4'h0 } -// parameter el2_param_t pt = 2291'h04840400010040010840000020908200002840004808220A0C848200060410C00000000000000000000000000000000000000000000000000000000000000000000000000000000003FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC104420401C21386810141400000000800820428042010840830C2010281840200081002008E0C0801004040800C01002100400606810104100C08110E10068102080800000000400420300000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF000210181010441000060000000078083008007C040100202100C3 +// parameter el2_param_t pt = 2291'h04840400010040010840000020908200002840004808220A0C848200060410C00000000000000000000000000000000000000000000000000000000000000000000000000000000003FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC104420401C21386810141400000000800820428042010840830C2010281840200081002008E0C0801004040800C01002100400606810104100C08110E10068102080800000000400420300000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF000210181010441000060000000078083008007C04010020210082 diff --git a/src/riscv_core/veer_el2/rtl/riscv_rev_info b/src/riscv_core/veer_el2/rtl/riscv_rev_info index 275dc24c4..8658a2dfb 100644 --- a/src/riscv_core/veer_el2/rtl/riscv_rev_info +++ b/src/riscv_core/veer_el2/rtl/riscv_rev_info @@ -1,8 +1,8 @@ -commit ad30bae95f921c7356abebaf9f1f65230c5c7b9f -Merge: d4e359372f8 0ec4c4d5db0 +commit fe63594a775c1258a6fec06e574c4fe03f629cd4 +Merge: 78cac32bfcc 2d868166ce3 Author: Tomasz Michalak -Date: Thu Oct 24 13:13:26 2024 +0200 +Date: Fri Nov 8 15:57:47 2024 +0100 - Merge pull request #253 from chipsalliance/wsip/ci_fix + Merge pull request #259 from chipsalliance/wsip/export_dmi - CI fix: use docker image + export DMI signals diff --git a/tools/scripts/veer_build_command.sh b/tools/scripts/veer_build_command.sh index ce2132742..03d51961e 100644 --- a/tools/scripts/veer_build_command.sh +++ b/tools/scripts/veer_build_command.sh @@ -84,9 +84,7 @@ $RV_ROOT/configs/veer.config \ -set=bitmanip_zbp=0 \ -set=bitmanip_zbr=0 \ -set=bitmanip_zbs=1 \ --set=user_mode=1 \ -set=pmp_entries=64 \ --set=smepmp=1 \ -set=reset_vec=0x00000000 \ -fpga_optimize=0 \ -snapshot=$1