From 098519cb1043d9b0d1f213669e1bfcdbacb033b5 Mon Sep 17 00:00:00 2001 From: Caleb <11879229+calebofearth@users.noreply.github.com> Date: Mon, 11 Nov 2024 18:02:52 -0800 Subject: [PATCH] Upgrade RV core to latest, enable SMEPMP and User Mode (#628) * Override reset_vec to 0x0 with script call option (no longer need to hand-edit script) * Refactor iccm config for maintainability * VeeR core update to latest design file version * Add rev info file to indicate VeeR version consumed * Remove JTAG IDCODE command, as previously done * Route a core_enable signal to conditionally disable internal core TAP access * Add a dmi_active output signal * Updated RV instance for compatibility with latest DMI export signals * Updated VeeR mem export interface splits data/ecc * Enable SMEPMP with 64-entries; enable user-mode * Update directory includes/dependencies * Requires soc_ifc_pkg * Port width fix * First index is for bank number - fix * Move localparams to top of file, so they exist at the first usage * Update license headers on RV core * Regenerate file lists * Revert latch fix that causes Verilator failures * Replace 'repeat' (verilator dislikes) with for-loop; add missing begin-end * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-rv-upgrade' with updated timestamp and hash after successful run --- .github/scripts/license_header_check.sh | 2 +- .github/workflow_metadata/pr_hash | 2 +- .github/workflow_metadata/pr_timestamp | 2 +- src/axi/config/axi_dma.vf | 5 + src/axi/config/compile.yml | 1 + src/integration/config/caliptra_top.vf | 24 +- src/integration/config/caliptra_top_tb.vf | 24 +- src/integration/config/caliptra_top_tb_pkg.vf | 24 +- .../config/caliptra_top_trng_tb.vf | 24 +- src/integration/rtl/caliptra_top.sv | 40 +- src/integration/tb/caliptra_top_tb_soc_bfm.sv | 25 +- .../tb/caliptra_veer_sram_export.sv | 88 +- .../config/uvmf_caliptra_top.vf | 18 +- .../config/uvmf_caliptra_top_itrng.vf | 18 +- .../config/uvmf_caliptra_top_vip.vf | 5 +- src/riscv_core/veer_el2/config/compile.yml | 18 +- .../veer_el2/config/el2_veer_pkg.vf | 9 +- .../veer_el2/config/el2_veer_wrapper.vf | 24 +- .../veer_el2/config/el2_veer_wrapper_tb.vf | 21 +- src/riscv_core/veer_el2/rtl/common_defines.sv | 443 +++--- src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv | 27 + src/riscv_core/veer_el2/rtl/dec/cdecode | 17 +- .../rtl/dec/{csrdecode => csrdecode_m} | 22 +- src/riscv_core/veer_el2/rtl/dec/csrdecode_mu | 343 +++++ src/riscv_core/veer_el2/rtl/dec/decode | 9 +- src/riscv_core/veer_el2/rtl/dec/el2_dec.sv | 616 ++++---- .../veer_el2/rtl/dec/el2_dec_decode_ctl.sv | 289 ++-- .../veer_el2/rtl/dec/el2_dec_pmp_ctl.sv | 176 +++ .../veer_el2/rtl/dec/el2_dec_tlu_ctl.sv | 1268 ++++++++++------- src/riscv_core/veer_el2/rtl/dmi/dmi_mux.v | 67 + src/riscv_core/veer_el2/rtl/el2_mem.sv | 12 +- src/riscv_core/veer_el2/rtl/el2_param.vh | 8 +- src/riscv_core/veer_el2/rtl/el2_pdef.vh | 4 + src/riscv_core/veer_el2/rtl/el2_pmp.sv | 313 ++++ src/riscv_core/veer_el2/rtl/el2_veer.sv | 158 +- .../veer_el2/rtl/el2_veer_wrapper.sv | 236 ++- .../veer_el2/rtl/exu/el2_exu_alu_ctl.sv | 4 +- src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv | 29 +- .../veer_el2/rtl/ifu/el2_ifu_compress_ctl.sv | 31 +- .../veer_el2/rtl/ifu/el2_ifu_ic_mem.sv | 78 +- .../veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv | 28 +- .../veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv | 133 +- .../rtl/include/el2_dec_csr_equ_m.svh | 462 ++++++ .../rtl/include/el2_dec_csr_equ_mu.svh | 555 ++++++++ .../veer_el2/rtl/include/el2_def.sv | 40 +- .../veer_el2/rtl/lib/ahb_to_axi4.sv | 36 +- .../veer_el2/rtl/lib/axi4_to_ahb.sv | 50 +- src/riscv_core/veer_el2/rtl/lib/beh_lib.sv | 1 - src/riscv_core/veer_el2/rtl/lib/el2_lib.sv | 4 +- src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv | 153 +- src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv | 52 +- .../veer_el2/rtl/lsu/el2_lsu_addrcheck.sv | 23 +- .../veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv | 24 + .../veer_el2/rtl/lsu/el2_lsu_bus_intf.sv | 24 + .../veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv | 29 +- .../veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv | 35 +- src/riscv_core/veer_el2/rtl/riscv_rev_info | 8 + src/soc_ifc/config/soc_ifc_tb.vf | 1 + src/soc_ifc/config/soc_ifc_top.vf | 5 +- .../uvmf_soc_ifc/config/uvmf_soc_ifc.vf | 5 +- .../uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf | 5 +- tools/scripts/veer_build_command.sh | 19 +- 62 files changed, 4459 insertions(+), 1757 deletions(-) rename src/riscv_core/veer_el2/rtl/dec/{csrdecode => csrdecode_m} (94%) create mode 100644 src/riscv_core/veer_el2/rtl/dec/csrdecode_mu create mode 100644 src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv create mode 100644 src/riscv_core/veer_el2/rtl/dmi/dmi_mux.v create mode 100644 src/riscv_core/veer_el2/rtl/el2_pmp.sv mode change 100755 => 100644 src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv create mode 100644 src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_m.svh create mode 100644 src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_mu.svh create mode 100644 src/riscv_core/veer_el2/rtl/riscv_rev_info diff --git a/.github/scripts/license_header_check.sh b/.github/scripts/license_header_check.sh index 996a3c7f4..36a617989 100755 --- a/.github/scripts/license_header_check.sh +++ b/.github/scripts/license_header_check.sh @@ -78,7 +78,7 @@ exclude_dir='{uvmf*,.git,cmark,caliptra_reg_html,caliptra_top_reg_html,sha256,sh exclude_suffix='*.{tcl,txt,js,htm,html,json,vf,yml,woff,rsp,rdl,bashrc,waiver,cfg,hex,rc,exe,pdf,png,hvp,svg,log}' exclude_regs='*_reg*.{sv,rdl}' exclude_csr='*_csr*.*' -exclude_file='{sglint_waivers,pr_hash,pr_timestamp,.git,.git-comodules,.gitignore,.gitmodules,spyglass_lint.policy,ascent.ctl,clp_mapfile,readme.md,README.md,SECURITY.md,c_sample.c,test_dilithium5}' +exclude_file='{sglint_waivers,pr_hash,pr_timestamp,.git,.git-comodules,.gitignore,.gitmodules,spyglass_lint.policy,ascent.ctl,clp_mapfile,readme.md,README.md,SECURITY.md,c_sample.c,test_dilithium5,riscv_rev_info}' apache_patn='Licensed under the Apache License\|Apache License, Version 2\.0 (the \"License\")' # Recursive find through repository with some major exclusions diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash index 029346579..6bbff16b2 100644 --- a/.github/workflow_metadata/pr_hash +++ b/.github/workflow_metadata/pr_hash @@ -1 +1 @@ -374c7baec55c97611a6c6065eb7ea4fb78561213bb5bdff113bf7d35ff86b3aa85d352dcf6d2e4327ccbddbadba392ae \ No newline at end of file +74eb435936566a8abc256940418d44e776b9e86cc0297e96fdd1513f1e36e70fee5d57590ff14eaaabf74c6727d10309 \ No newline at end of file diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp index 44425d126..92280333a 100644 --- a/.github/workflow_metadata/pr_timestamp +++ b/.github/workflow_metadata/pr_timestamp @@ -1 +1 @@ -1731352011 \ No newline at end of file +1731369802 \ No newline at end of file diff --git a/src/axi/config/axi_dma.vf b/src/axi/config/axi_dma.vf index 24dc6200c..f71cf6b19 100644 --- a/src/axi/config/axi_dma.vf +++ b/src/axi/config/axi_dma.vf @@ -3,6 +3,7 @@ +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/axi/rtl ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh @@ -29,6 +30,8 @@ ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv @@ -64,6 +67,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv diff --git a/src/axi/config/compile.yml b/src/axi/config/compile.yml index d0ccd4b9c..dab21ac8d 100644 --- a/src/axi/config/compile.yml +++ b/src/axi/config/compile.yml @@ -47,6 +47,7 @@ requires: - libs - caliptra_prim - axi_pkg + - soc_ifc_pkg targets: rtl: directories: [$COMPILE_ROOT/rtl] diff --git a/src/integration/config/caliptra_top.vf b/src/integration/config/caliptra_top.vf index fc1c37e7e..3d190c58d 100644 --- a/src/integration/config/caliptra_top.vf +++ b/src/integration/config/caliptra_top.vf @@ -3,7 +3,6 @@ +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl +incdir+${CALIPTRA_ROOT}/src/datavault/rtl -+incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/src/doe/rtl +incdir+${CALIPTRA_ROOT}/submodules/adams-bridge/src/mldsa_top/rtl @@ -16,9 +15,11 @@ +incdir+${CALIPTRA_ROOT}/src/axi/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/tb +incdir+${CALIPTRA_ROOT}/src/csrng/rtl ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl +incdir+${CALIPTRA_ROOT}/src/sha512/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/rtl @@ -63,8 +64,6 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv @@ -119,6 +118,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv @@ -127,14 +128,7 @@ ${CALIPTRA_ROOT}/src/entropy_src/tb/physical_rng.sv ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv @@ -142,6 +136,8 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_ib_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_trigger.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_mux.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v @@ -173,6 +169,12 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_trigger.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pmp.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus.sv @@ -390,6 +392,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv diff --git a/src/integration/config/caliptra_top_tb.vf b/src/integration/config/caliptra_top_tb.vf index 79f056295..75f51e370 100644 --- a/src/integration/config/caliptra_top_tb.vf +++ b/src/integration/config/caliptra_top_tb.vf @@ -6,7 +6,6 @@ +incdir+${CALIPTRA_ROOT}/src/axi/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl +incdir+${CALIPTRA_ROOT}/src/datavault/rtl -+incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/submodules/adams-bridge/src/mldsa_top/rtl +incdir+${CALIPTRA_ROOT}/submodules/adams-bridge/src/abr_libs/rtl @@ -17,6 +16,7 @@ +incdir+${CALIPTRA_ROOT}/submodules/adams-bridge/src/norm_check/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/tb +incdir+${CALIPTRA_ROOT}/src/csrng/rtl @@ -29,6 +29,7 @@ +incdir+${CALIPTRA_ROOT}/src/keyvault/coverage +incdir+${CALIPTRA_ROOT}/src/integration/tb +incdir+${CALIPTRA_ROOT}/src/integration/coverage ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl +incdir+${CALIPTRA_ROOT}/src/sha512/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/rtl @@ -77,8 +78,6 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv @@ -130,6 +129,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv @@ -169,14 +170,7 @@ ${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv ${CALIPTRA_ROOT}/src/axi/rtl/caliptra_axi_sram.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv @@ -184,6 +178,8 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_ib_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_trigger.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_mux.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v @@ -215,6 +211,12 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_trigger.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pmp.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus.sv @@ -427,6 +429,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv diff --git a/src/integration/config/caliptra_top_tb_pkg.vf b/src/integration/config/caliptra_top_tb_pkg.vf index 408faa181..5b25bdef6 100644 --- a/src/integration/config/caliptra_top_tb_pkg.vf +++ b/src/integration/config/caliptra_top_tb_pkg.vf @@ -6,7 +6,6 @@ +incdir+${CALIPTRA_ROOT}/src/axi/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl +incdir+${CALIPTRA_ROOT}/src/datavault/rtl -+incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/submodules/adams-bridge/src/mldsa_top/rtl +incdir+${CALIPTRA_ROOT}/submodules/adams-bridge/src/abr_libs/rtl @@ -17,6 +16,7 @@ +incdir+${CALIPTRA_ROOT}/submodules/adams-bridge/src/norm_check/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/tb +incdir+${CALIPTRA_ROOT}/src/csrng/rtl @@ -29,6 +29,7 @@ +incdir+${CALIPTRA_ROOT}/src/keyvault/coverage +incdir+${CALIPTRA_ROOT}/src/integration/tb +incdir+${CALIPTRA_ROOT}/src/integration/coverage ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl +incdir+${CALIPTRA_ROOT}/src/sha512/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/rtl @@ -77,8 +78,6 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv @@ -130,6 +129,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv @@ -168,14 +169,7 @@ ${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv ${CALIPTRA_ROOT}/src/axi/rtl/caliptra_axi_sram.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv @@ -183,6 +177,8 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_ib_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_trigger.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_mux.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v @@ -214,6 +210,12 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_trigger.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pmp.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus.sv @@ -426,6 +428,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv diff --git a/src/integration/config/caliptra_top_trng_tb.vf b/src/integration/config/caliptra_top_trng_tb.vf index 79f056295..75f51e370 100644 --- a/src/integration/config/caliptra_top_trng_tb.vf +++ b/src/integration/config/caliptra_top_trng_tb.vf @@ -6,7 +6,6 @@ +incdir+${CALIPTRA_ROOT}/src/axi/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl +incdir+${CALIPTRA_ROOT}/src/datavault/rtl -+incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/submodules/adams-bridge/src/mldsa_top/rtl +incdir+${CALIPTRA_ROOT}/submodules/adams-bridge/src/abr_libs/rtl @@ -17,6 +16,7 @@ +incdir+${CALIPTRA_ROOT}/submodules/adams-bridge/src/norm_check/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/tb +incdir+${CALIPTRA_ROOT}/src/csrng/rtl @@ -29,6 +29,7 @@ +incdir+${CALIPTRA_ROOT}/src/keyvault/coverage +incdir+${CALIPTRA_ROOT}/src/integration/tb +incdir+${CALIPTRA_ROOT}/src/integration/coverage ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl +incdir+${CALIPTRA_ROOT}/src/sha512/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/rtl @@ -77,8 +78,6 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv @@ -130,6 +129,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv @@ -169,14 +170,7 @@ ${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv ${CALIPTRA_ROOT}/src/axi/rtl/caliptra_axi_sram.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv -${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv @@ -184,6 +178,8 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_ib_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_trigger.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_mux.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v @@ -215,6 +211,12 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_trigger.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pmp.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus.sv @@ -427,6 +429,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index b82e89942..ad6673002 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -169,6 +169,8 @@ module caliptra_top logic [`CLP_OBF_UDS_DWORDS-1:0][31:0] obf_uds_seed; //caliptra uncore jtag ports & pertinent logic + logic cptra_core_dmi_enable; + logic cptra_uncore_dmi_enable; logic cptra_uncore_dmi_reg_en; logic cptra_uncore_dmi_reg_wr_en; logic [31:0] cptra_uncore_dmi_reg_rdata; @@ -386,6 +388,10 @@ always_comb begin intr[NUM_INTR-1:`VEER_INTR_VEC_MAX_ASSIGNED] = '0; end +always_comb cptra_core_dmi_enable = ~(cptra_security_state_Latched.debug_locked); +always_comb cptra_uncore_dmi_enable = ~(cptra_security_state_Latched.debug_locked) | + ((cptra_security_state_Latched.debug_locked) & (cptra_security_state_Latched.device_lifecycle == DEVICE_MANUFACTURING)); + el2_veer_wrapper rvtop ( `ifdef CALIPTRA_FORCE_CPU_RESET .rst_l ( 1'b0 ), @@ -461,6 +467,7 @@ el2_veer_wrapper rvtop ( .dma_hreadyout ( responder_inst[`CALIPTRA_SLAVE_SEL_DDMA].hreadyout ), .timer_int ( timer_int), + .soft_int ( soft_int ), .extintsrc_req ( intr ), .lsu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface @@ -468,6 +475,15 @@ el2_veer_wrapper rvtop ( .dbg_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB Debug master interface .dma_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB slave interface + // ICCM/DCCM ECC status + .iccm_ecc_single_error (rv_ecc_sts.cptra_iccm_ecc_single_error), + .iccm_ecc_double_error (rv_ecc_sts.cptra_iccm_ecc_double_error), + .dccm_ecc_single_error (rv_ecc_sts.cptra_dccm_ecc_single_error), + .dccm_ecc_double_error (rv_ecc_sts.cptra_dccm_ecc_double_error), + + .ic_data_ext_in_pkt (48'h0), + .ic_tag_ext_in_pkt (24'h0), + .trace_rv_i_insn_ip (trace_rv_i_insn_ip), .trace_rv_i_address_ip (trace_rv_i_address_ip), .trace_rv_i_valid_ip (trace_rv_i_valid_ip), @@ -483,14 +499,15 @@ el2_veer_wrapper rvtop ( .jtag_tdo ( jtag_tdo ), .jtag_tdoEn ( jtag_tdoEn ), - //caliptra uncore jtag ports - .cptra_uncore_dmi_reg_en ( cptra_uncore_dmi_reg_en ), - .cptra_uncore_dmi_reg_wr_en ( cptra_uncore_dmi_reg_wr_en ), - .cptra_uncore_dmi_reg_rdata ( cptra_uncore_dmi_reg_rdata ), - .cptra_uncore_dmi_reg_addr ( cptra_uncore_dmi_reg_addr ), - .cptra_uncore_dmi_reg_wdata ( cptra_uncore_dmi_reg_wdata ), - .cptra_security_state_Latched ( cptra_security_state_Latched), - .cptra_dmi_reg_en_preQ ( cptra_dmi_reg_en_preQ ), + .dmi_core_enable ( cptra_core_dmi_enable ), + // DMI port for uncore + .dmi_uncore_enable( cptra_uncore_dmi_enable ), + .dmi_uncore_en ( cptra_uncore_dmi_reg_en ), + .dmi_uncore_wr_en ( cptra_uncore_dmi_reg_wr_en ), + .dmi_uncore_addr ( cptra_uncore_dmi_reg_addr ), + .dmi_uncore_wdata ( cptra_uncore_dmi_reg_wdata ), + .dmi_uncore_rdata ( cptra_uncore_dmi_reg_rdata ), + .dmi_active ( cptra_dmi_reg_en_preQ ), .mpc_debug_halt_ack ( mpc_debug_halt_ack), .mpc_debug_halt_req ( 1'b0), @@ -514,13 +531,6 @@ el2_veer_wrapper rvtop ( // Caliptra Memory Export Interface .el2_mem_export (el2_mem_export), - // Caliptra ECC status signals - .cptra_iccm_ecc_single_error(rv_ecc_sts.cptra_iccm_ecc_single_error), - .cptra_iccm_ecc_double_error(rv_ecc_sts.cptra_iccm_ecc_double_error), - .cptra_dccm_ecc_single_error(rv_ecc_sts.cptra_dccm_ecc_single_error), - .cptra_dccm_ecc_double_error(rv_ecc_sts.cptra_dccm_ecc_double_error), - - .soft_int (soft_int), .core_id ('0), .scan_mode ( scan_mode ), // To enable scan mode .mbist_mode ( 1'b0 ) // to enable mbist diff --git a/src/integration/tb/caliptra_top_tb_soc_bfm.sv b/src/integration/tb/caliptra_top_tb_soc_bfm.sv index 579c174df..cdbbef403 100644 --- a/src/integration/tb/caliptra_top_tb_soc_bfm.sv +++ b/src/integration/tb/caliptra_top_tb_soc_bfm.sv @@ -193,7 +193,7 @@ import caliptra_top_tb_pkg::*; #( wait(ready_for_fuses == 1); $display ("CLP: Ready for fuse download\n"); - repeat(5) @(posedge core_clk); + for (int rpt=0; rpt < 5; rpt++) @(posedge core_clk); $display ("SoC: Writing obfuscated UDS to fuse bank\n"); for (int dw=0; dw < `CLP_OBF_UDS_DWORDS; dw++) begin @@ -239,7 +239,7 @@ import caliptra_top_tb_pkg::*; #( // Mailbox flow if (ready_for_fw_push) begin - repeat(5) @(posedge core_clk); + for (int rpt=0; rpt<5; rpt++) @(posedge core_clk); $display ("CLP: Ready for firmware push\n"); $write ("SoC: Requesting mailbox lock..."); @@ -443,32 +443,35 @@ import caliptra_top_tb_pkg::*; #( end: BOOT_AND_CMD_FLOW begin: CLK_GATE_FLOW wait(cycleCnt_smpl_en); - repeat(2000) @(negedge core_clk); + for (int rpt=0; rpt<2000; rpt++) @(negedge core_clk); - if (int_flag) + if (int_flag) begin $display("SoC (clk_gate_flow): Forcing soft_int = 1. cycleCnt [%d]\n", cycleCnt); force caliptra_top_dut.soft_int = 1'b1; - repeat(2) @(negedge core_clk); + for (int rpt=0; rpt<2; rpt++) @(negedge core_clk); $display("SoC (clk_gate_flow): Releasing soft_int = 1. cycleCnt [%d]\n", cycleCnt); release caliptra_top_dut.soft_int; + end - repeat(5000) @(negedge core_clk); + for (int rpt=0; rpt<5000; rpt++) @(negedge core_clk); - if (int_flag) + if (int_flag) begin $display("SoC (clk_gate_flow): Forcing timer_int = 1. cycleCnt [%d]\n", cycleCnt); force caliptra_top_dut.timer_int = 1'b1; - repeat(2) @(negedge core_clk); + for (int rpt=0; rpt<2; rpt++) @(negedge core_clk); $display("SoC (clk_gate_flow): Releasing timer_int = 1. cycleCnt [%d]\n", cycleCnt); release caliptra_top_dut.timer_int; + end - repeat(8000) @(negedge core_clk); + for (int rpt=0; rpt<8000; rpt++) @(negedge core_clk); - if (int_flag) + if (int_flag) begin $display("SoC (clk_gate_flow): Forcing soft_int = 1. cycleCnt [%d]\n", cycleCnt); force caliptra_top_dut.soft_int = 1'b1; - repeat(2) @(negedge core_clk); + for (int rpt=0; rpt<2; rpt++) @(negedge core_clk); $display("SoC (clk_gate_flow): Releasing soft_int = 1. cycleCnt [%d]\n", cycleCnt); release caliptra_top_dut.soft_int; + end wait(cptra_rst_b == 0); end: CLK_GATE_FLOW diff --git a/src/integration/tb/caliptra_veer_sram_export.sv b/src/integration/tb/caliptra_veer_sram_export.sv index 04e717840..0dd47e7df 100644 --- a/src/integration/tb/caliptra_veer_sram_export.sv +++ b/src/integration/tb/caliptra_veer_sram_export.sv @@ -113,8 +113,8 @@ for (genvar i=0; i corresponding tag - input logic lsu_nonblock_load_inv_r, // invalidate request for nonblock load r - input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag - input logic lsu_nonblock_load_data_valid, // valid nonblock load data back - input logic lsu_nonblock_load_data_error, // nonblock load bus error - input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag - input logic [31:0] lsu_nonblock_load_data, // nonblock load data - input logic lsu_pmu_bus_trxn, // D side bus transaction - input logic lsu_pmu_bus_misaligned, // D side bus misaligned - input logic lsu_pmu_bus_error, // D side bus error - input logic lsu_pmu_bus_busy, // D side bus busy - input logic lsu_pmu_misaligned_m, // D side load or store misaligned - input logic lsu_pmu_load_external_m, // D side bus load - input logic lsu_pmu_store_external_m, // D side bus store - input logic dma_pmu_dccm_read, // DMA DCCM read - input logic dma_pmu_dccm_write, // DMA DCCM write - input logic dma_pmu_any_read, // DMA read - input logic dma_pmu_any_write, // DMA write + input logic lsu_nonblock_load_valid_m, // valid nonblock load at m + input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // -> corresponding tag + input logic lsu_nonblock_load_inv_r, // invalidate request for nonblock load r + input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag + input logic lsu_nonblock_load_data_valid, // valid nonblock load data back + input logic lsu_nonblock_load_data_error, // nonblock load bus error + input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag + input logic [31:0] lsu_nonblock_load_data, // nonblock load data - input logic [31:1] lsu_fir_addr, // Fast int address - input logic [1:0] lsu_fir_error, // Fast int lookup error + input logic lsu_pmu_bus_trxn, // D side bus transaction + input logic lsu_pmu_bus_misaligned, // D side bus misaligned + input logic lsu_pmu_bus_error, // D side bus error + input logic lsu_pmu_bus_busy, // D side bus busy + input logic lsu_pmu_misaligned_m, // D side load or store misaligned + input logic lsu_pmu_load_external_m, // D side bus load + input logic lsu_pmu_store_external_m, // D side bus store + input logic dma_pmu_dccm_read, // DMA DCCM read + input logic dma_pmu_dccm_write, // DMA DCCM write + input logic dma_pmu_any_read, // DMA read + input logic dma_pmu_any_write, // DMA write - input logic ifu_pmu_instr_aligned, // aligned instructions - input logic ifu_pmu_fetch_stall, // fetch unit stalled - input logic ifu_pmu_ic_miss, // icache miss - input logic ifu_pmu_ic_hit, // icache hit - input logic ifu_pmu_bus_error, // Instruction side bus error - input logic ifu_pmu_bus_busy, // Instruction side bus busy - input logic ifu_pmu_bus_trxn, // Instruction side bus transaction + input logic [31:1] lsu_fir_addr, // Fast int address + input logic [ 1:0] lsu_fir_error, // Fast int lookup error - input logic ifu_ic_error_start, // IC single bit error - input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error + input logic ifu_pmu_instr_aligned, // aligned instructions + input logic ifu_pmu_fetch_stall, // fetch unit stalled + input logic ifu_pmu_ic_miss, // icache miss + input logic ifu_pmu_ic_hit, // icache hit + input logic ifu_pmu_bus_error, // Instruction side bus error + input logic ifu_pmu_bus_busy, // Instruction side bus busy + input logic ifu_pmu_bus_trxn, // Instruction side bus transaction - input logic [3:0] lsu_trigger_match_m, - input logic dbg_cmd_valid, // debugger abstract command valid - input logic dbg_cmd_write, // command is a write - input logic [1:0] dbg_cmd_type, // command type - input logic [31:0] dbg_cmd_addr, // command address - input logic [1:0] dbg_cmd_wrdata, // command write data, for fence/fence_i + input logic ifu_ic_error_start, // IC single bit error + input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error + input logic [ 3:0] lsu_trigger_match_m, + input logic dbg_cmd_valid, // debugger abstract command valid + input logic dbg_cmd_write, // command is a write + input logic [ 1:0] dbg_cmd_type, // command type + input logic [31:0] dbg_cmd_addr, // command address + input logic [ 1:0] dbg_cmd_wrdata, // command write data, for fence/fence_i - input logic ifu_i0_icaf, // icache access fault - input logic [1:0] ifu_i0_icaf_type, // icache access fault type - input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst - input logic ifu_i0_dbecc, // icache/iccm double-bit error + input logic ifu_i0_icaf, // icache access fault + input logic [1:0] ifu_i0_icaf_type, // icache access fault type - input logic lsu_idle_any, // lsu idle for halting + input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst + input logic ifu_i0_dbecc, // icache/iccm double-bit error - input el2_br_pkt_t i0_brp, // branch packet - input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index - input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR - input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag - input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index + input logic lsu_idle_any, // lsu idle for halting - input el2_lsu_error_pkt_t lsu_error_pkt_r, // LSU exception/error packet - input logic lsu_single_ecc_error_incr, // LSU inc SB error counter + input el2_br_pkt_t i0_brp, // branch packet + input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index + input logic [ pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR + input logic [ pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag + input logic [ $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index - input logic lsu_imprecise_error_load_any, // LSU imprecise load bus error - input logic lsu_imprecise_error_store_any, // LSU imprecise store bus error - input logic [31:0] lsu_imprecise_error_addr_any, // LSU imprecise bus error address + input el2_lsu_error_pkt_t lsu_error_pkt_r, // LSU exception/error packet + input logic lsu_single_ecc_error_incr, // LSU inc SB error counter - input logic [31:0] exu_div_result, // final div result - input logic exu_div_wren, // Divide write enable to GPR + input logic lsu_imprecise_error_load_any, // LSU imprecise load bus error + input logic lsu_imprecise_error_store_any, // LSU imprecise store bus error + input logic [31:0] lsu_imprecise_error_addr_any, // LSU imprecise bus error address - input logic [31:0] exu_csr_rs1_x, // rs1 for csr instruction + input logic [31:0] exu_div_result, // final div result + input logic exu_div_wren, // Divide write enable to GPR - input logic [31:0] lsu_result_m, // load result - input logic [31:0] lsu_result_corr_r, // load result - corrected load data + input logic [31:0] exu_csr_rs1_x, // rs1 for csr instruction - input logic lsu_load_stall_any, // This is for blocking loads - input logic lsu_store_stall_any, // This is for blocking stores - input logic dma_dccm_stall_any, // stall any load/store at decode, pmu event - input logic dma_iccm_stall_any, // iccm stalled, pmu event + input logic [31:0] lsu_result_m, // load result + input logic [31:0] lsu_result_corr_r, // load result - corrected load data - input logic iccm_dma_sb_error, // ICCM DMA single bit error + input logic lsu_load_stall_any, // This is for blocking loads + input logic lsu_store_stall_any, // This is for blocking stores + input logic dma_dccm_stall_any, // stall any load/store at decode, pmu event + input logic dma_iccm_stall_any, // iccm stalled, pmu event - input logic exu_flush_final, // slot0 flush + input logic iccm_dma_sb_error, // ICCM DMA single bit error - input logic [31:1] exu_npc_r, // next PC + input logic exu_flush_final, // slot0 flush - input logic [31:0] exu_i0_result_x, // alu result x + input logic [31:1] exu_npc_r, // next PC + input logic [31:0] exu_i0_result_x, // alu result x - input logic ifu_i0_valid, // fetch valids to instruction buffer - input logic [31:0] ifu_i0_instr, // fetch inst's to instruction buffer - input logic [31:1] ifu_i0_pc, // pc's for instruction buffer - input logic ifu_i0_pc4, // indication of 4B or 2B for corresponding inst - input logic [31:1] exu_i0_pc_x, // pc's for e1 from the alu's - input logic mexintpend, // External interrupt pending - input logic timer_int, // Timer interrupt pending (from pin) - input logic soft_int, // Software interrupt pending (from pin) + input logic ifu_i0_valid, // fetch valids to instruction buffer + input logic [31:0] ifu_i0_instr, // fetch inst's to instruction buffer + input logic [31:1] ifu_i0_pc, // pc's for instruction buffer + input logic ifu_i0_pc4, // indication of 4B or 2B for corresponding inst + input logic [31:1] exu_i0_pc_x, // pc's for e1 from the alu's - input logic [7:0] pic_claimid, // PIC claimid - input logic [3:0] pic_pl, // PIC priv level - input logic mhwakeup, // High priority wakeup + input logic mexintpend, // External interrupt pending + input logic timer_int, // Timer interrupt pending (from pin) + input logic soft_int, // Software interrupt pending (from pin) - output logic [3:0] dec_tlu_meicurpl, // to PIC, Current priv level - output logic [3:0] dec_tlu_meipt, // to PIC + input logic [7:0] pic_claimid, // PIC claimid + input logic [3:0] pic_pl, // PIC priv level + input logic mhwakeup, // High priority wakeup - input logic [70:0] ifu_ic_debug_rd_data, // diagnostic icache read data - input logic ifu_ic_debug_rd_data_valid, // diagnostic icache read data valid - output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics + output logic [3:0] dec_tlu_meicurpl, // to PIC, Current priv level + output logic [3:0] dec_tlu_meipt, // to PIC + input logic [70:0] ifu_ic_debug_rd_data, // diagnostic icache read data + input logic ifu_ic_debug_rd_data_valid, // diagnostic icache read data valid + output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics -// Debug start - input logic dbg_halt_req, // DM requests a halt - input logic dbg_resume_req, // DM requests a resume - input logic ifu_miss_state_idle, // I-side miss buffer empty - output logic dec_tlu_dbg_halted, // Core is halted and ready for debug command - output logic dec_tlu_debug_mode, // Core is in debug mode - output logic dec_tlu_resume_ack, // Resume acknowledge - output logic dec_tlu_flush_noredir_r, // Tell fetch to idle on this flush - output logic dec_tlu_mpc_halted_only, // Core is halted only due to MPC - output logic dec_tlu_flush_leak_one_r, // single step - output logic dec_tlu_flush_err_r, // iside perr/ecc rfpc - output logic [31:2] dec_tlu_meihap, // Fast ext int base + // Debug start + input logic dbg_halt_req, // DM requests a halt + input logic dbg_resume_req, // DM requests a resume + input logic ifu_miss_state_idle, // I-side miss buffer empty - output logic dec_debug_wdata_rs1_d, // insert debug write data into rs1 at decode + output logic dec_tlu_dbg_halted, // Core is halted and ready for debug command + output logic dec_tlu_debug_mode, // Core is in debug mode + output logic dec_tlu_resume_ack, // Resume acknowledge + output logic dec_tlu_flush_noredir_r, // Tell fetch to idle on this flush + output logic dec_tlu_mpc_halted_only, // Core is halted only due to MPC + output logic dec_tlu_flush_leak_one_r, // single step + output logic dec_tlu_flush_err_r, // iside perr/ecc rfpc + output logic [31:2] dec_tlu_meihap, // Fast ext int base - output logic [31:0] dec_dbg_rddata, // debug command read data + output logic dec_debug_wdata_rs1_d, // insert debug write data into rs1 at decode - output logic dec_dbg_cmd_done, // abstract command is done - output logic dec_dbg_cmd_fail, // abstract command failed (illegal reg address) + output logic [31:0] dec_dbg_rddata, // debug command read data - output el2_trigger_pkt_t [3:0] trigger_pkt_any, // info needed by debug trigger blocks + output logic dec_dbg_cmd_done, // abstract command is done + output logic dec_dbg_cmd_fail, // abstract command failed (illegal reg address) - output logic dec_tlu_force_halt, // halt has been forced -// Debug end - // branch info from pipe0 for errors or counter updates - input logic [1:0] exu_i0_br_hist_r, // history - input logic exu_i0_br_error_r, // error - input logic exu_i0_br_start_error_r, // start error - input logic exu_i0_br_valid_r, // valid - input logic exu_i0_br_mp_r, // mispredict - input logic exu_i0_br_middle_r, // middle of bank + output el2_trigger_pkt_t [3:0] trigger_pkt_any, // info needed by debug trigger blocks - // branch info from pipe1 for errors or counter updates + output logic dec_tlu_force_halt, // halt has been forced + // Debug end + // branch info from pipe0 for errors or counter updates + input logic [1:0] exu_i0_br_hist_r, // history + input logic exu_i0_br_error_r, // error + input logic exu_i0_br_start_error_r, // start error + input logic exu_i0_br_valid_r, // valid + input logic exu_i0_br_mp_r, // mispredict + input logic exu_i0_br_middle_r, // middle of bank - input logic exu_i0_br_way_r, // way hit or repl + // branch info from pipe1 for errors or counter updates - output logic dec_i0_rs1_en_d, // Qualify GPR RS1 data - output logic dec_i0_rs2_en_d, // Qualify GPR RS2 data - output logic [31:0] gpr_i0_rs1_d, // gpr rs1 data - output logic [31:0] gpr_i0_rs2_d, // gpr rs2 data + input logic exu_i0_br_way_r, // way hit or repl - output logic [31:0] dec_i0_immed_d, // immediate data - output logic [12:1] dec_i0_br_immed_d, // br immediate data + output logic dec_i0_rs1_en_d, // Qualify GPR RS1 data + output logic dec_i0_rs2_en_d, // Qualify GPR RS2 data + output logic [31:0] gpr_i0_rs1_d, // gpr rs1 data + output logic [31:0] gpr_i0_rs2_d, // gpr rs2 data - output el2_alu_pkt_t i0_ap, // alu packet + output logic [31:0] dec_i0_immed_d, // immediate data + output logic [12:1] dec_i0_br_immed_d, // br immediate data - output logic dec_i0_alu_decode_d, // schedule on D-stage alu - output logic dec_i0_branch_d, // Branch in D-stage + output el2_alu_pkt_t i0_ap, // alu packet - output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's + output logic dec_i0_alu_decode_d, // schedule on D-stage alu + output logic dec_i0_branch_d, // Branch in D-stage - output logic [31:1] dec_i0_pc_d, // pc's at decode - output logic [3:0] dec_i0_rs1_bypass_en_d, // rs1 bypass enable - output logic [3:0] dec_i0_rs2_bypass_en_d, // rs2 bypass enable + output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's - output logic [31:0] dec_i0_result_r, // Result R-stage + output logic [31:1] dec_i0_pc_d, // pc's at decode + output logic [ 3:0] dec_i0_rs1_bypass_en_d, // rs1 bypass enable + output logic [ 3:0] dec_i0_rs2_bypass_en_d, // rs2 bypass enable - output el2_lsu_pkt_t lsu_p, // lsu packet - output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands - output el2_mul_pkt_t mul_p, // mul packet - output el2_div_pkt_t div_p, // div packet - output logic dec_div_cancel, // cancel divide operation + output logic [31:0] dec_i0_result_r, // Result R-stage - output logic [11:0] dec_lsu_offset_d, // 12b offset for load/store addresses + output el2_lsu_pkt_t lsu_p, // lsu packet + output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands + output el2_mul_pkt_t mul_p, // mul packet + output el2_div_pkt_t div_p, // div packet + output logic dec_div_cancel, // cancel divide operation - output logic dec_csr_ren_d, // CSR read enable - output logic [31:0] dec_csr_rddata_d, // CSR read data + output logic [11:0] dec_lsu_offset_d, // 12b offset for load/store addresses - output logic dec_tlu_flush_lower_r, // tlu flush due to late mp, exception, rfpc, or int - output logic dec_tlu_flush_lower_wb, - output logic [31:1] dec_tlu_flush_path_r, // tlu flush target - output logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state - output logic dec_tlu_fence_i_r, // flush is a fence_i rfnpc, flush icache + output logic dec_csr_ren_d, // CSR read enable + output logic [31:0] dec_csr_rddata_d, // CSR read data - output logic [31:1] pred_correct_npc_x, // npc if prediction is correct at e2 stage + output logic dec_tlu_flush_lower_r, // tlu flush due to late mp, exception, rfpc, or int + output logic dec_tlu_flush_lower_wb, + output logic [31:1] dec_tlu_flush_path_r, // tlu flush target + output logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state + output logic dec_tlu_fence_i_r, // flush is a fence_i rfnpc, flush icache - output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot 0 branch predictor update packet + output logic [31:1] pred_correct_npc_x, // npc if prediction is correct at e2 stage - output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc - output logic dec_tlu_perfcnt1, // toggles when slot0 perf counter 1 has an event inc - output logic dec_tlu_perfcnt2, // toggles when slot0 perf counter 2 has an event inc - output logic dec_tlu_perfcnt3, // toggles when slot0 perf counter 3 has an event inc + output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot 0 branch predictor update packet - output el2_predict_pkt_t dec_i0_predict_p_d, // prediction packet to alus - output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // DEC predict fghr - output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index - output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // DEC predict branch tag + output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc + output logic dec_tlu_perfcnt1, // toggles when slot0 perf counter 1 has an event inc + output logic dec_tlu_perfcnt2, // toggles when slot0 perf counter 2 has an event inc + output logic dec_tlu_perfcnt3, // toggles when slot0 perf counter 3 has an event inc - output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index + output el2_predict_pkt_t dec_i0_predict_p_d, // prediction packet to alus + output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // DEC predict fghr + output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index + output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // DEC predict branch tag - output logic dec_lsu_valid_raw_d, + output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index - output logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control + output logic dec_lsu_valid_raw_d, - output logic [1:0] dec_data_en, // clock-gate control logic - output logic [1:0] dec_ctl_en, + output logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control - input logic [15:0] ifu_i0_cinst, // 16b compressed instruction + output logic [1:0] dec_data_en, // clock-gate control logic + output logic [1:0] dec_ctl_en, - output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet + input logic [15:0] ifu_i0_cinst, // 16b compressed instruction - // feature disable from mfdc - output logic dec_tlu_external_ldfwd_disable, // disable external load forwarding - output logic dec_tlu_sideeffect_posted_disable, // disable posted stores to side-effect address - output logic dec_tlu_core_ecc_disable, // disable core ECC - output logic dec_tlu_bpred_disable, // disable branch prediction - output logic dec_tlu_wb_coalescing_disable, // disable writebuffer coalescing - output logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:16] + output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet - // clock gating overrides from mcgc - output logic dec_tlu_misc_clk_override, // override misc clock domain gating - output logic dec_tlu_ifu_clk_override, // override fetch clock domain gating - output logic dec_tlu_lsu_clk_override, // override load/store clock domain gating - output logic dec_tlu_bus_clk_override, // override bus clock domain gating - output logic dec_tlu_pic_clk_override, // override PIC clock domain gating - output logic dec_tlu_picio_clk_override, // override PICIO clock domain gating - output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating - output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating + // PMP signals + output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES], + output logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES], - output logic dec_tlu_i0_commit_cmt, // committed i0 instruction - input logic scan_mode // Flop scan mode control +`ifdef RV_USER_MODE - ); + // Privilege mode + output logic priv_mode, + output logic priv_mode_eff, + output logic priv_mode_ns, + // mseccfg CSR content for PMP + output el2_mseccfg_pkt_t mseccfg, - logic dec_tlu_dec_clk_override; // to and from dec blocks - logic clk_override; +`endif - logic dec_ib0_valid_d; + // feature disable from mfdc + output logic dec_tlu_external_ldfwd_disable, // disable external load forwarding + output logic dec_tlu_sideeffect_posted_disable, // disable posted stores to side-effect address + output logic dec_tlu_core_ecc_disable, // disable core ECC + output logic dec_tlu_bpred_disable, // disable branch prediction + output logic dec_tlu_wb_coalescing_disable, // disable writebuffer coalescing + output logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:16] - logic dec_pmu_instr_decoded; - logic dec_pmu_decode_stall; - logic dec_pmu_presync_stall; - logic dec_pmu_postsync_stall; + // clock gating overrides from mcgc + output logic dec_tlu_misc_clk_override, // override misc clock domain gating + output logic dec_tlu_ifu_clk_override, // override fetch clock domain gating + output logic dec_tlu_lsu_clk_override, // override load/store clock domain gating + output logic dec_tlu_bus_clk_override, // override bus clock domain gating + output logic dec_tlu_pic_clk_override, // override PIC clock domain gating + output logic dec_tlu_picio_clk_override, // override PICIO clock domain gating + output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating + output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating - logic dec_tlu_wr_pause_r; // CSR write to pause reg is at R. + output logic dec_tlu_i0_commit_cmt, // committed i0 instruction + input logic scan_mode // Flop scan mode control - logic [4:0] dec_i0_rs1_d; - logic [4:0] dec_i0_rs2_d; +); - logic [31:0] dec_i0_instr_d; - logic dec_tlu_trace_disable; - logic dec_tlu_pipelining_disable; + logic dec_tlu_dec_clk_override; // to and from dec blocks + logic clk_override; + logic dec_ib0_valid_d; - logic [4:0] dec_i0_waddr_r; - logic dec_i0_wen_r; - logic [31:0] dec_i0_wdata_r; - logic dec_csr_wen_r; // csr write enable at wb - logic [11:0] dec_csr_wraddr_r; // write address for csryes - logic [31:0] dec_csr_wrdata_r; // csr write data at wb + logic dec_pmu_instr_decoded; + logic dec_pmu_decode_stall; + logic dec_pmu_presync_stall; + logic dec_pmu_postsync_stall; - logic [11:0] dec_csr_rdaddr_d; // read address for csr - logic dec_csr_legal_d; // csr indicates legal operation + logic dec_tlu_wr_pause_r; // CSR write to pause reg is at R. - logic dec_csr_wen_unq_d; // valid csr with write - for csr legal - logic dec_csr_any_unq_d; // valid csr - for csr legal - logic dec_csr_stall_int_ff; // csr is mie/mstatus + logic [4:0] dec_i0_rs1_d; + logic [4:0] dec_i0_rs2_d; - el2_trap_pkt_t dec_tlu_packet_r; + logic [31:0] dec_i0_instr_d; - logic dec_i0_pc4_d; - logic dec_tlu_presync_d; - logic dec_tlu_postsync_d; - logic dec_tlu_debug_stall; + logic dec_tlu_trace_disable; + logic dec_tlu_pipelining_disable; - logic [31:0] dec_illegal_inst; - logic dec_i0_icaf_d; + logic [4:0] dec_i0_waddr_r; + logic dec_i0_wen_r; + logic [31:0] dec_i0_wdata_r; + logic dec_csr_wen_r; // csr write enable at wb + logic [11:0] dec_csr_rdaddr_r; // read address for csrs + logic [11:0] dec_csr_wraddr_r; // write address for csryes + logic [31:0] dec_csr_wrdata_r; // csr write data at wb - logic dec_i0_dbecc_d; - logic dec_i0_icaf_second_d; - logic [3:0] dec_i0_trigger_match_d; - logic dec_debug_fence_d; - logic dec_nonblock_load_wen; - logic [4:0] dec_nonblock_load_waddr; - logic dec_tlu_flush_pause_r; - el2_br_pkt_t dec_i0_brp; - logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index; - logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr; - logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag; - logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index; // Fully associt btb index + logic [11:0] dec_csr_rdaddr_d; // read address for csr + logic dec_csr_legal_d; // csr indicates legal operation - logic [31:1] dec_tlu_i0_pc_r; - logic dec_tlu_i0_kill_writeb_wb; - logic dec_tlu_i0_valid_r; + logic dec_csr_wen_unq_d; // valid csr with write - for csr legal + logic dec_csr_any_unq_d; // valid csr - for csr legal + logic dec_csr_stall_int_ff; // csr is mie/mstatus - logic dec_pause_state; + el2_trap_pkt_t dec_tlu_packet_r; - logic [1:0] dec_i0_icaf_type_d; // i0 instruction access fault type + logic dec_i0_pc4_d; + logic dec_tlu_presync_d; + logic dec_tlu_postsync_d; + logic dec_tlu_debug_stall; - logic dec_tlu_flush_extint; // Fast ext int started + logic [31:0] dec_illegal_inst; - logic [31:0] dec_i0_inst_wb; - logic [31:1] dec_i0_pc_wb; - logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1; - logic [4:0] dec_tlu_exc_cause_wb1; - logic [31:0] dec_tlu_mtval_wb1; - logic dec_tlu_i0_exc_valid_wb1; + logic dec_i0_icaf_d; - logic [4:0] div_waddr_wb; - logic dec_div_active; + logic dec_i0_dbecc_d; + logic dec_i0_icaf_second_d; + logic [3:0] dec_i0_trigger_match_d; + logic dec_debug_fence_d; + logic dec_nonblock_load_wen; + logic [4:0] dec_nonblock_load_waddr; + logic dec_tlu_flush_pause_r; + el2_br_pkt_t dec_i0_brp; + logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index; + logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr; + logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag; + logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index; // Fully associt btb index - logic dec_debug_valid_d; + logic [31:1] dec_tlu_i0_pc_r; + logic dec_tlu_i0_kill_writeb_wb; + logic dec_tlu_i0_valid_r; - assign clk_override = dec_tlu_dec_clk_override; + logic dec_pause_state; + logic [1:0] dec_i0_icaf_type_d; // i0 instruction access fault type - assign dec_dbg_rddata[31:0] = dec_i0_wdata_r[31:0]; + logic dec_tlu_flush_extint; // Fast ext int started + logic [31:0] dec_i0_inst_wb; + logic [31:1] dec_i0_pc_wb; + logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1; + logic [ 4:0] dec_tlu_exc_cause_wb1; + logic [31:0] dec_tlu_mtval_wb1; + logic dec_tlu_i0_exc_valid_wb1; - el2_dec_ib_ctl #(.pt(pt)) instbuff (.*); + logic [ 4:0] div_waddr_wb; + logic dec_div_active; + logic dec_debug_valid_d; - el2_dec_decode_ctl #(.pt(pt)) decode (.*); + assign clk_override = dec_tlu_dec_clk_override; - el2_dec_tlu_ctl #(.pt(pt)) tlu (.*); + assign dec_dbg_rddata[31:0] = dec_i0_wdata_r[31:0]; - el2_dec_gpr_ctl #(.pt(pt)) arf (.*, - // inputs - .raddr0(dec_i0_rs1_d[4:0]), - .raddr1(dec_i0_rs2_d[4:0]), + el2_dec_ib_ctl #(.pt(pt)) instbuff (.*); - .wen0(dec_i0_wen_r), .waddr0(dec_i0_waddr_r[4:0]), .wd0(dec_i0_wdata_r[31:0]), - .wen1(dec_nonblock_load_wen), .waddr1(dec_nonblock_load_waddr[4:0]), .wd1(lsu_nonblock_load_data[31:0]), - .wen2(exu_div_wren), .waddr2(div_waddr_wb), .wd2(exu_div_result[31:0]), - // outputs - .rd0(gpr_i0_rs1_d[31:0]), .rd1(gpr_i0_rs2_d[31:0]) - ); + el2_dec_decode_ctl #(.pt(pt)) decode (.*); -// Trigger + el2_dec_tlu_ctl #(.pt(pt)) tlu (.*); - el2_dec_trigger #(.pt(pt)) dec_trigger (.*); + el2_dec_gpr_ctl #( + .pt(pt) + ) arf ( + .*, + // inputs + .raddr0(dec_i0_rs1_d[4:0]), + .raddr1(dec_i0_rs2_d[4:0]), + .wen0(dec_i0_wen_r), + .waddr0(dec_i0_waddr_r[4:0]), + .wd0(dec_i0_wdata_r[31:0]), + .wen1(dec_nonblock_load_wen), + .waddr1(dec_nonblock_load_waddr[4:0]), + .wd1(lsu_nonblock_load_data[31:0]), + .wen2(exu_div_wren), + .waddr2(div_waddr_wb), + .wd2(exu_div_result[31:0]), + // outputs + .rd0(gpr_i0_rs1_d[31:0]), + .rd1(gpr_i0_rs2_d[31:0]) + ); -// trace - assign trace_rv_trace_pkt.trace_rv_i_insn_ip = dec_i0_inst_wb[31:0]; - assign trace_rv_trace_pkt.trace_rv_i_address_ip = { dec_i0_pc_wb[31:1], 1'b0}; - assign trace_rv_trace_pkt.trace_rv_i_valid_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_valid_wb1 | dec_tlu_i0_exc_valid_wb1; - assign trace_rv_trace_pkt.trace_rv_i_exception_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_exc_valid_wb1; - assign trace_rv_trace_pkt.trace_rv_i_ecause_ip = dec_tlu_exc_cause_wb1[4:0]; // replicate across ports - assign trace_rv_trace_pkt.trace_rv_i_interrupt_ip = dec_tlu_int_valid_wb1; - assign trace_rv_trace_pkt.trace_rv_i_tval_ip = dec_tlu_mtval_wb1[31:0]; // replicate across ports + // Trigger + el2_dec_trigger #(.pt(pt)) dec_trigger (.*); -// end trace -endmodule // el2_dec + // trace + assign trace_rv_trace_pkt.trace_rv_i_insn_ip = dec_i0_inst_wb[31:0]; + assign trace_rv_trace_pkt.trace_rv_i_address_ip = {dec_i0_pc_wb[31:1], 1'b0}; + + assign trace_rv_trace_pkt.trace_rv_i_valid_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_valid_wb1 | dec_tlu_i0_exc_valid_wb1; + assign trace_rv_trace_pkt.trace_rv_i_exception_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_exc_valid_wb1; + assign trace_rv_trace_pkt.trace_rv_i_ecause_ip = dec_tlu_exc_cause_wb1[4:0]; // replicate across ports + assign trace_rv_trace_pkt.trace_rv_i_interrupt_ip = dec_tlu_int_valid_wb1; + assign trace_rv_trace_pkt.trace_rv_i_tval_ip = dec_tlu_mtval_wb1[31:0]; // replicate across ports + + + + // end trace + + +endmodule // el2_dec diff --git a/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv b/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv index de2694e7c..0afac252a 100644 --- a/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv @@ -160,6 +160,7 @@ import el2_pkg::*; output logic dec_csr_any_unq_d, // valid csr - for csr legal output logic [11:0] dec_csr_rdaddr_d, // read address for csr output logic dec_csr_wen_r, // csr write enable at r + output logic [11:0] dec_csr_rdaddr_r, // read address for csr output logic [11:0] dec_csr_wraddr_r, // write address for csr output logic [31:0] dec_csr_wrdata_r, // csr write data at r output logic dec_csr_stall_int_ff, // csr is mie/mstatus @@ -920,8 +921,9 @@ end : cam_array assign dec_csr_any_unq_d = any_csr_d & i0_valid_d; - assign dec_csr_rdaddr_d[11:0] = {12{dec_csr_any_unq_d}} & i0[31:20]; - assign dec_csr_wraddr_r[11:0] = {12{r_d.csrwen & r_d.i0valid}} & r_d.csrwaddr[11:0]; + assign dec_csr_rdaddr_d[11:0] = {12{dec_csr_any_unq_d}} & i0[31:20]; + assign dec_csr_rdaddr_r[11:0] = {12{~r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0]; + assign dec_csr_wraddr_r[11:0] = {12{r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0]; // make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb @@ -929,7 +931,7 @@ end : cam_array assign dec_csr_wen_r = r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_r; // If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write. - assign dec_csr_stall_int_ff = ((r_d.csrwaddr[11:0] == 12'h300) | (r_d.csrwaddr[11:0] == 12'h304)) & r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_wb; + assign dec_csr_stall_int_ff = ((r_d.csraddr[11:0] == 12'h300) | (r_d.csraddr[11:0] == 12'h304)) & r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_wb; rvdff #(5) csrmiscff (.*, @@ -1307,9 +1309,9 @@ end : cam_array assign d_d.i0div = i0_dp.div & i0_legal_decode_d; - assign d_d.csrwen = dec_csr_wen_unq_d & i0_legal_decode_d; - assign d_d.csrwonly = i0_csr_write_only_d & dec_i0_decode_d; - assign d_d.csrwaddr[11:0] = (d_d.csrwen) ? i0[31:20] : '0; // csr write address for rd==0 case + assign d_d.csrwen = dec_csr_wen_unq_d & i0_legal_decode_d; + assign d_d.csrwonly = i0_csr_write_only_d & dec_i0_decode_d; + assign d_d.csraddr[11:0] = i0[31:20]; // csr read/write address rvdff #(3) i0cgff (.*, .clk(active_clk), .din(i0_pipe_en[3:1]), .dout(i0_pipe_en[2:0])); @@ -1487,156 +1489,153 @@ end : cam_array endmodule // el2_dec_decode_ctl - - - - -// file "decode" is human readable file that has all of the instruction decodes defined and is part of git repo -// modify this file as needed - -// to generate all the equations below from "decode" except legal equation: - -// 1) coredecode -in decode > coredecode.e - -// 2) espresso -Dso -oeqntott coredecode.e | addassign -pre out. > equations - -// to generate the legal (32b instruction is legal) equation below: - -// 1) coredecode -in decode -legal > legal.e - -// 2) espresso -Dso -oeqntott legal.e | addassign -pre out. > legal_equation +// file "decode" is human readable file that has all of the instruction decodes +// defined and is part of git repo. Modify this file as needed. +// +// The tools needed are "coredecode", "addasign" and "espresso". The first two +// can be found in this repo under /tools. Espresso can be found in another +// repo (https://github.com/chipsalliance/espresso). +// IMPORTANT: use Espresso v2.4 (git tag v2.4) +// +// To generate instruction decoding equations do: +// 1) coredecode -in decode > coredecode.e +// 2) espresso -Dso -oeqntott < coredecode.e | addassign -pre out. > equations +// 3) copy-paste assignments from the file "equations" and replace ones below. +// +// To generate instruction legality check equation do: +// 1) coredecode -in decode -legal > legal.e +// 2) espresso -Dso -oeqntott < legal.e | addassign -pre out. > legal +// 3) copy-paste assignment from the file "legal" and replace the one below. module el2_dec_dec_ctl -import el2_pkg::*; - ( - input logic [31:0] inst, - - output el2_dec_pkt_t out - ); - - logic [31:0] i; + import el2_pkg::*; +( + input logic [31:0] inst, + output el2_dec_pkt_t out +); + logic [31:0] i; - assign i[31:0] = inst[31:0]; + assign i[31:0] = inst[31:0]; -assign out.alu = (i[30]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[5]&i[4]) | (i[30] + assign out.alu = (i[30]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[5]&i[4]) | (i[30] &!i[27]&!i[24]&i[4]) | (!i[30]&!i[25]&i[13]&i[12]) | (!i[29]&!i[27] &!i[5]&i[4]) | (i[27]&i[25]&i[14]&i[4]) | (!i[29]&!i[25]&!i[13]&!i[12] &i[4]) | (i[29]&i[27]&!i[14]&i[12]&i[4]) | (!i[27]&i[14]&!i[5]&i[4]) | ( i[30]&!i[29]&!i[13]&i[4]) | (!i[27]&!i[25]&i[5]&i[4]) | (i[13]&!i[5] - &i[4]) | (i[2]) | (i[6]) | (!i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21] - &i[20]&!i[5]&i[4]) | (!i[12]&!i[5]&i[4]); + &i[4]) | (i[6]) | (!i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]&i[20]&!i[5] + &i[4]) | (i[2]) | (!i[12]&!i[5]&i[4]); -assign out.rs1 = (!i[13]&i[11]&!i[2]) | (!i[13]&i[10]&!i[2]) | (i[19]&i[13]&!i[2]) | ( + assign out.rs1 = (!i[13]&i[11]&!i[2]) | (!i[13]&i[10]&!i[2]) | (i[19]&i[13]&!i[2]) | ( !i[13]&i[9]&!i[2]) | (i[18]&i[13]&!i[2]) | (!i[13]&i[8]&!i[2]) | ( i[17]&i[13]&!i[2]) | (!i[13]&i[7]&!i[2]) | (i[16]&i[13]&!i[2]) | ( i[15]&i[13]&!i[2]) | (!i[4]&!i[2]) | (!i[14]&!i[13]&i[6]&!i[3]) | ( !i[6]&!i[2]); -assign out.rs2 = (i[5]&!i[4]&!i[2]) | (!i[6]&i[5]&!i[2]); + assign out.rs2 = (i[5] & !i[4] & !i[2]) | (!i[6] & i[5] & !i[2]); -assign out.imm12 = (!i[4]&!i[3]&i[2]) | (i[13]&!i[5]&i[4]&!i[2]) | (!i[13]&!i[12] + assign out.imm12 = (!i[4]&!i[3]&i[2]) | (i[13]&!i[5]&i[4]&!i[2]) | (!i[13]&!i[12] &i[6]&i[4]) | (!i[12]&!i[5]&i[4]&!i[2]); -assign out.rd = (!i[5]&!i[2]) | (i[5]&i[2]) | (i[4]); + assign out.rd = (!i[5] & !i[2]) | (i[5] & i[2]) | (i[4]); -assign out.shimm5 = (!i[29]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[13]&i[12] + assign out.shimm5 = (!i[29]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[13]&i[12] &!i[5]&i[4]&!i[2]) | (i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); -assign out.imm20 = (i[5]&i[3]) | (i[4]&i[2]); + assign out.imm20 = (i[5] & i[3]) | (i[4] & i[2]); -assign out.pc = (!i[5]&!i[3]&i[2]) | (i[5]&i[3]); + assign out.pc = (!i[5] & !i[3] & i[2]) | (i[5] & i[3]); -assign out.load = (!i[5]&!i[4]&!i[2]); + assign out.load = (!i[5] & !i[4] & !i[2]); -assign out.store = (!i[6]&i[5]&!i[4]); + assign out.store = (!i[6] & i[5] & !i[4]); -assign out.lsu = (!i[6]&!i[4]&!i[2]); + assign out.lsu = (!i[6] & !i[4] & !i[2]); -assign out.add = (!i[14]&!i[13]&!i[12]&!i[5]&i[4]) | (!i[5]&!i[3]&i[2]) | (!i[30] + assign out.add = (!i[14]&!i[13]&!i[12]&!i[5]&i[4]) | (!i[5]&!i[3]&i[2]) | (!i[30] &!i[25]&!i[14]&!i[13]&!i[12]&!i[6]&i[4]&!i[2]); -assign out.sub = (i[30]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[29]&!i[25]&!i[14] + assign out.sub = (i[30]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[29]&!i[25]&!i[14] &i[13]&!i[6]&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]) | ( !i[14]&i[13]&!i[5]&i[4]&!i[2]) | (i[6]&!i[4]&!i[2]); -assign out.land = (!i[27]&!i[25]&i[14]&i[13]&i[12]&!i[6]&!i[2]) | (i[14]&i[13]&i[12] + assign out.land = (!i[27]&!i[25]&i[14]&i[13]&i[12]&!i[6]&!i[2]) | (i[14]&i[13]&i[12] &!i[5]&!i[2]); -assign out.lor = (!i[6]&i[3]) | (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) | ( + assign out.lor = (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) | (!i[6]&i[3]) | ( i[5]&i[4]&i[2]) | (!i[13]&!i[12]&i[6]&i[4]) | (i[14]&i[13]&!i[12] &!i[5]&!i[2]); -assign out.lxor = (!i[29]&!i[27]&!i[25]&i[14]&!i[13]&!i[12]&i[4]&!i[2]) | (i[14] + assign out.lxor = (!i[29]&!i[27]&!i[25]&i[14]&!i[13]&!i[12]&i[4]&!i[2]) | (i[14] &!i[13]&!i[12]&!i[5]&i[4]&!i[2]); -assign out.sll = (!i[29]&!i[27]&!i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.sll = (!i[29] & !i[27] & !i[25] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]); -assign out.sra = (i[30]&!i[29]&!i[27]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.sra = (i[30] & !i[29] & !i[27] & !i[13] & i[12] & !i[6] & i[4] & !i[2]); -assign out.srl = (!i[30]&!i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.srl = (!i[30] & !i[27] & !i[25] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]); -assign out.slt = (!i[29]&!i[25]&!i[14]&i[13]&!i[6]&i[4]&!i[2]) | (!i[14]&i[13]&!i[5] + assign out.slt = (!i[29]&!i[25]&!i[14]&i[13]&!i[6]&i[4]&!i[2]) | (!i[14]&i[13]&!i[5] &i[4]&!i[2]); -assign out.unsign = (!i[14]&i[13]&i[12]&!i[5]&!i[2]) | (i[13]&i[6]&!i[4]&!i[2]) | ( + assign out.unsign = (!i[14]&i[13]&i[12]&!i[5]&!i[2]) | (i[13]&i[6]&!i[4]&!i[2]) | ( i[14]&!i[5]&!i[4]) | (!i[25]&!i[14]&i[13]&i[12]&!i[6]&!i[2]) | ( i[25]&i[14]&i[12]&!i[6]&i[5]&!i[2]); -assign out.condbr = (i[6]&!i[4]&!i[2]); + assign out.condbr = (i[6] & !i[4] & !i[2]); -assign out.beq = (!i[14]&!i[12]&i[6]&!i[4]&!i[2]); + assign out.beq = (!i[14] & !i[12] & i[6] & !i[4] & !i[2]); -assign out.bne = (!i[14]&i[12]&i[6]&!i[4]&!i[2]); + assign out.bne = (!i[14] & i[12] & i[6] & !i[4] & !i[2]); -assign out.bge = (i[14]&i[12]&i[5]&!i[4]&!i[2]); + assign out.bge = (i[14] & i[12] & i[5] & !i[4] & !i[2]); -assign out.blt = (i[14]&!i[12]&i[5]&!i[4]&!i[2]); + assign out.blt = (i[14] & !i[12] & i[5] & !i[4] & !i[2]); -assign out.jal = (i[6]&i[2]); + assign out.jal = (i[6] & i[2]); -assign out.by = (!i[13]&!i[12]&!i[6]&!i[4]&!i[2]); + assign out.by = (!i[13] & !i[12] & !i[6] & !i[4] & !i[2]); -assign out.half = (i[12]&!i[6]&!i[4]&!i[2]); + assign out.half = (i[12] & !i[6] & !i[4] & !i[2]); -assign out.word = (i[13]&!i[6]&!i[4]); + assign out.word = (i[13] & !i[6] & !i[4]); -assign out.csr_read = (i[13]&i[6]&i[4]) | (i[7]&i[6]&i[4]) | (i[8]&i[6]&i[4]) | ( + assign out.csr_read = (i[13]&i[6]&i[4]) | (i[7]&i[6]&i[4]) | (i[8]&i[6]&i[4]) | ( i[9]&i[6]&i[4]) | (i[10]&i[6]&i[4]) | (i[11]&i[6]&i[4]); -assign out.csr_clr = (i[15]&i[13]&i[12]&i[6]&i[4]) | (i[16]&i[13]&i[12]&i[6]&i[4]) | ( + assign out.csr_clr = (i[15]&i[13]&i[12]&i[6]&i[4]) | (i[16]&i[13]&i[12]&i[6]&i[4]) | ( i[17]&i[13]&i[12]&i[6]&i[4]) | (i[18]&i[13]&i[12]&i[6]&i[4]) | ( i[19]&i[13]&i[12]&i[6]&i[4]); -assign out.csr_set = (i[15]&!i[12]&i[6]&i[4]) | (i[16]&!i[12]&i[6]&i[4]) | (i[17] + assign out.csr_set = (i[15]&!i[12]&i[6]&i[4]) | (i[16]&!i[12]&i[6]&i[4]) | (i[17] &!i[12]&i[6]&i[4]) | (i[18]&!i[12]&i[6]&i[4]) | (i[19]&!i[12]&i[6] &i[4]); -assign out.csr_write = (!i[13]&i[12]&i[6]&i[4]); + assign out.csr_write = (!i[13] & i[12] & i[6] & i[4]); -assign out.csr_imm = (i[14]&!i[13]&i[6]&i[4]) | (i[15]&i[14]&i[6]&i[4]) | (i[16] + assign out.csr_imm = (i[14]&!i[13]&i[6]&i[4]) | (i[15]&i[14]&i[6]&i[4]) | (i[16] &i[14]&i[6]&i[4]) | (i[17]&i[14]&i[6]&i[4]) | (i[18]&i[14]&i[6]&i[4]) | ( i[19]&i[14]&i[6]&i[4]); -assign out.presync = (!i[5]&i[3]) | (!i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&i[4]) | ( + assign out.presync = (!i[5]&i[3]) | (!i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&i[4]) | ( !i[13]&i[9]&i[6]&i[4]) | (!i[13]&i[10]&i[6]&i[4]) | (!i[13]&i[11] &i[6]&i[4]) | (i[15]&i[13]&i[6]&i[4]) | (i[16]&i[13]&i[6]&i[4]) | ( i[17]&i[13]&i[6]&i[4]) | (i[18]&i[13]&i[6]&i[4]) | (i[19]&i[13]&i[6] &i[4]); -assign out.postsync = (i[12]&!i[5]&i[3]) | (!i[22]&!i[13]&!i[12]&i[6]&i[4]) | ( + assign out.postsync = (!i[22]&!i[13]&!i[12]&i[6]&i[4]) | (i[12]&!i[5]&i[3]) | ( !i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&i[4]) | (!i[13]&i[9]&i[6] &i[4]) | (!i[13]&i[10]&i[6]&i[4]) | (!i[13]&i[11]&i[6]&i[4]) | ( i[15]&i[13]&i[6]&i[4]) | (i[16]&i[13]&i[6]&i[4]) | (i[17]&i[13]&i[6] &i[4]) | (i[18]&i[13]&i[6]&i[4]) | (i[19]&i[13]&i[6]&i[4]); -assign out.ebreak = (!i[22]&i[20]&!i[13]&!i[12]&i[6]&i[4]); + assign out.ebreak = (!i[22] & i[20] & !i[13] & !i[12] & i[6] & i[4]); -assign out.ecall = (!i[21]&!i[20]&!i[13]&!i[12]&i[6]&i[4]); + assign out.ecall = (!i[21] & !i[20] & !i[13] & !i[12] & i[6] & i[4]); -assign out.mret = (i[29]&!i[13]&!i[12]&i[6]&i[4]); + assign out.mret = (i[29] & !i[13] & !i[12] & i[6] & i[4]); -assign out.mul = (i[29]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30] + assign out.mul = (i[29]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30] &i[27]&i[13]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[23]&!i[20] &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[21]&i[20] &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&i[24]&i[21] @@ -1648,48 +1647,48 @@ assign out.mul = (i[29]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[ &i[4]&!i[2]) | (i[25]&!i[14]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27] &i[14]&!i[6]&i[5]&!i[2]); -assign out.rs1_sign = (!i[27]&i[25]&!i[14]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | ( + assign out.rs1_sign = (!i[27]&i[25]&!i[14]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | ( !i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); -assign out.rs2_sign = (!i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.rs2_sign = (!i[27] & i[25] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]); -assign out.low = (i[25]&!i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); + assign out.low = (i[25] & !i[14] & !i[13] & !i[12] & i[5] & i[4] & !i[2]); -assign out.div = (!i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]); + assign out.div = (!i[27] & i[25] & i[14] & !i[6] & i[5] & !i[2]); -assign out.rem = (!i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[2]); + assign out.rem = (!i[27] & i[25] & i[14] & i[13] & !i[6] & i[5] & !i[2]); -assign out.fence = (!i[5]&i[3]); + assign out.fence = (!i[5] & i[3]); -assign out.fence_i = (i[12]&!i[5]&i[3]); + assign out.fence_i = (i[12] & !i[5] & i[3]); -assign out.clz = (i[29]&!i[27]&!i[24]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5] + assign out.clz = (i[29]&!i[27]&!i[24]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5] &i[4]&!i[2]); -assign out.ctz = (i[29]&!i[27]&!i[24]&!i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4] + assign out.ctz = (i[29]&!i[27]&!i[24]&!i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4] &!i[2]); -assign out.cpop = (i[29]&!i[27]&!i[24]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + assign out.cpop = (i[29]&!i[27]&!i[24]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); -assign out.sext_b = (i[29]&!i[27]&i[22]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + assign out.sext_b = (i[29]&!i[27]&i[22]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); -assign out.sext_h = (i[29]&!i[27]&i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + assign out.sext_h = (i[29]&!i[27]&i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); -assign out.min = (i[27]&i[25]&i[14]&!i[13]&!i[6]&i[5]&!i[2]); + assign out.min = (i[27] & i[25] & i[14] & !i[13] & !i[6] & i[5] & !i[2]); -assign out.max = (i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[2]); + assign out.max = (i[27] & i[25] & i[14] & i[13] & !i[6] & i[5] & !i[2]); -assign out.pack = (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); + assign out.pack = (!i[30] & !i[29] & i[27] & !i[25] & !i[13] & !i[12] & i[5] & i[4] & !i[2]); -assign out.packu = (i[30]&i[27]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); + assign out.packu = (i[30] & i[27] & !i[13] & !i[12] & i[5] & i[4] & !i[2]); -assign out.packh = (!i[30]&i[27]&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]); + assign out.packh = (!i[30] & i[27] & !i[25] & i[13] & i[12] & !i[6] & i[5] & !i[2]); -assign out.rol = (i[29]&!i[27]&!i[14]&i[12]&!i[6]&i[5]&i[4]&!i[2]); + assign out.rol = (i[29] & !i[27] & !i[14] & i[12] & !i[6] & i[5] & i[4] & !i[2]); -assign out.ror = (i[29]&!i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.ror = (i[29] & !i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]); -assign out.zbb = (!i[30]&!i[29]&i[27]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[13] + assign out.zbb = (!i[30]&!i[29]&i[27]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[13] &!i[12]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&!i[24]&!i[13]&i[12]&!i[5] &i[4]&!i[2]) | (i[29]&!i[27]&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | ( i[30]&!i[27]&i[14]&!i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13] @@ -1698,92 +1697,92 @@ assign out.zbb = (!i[30]&!i[29]&i[27]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[13] &i[4]&!i[2]) | (i[30]&i[29]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14] &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]); -assign out.bset = (!i[30]&i[29]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.bset = (!i[30] & i[29] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]); -assign out.bclr = (i[30]&!i[29]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.bclr = (i[30] & !i[29] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]); -assign out.binv = (i[30]&i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.binv = (i[30] & i[29] & i[27] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]); -assign out.bext = (i[30]&!i[29]&i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.bext = (i[30] & !i[29] & i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]); -assign out.zbs = (i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]) | (i[30]&!i[29] + assign out.zbs = (i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]) | (i[30]&!i[29] &i[27]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); -assign out.bcompress = (!i[30]&!i[29]&i[27]&!i[25]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + assign out.bcompress = (!i[30]&!i[29]&i[27]&!i[25]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); -assign out.bdecompress = (i[30]&i[27]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + assign out.bdecompress = (i[30] & i[27] & i[13] & !i[12] & !i[6] & i[5] & i[4] & !i[2]); -assign out.zbe = (i[30]&i[27]&i[14]&i[13]&!i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&i[27] + assign out.zbe = (i[30]&i[27]&i[14]&i[13]&!i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&i[27] &!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25] &!i[12]&!i[6]&i[5]&i[4]&!i[2]); -assign out.clmul = (i[27]&i[25]&!i[14]&!i[13]&!i[6]&i[5]&i[4]&!i[2]); + assign out.clmul = (i[27] & i[25] & !i[14] & !i[13] & !i[6] & i[5] & i[4] & !i[2]); -assign out.clmulh = (i[27]&!i[14]&i[13]&i[12]&!i[6]&i[5]&!i[2]); + assign out.clmulh = (i[27] & !i[14] & i[13] & i[12] & !i[6] & i[5] & !i[2]); -assign out.clmulr = (i[27]&i[25]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + assign out.clmulr = (i[27] & i[25] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]); -assign out.zbc = (i[27]&i[25]&!i[14]&!i[6]&i[5]&i[4]&!i[2]); + assign out.zbc = (i[27] & i[25] & !i[14] & !i[6] & i[5] & i[4] & !i[2]); -assign out.grev = (i[30]&i[29]&i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.grev = (i[30] & i[29] & i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]); -assign out.gorc = (!i[30]&i[29]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.gorc = (!i[30] & i[29] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]); -assign out.shfl = (!i[30]&!i[29]&i[27]&!i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.shfl = (!i[30]&!i[29]&i[27]&!i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); -assign out.unshfl = (!i[30]&!i[29]&i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + assign out.unshfl = (!i[30]&!i[29]&i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); -assign out.xperm_n = (i[29]&i[27]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + assign out.xperm_n = (i[29] & i[27] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]); -assign out.xperm_b = (i[29]&i[27]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); + assign out.xperm_b = (i[29] & i[27] & !i[13] & !i[12] & i[5] & i[4] & !i[2]); -assign out.xperm_h = (i[29]&i[27]&i[14]&i[13]&!i[6]&i[5]&!i[2]); + assign out.xperm_h = (i[29] & i[27] & i[14] & i[13] & !i[6] & i[5] & !i[2]); -assign out.zbp = (i[30]&!i[27]&!i[14]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[30]&i[27] + assign out.zbp = (i[30]&!i[27]&!i[14]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[30]&i[27] &!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13]&!i[6] &i[5]&i[4]&!i[2]) | (i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | ( i[30]&i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[12]&!i[6] &i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6] &i[4]&!i[2]) | (i[29]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); -assign out.crc32_b = (i[29]&!i[27]&i[24]&!i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12] + assign out.crc32_b = (i[29]&!i[27]&i[24]&!i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12] &!i[5]&i[4]&!i[2]); -assign out.crc32_h = (i[29]&!i[27]&i[24]&!i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4] + assign out.crc32_h = (i[29]&!i[27]&i[24]&!i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4] &!i[2]); -assign out.crc32_w = (i[29]&!i[27]&i[24]&!i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4] + assign out.crc32_w = (i[29]&!i[27]&i[24]&!i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4] &!i[2]); -assign out.crc32c_b = (i[29]&!i[27]&i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5] + assign out.crc32c_b = (i[29]&!i[27]&i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5] &i[4]&!i[2]); -assign out.crc32c_h = (i[29]&!i[27]&i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + assign out.crc32c_h = (i[29]&!i[27]&i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); -assign out.crc32c_w = (i[29]&!i[27]&i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + assign out.crc32c_w = (i[29]&!i[27]&i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); -assign out.zbr = (i[29]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + assign out.zbr = (i[29] & !i[27] & i[24] & !i[14] & !i[13] & i[12] & !i[5] & i[4] & !i[2]); -assign out.bfp = (i[30]&i[27]&i[13]&i[12]&!i[6]&i[5]&!i[2]); + assign out.bfp = (i[30] & i[27] & i[13] & i[12] & !i[6] & i[5] & !i[2]); -assign out.zbf = (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | ( + assign out.zbf = (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | ( i[27]&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]); -assign out.sh1add = (i[29]&!i[27]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + assign out.sh1add = (i[29] & !i[27] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]); -assign out.sh2add = (i[29]&!i[27]&i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); + assign out.sh2add = (i[29] & !i[27] & i[14] & !i[13] & !i[12] & i[5] & i[4] & !i[2]); -assign out.sh3add = (i[29]&!i[27]&i[14]&i[13]&!i[6]&i[5]&!i[2]); + assign out.sh3add = (i[29] & !i[27] & i[14] & i[13] & !i[6] & i[5] & !i[2]); -assign out.zba = (i[29]&!i[27]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + assign out.zba = (i[29] & !i[27] & !i[12] & !i[6] & i[5] & i[4] & !i[2]); -assign out.pm_alu = (i[28]&i[20]&!i[13]&!i[12]&i[4]) | (!i[30]&!i[29]&!i[27]&!i[25] + assign out.pm_alu = (i[28]&i[20]&!i[13]&!i[12]&i[4]) | (!i[30]&!i[29]&!i[27]&!i[25] &!i[6]&i[4]) | (!i[29]&!i[27]&!i[25]&!i[13]&i[12]&!i[6]&i[4]) | ( !i[29]&!i[27]&!i[25]&!i[14]&!i[6]&i[4]) | (i[13]&!i[5]&i[4]) | (i[4] &i[2]) | (!i[12]&!i[5]&i[4]); -assign out.legal = (!i[31]&!i[30]&i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23] + assign out.legal = (!i[31]&!i[30]&i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23] &!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11] &!i[10]&!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | ( !i[31]&!i[30]&!i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&i[22] @@ -1816,20 +1815,14 @@ assign out.legal = (!i[31]&!i[30]&i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23] &i[0]) | (!i[14]&!i[13]&!i[12]&i[6]&i[5]&!i[4]&!i[3]&i[1]&i[0]) | ( i[14]&i[6]&i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&!i[13]&i[5] &!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[12]&!i[6]&!i[5]&i[4]&!i[3]&i[1] - &i[0]) | (!i[13]&i[12]&i[6]&i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31] - &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21] - &!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&!i[11]&!i[10] - &!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[31] - &!i[30]&!i[29]&!i[28]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13] - &!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&i[3]&i[2] - &i[1]&i[0]) | (i[13]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31] - &!i[30]&!i[28]&!i[26]&!i[25]&i[14]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | ( - i[6]&i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[14]&!i[12]&!i[6]&!i[4] - &!i[3]&!i[2]&i[1]&i[0]) | (!i[13]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1] - &i[0]) | (i[13]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[6]&i[4]&!i[3] - &i[2]&i[1]&i[0]); - - - - -endmodule // el2_dec_dec_ctl + &i[0]) | (!i[13]&i[12]&i[6]&i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[13]&i[6] + &i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&!i[29]&!i[28]&!i[14] + &!i[13]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28] + &!i[26]&!i[25]&i[14]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[14] + &!i[13]&i[12]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (i[6]&i[5] + &!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[14]&!i[12]&!i[6]&!i[4]&!i[3]&!i[2] + &i[1]&i[0]) | (!i[13]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | ( + i[13]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[6]&i[4]&!i[3]&i[2]&i[1] + &i[0]); + +endmodule // el2_dec_dec_ctl diff --git a/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv b/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv new file mode 100644 index 000000000..1dc734d3a --- /dev/null +++ b/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2023 Antmicro +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +//******************************************************************************** +// el2_dec_pmp_ctl.sv +// +// +// Function: Physical Memory Protection CSRs +// Comments: +// +//******************************************************************************** + +module el2_dec_pmp_ctl + import el2_pkg::*; +#( +`include "el2_param.vh" + ) + ( + input logic clk, + input logic free_l2clk, + input logic csr_wr_clk, + input logic rst_l, + input logic dec_csr_wen_r_mod, // csr write enable at wb + input logic [11:0] dec_csr_wraddr_r, // write address for csr + input logic [31:0] dec_csr_wrdata_r, // csr write data at wb + input logic [11:0] dec_csr_rdaddr_d, // read address for csr + + input logic csr_pmpcfg, + input logic csr_pmpaddr0, + input logic csr_pmpaddr16, + input logic csr_pmpaddr32, + input logic csr_pmpaddr48, + + input logic dec_pause_state, // Paused + input logic dec_tlu_pmu_fw_halted, // pmu/fw halted + input logic internal_dbg_halt_timers, // debug halted + +`ifdef RV_SMEPMP + input el2_mseccfg_pkt_t mseccfg, +`endif + + output logic [31:0] dec_pmp_rddata_d, // pmp CSR read data + output logic dec_pmp_read_d, // pmp CSR address match + + output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES], + output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES], + + input logic scan_mode + ); + + logic wr_pmpcfg_r; + logic [3:0] wr_pmpcfg_group; + + logic wr_pmpaddr0_sel; + logic wr_pmpaddr16_sel; + logic wr_pmpaddr32_sel; + logic wr_pmpaddr48_sel; + logic wr_pmpaddr_r; + logic [1:0] wr_pmpaddr_quarter; + logic [5:0] wr_pmpaddr_address; + + logic [3:0] pmp_quarter_rdaddr; + logic [31:0] pmp_pmpcfg_rddata; + + // ---------------------------------------------------------------------- + + logic [pt.PMP_ENTRIES-1:0] entry_lock_eff; // Effective entry lock + for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_pmpcfg_lock +`ifdef RV_SMEPMP + // Smepmp allow modifying locked entries when mseccfg.RLB is set + assign entry_lock_eff[r] = pmp_pmpcfg[r].lock & ~mseccfg.RLB; +`else + assign entry_lock_eff[r] = pmp_pmpcfg[r].lock; +`endif + end + + // ---------------------------------------------------------------------- + // PMPCFGx (RW) + // [31:24] : PMP entry (x*4 + 3) configuration + // [23:16] : PMP entry (x*4 + 2) configuration + // [15:8] : PMP entry (x*4 + 1) configuration + // [7:0] : PMP entry (x*4 + 0) configuration + + localparam PMPCFG = 12'h3a0; + + assign wr_pmpcfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:4] == PMPCFG[11:4]); + assign wr_pmpcfg_group = dec_csr_wraddr_r[3:0]; // selects group of 4 pmpcfg entries (group 1 -> entries 4-7; up to 16 groups) + + for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpcfg_ff + logic [7:0] raw_wdata; + logic [7:0] csr_wdata; + + // PMPCFG fields are WARL. Mask out bits 6:5 during write. + // When Smepmp is disabled R=0 and W=1 combination is illegal mask out W + // when R is cleared. + assign raw_wdata = dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0]; +`ifdef RV_SMEPMP + assign csr_wdata = raw_wdata & 8'b10011111; +`else + assign csr_wdata = (raw_wdata & 8'b00000001) ? (raw_wdata & 8'b10011111) : (raw_wdata & 8'b10011101); +`endif + + rvdffe #(8) pmpcfg_ff (.*, .clk(free_l2clk), + .en(wr_pmpcfg_r & (wr_pmpcfg_group == entry_idx[5:2]) & (~entry_lock_eff[entry_idx])), + .din(csr_wdata), + .dout(pmp_pmpcfg[entry_idx])); + end + + // ---------------------------------------------------------------------- + // PMPADDRx (RW) + // [31:0] : PMP entry (x) address selector (word addressing) + // + // NOTE: VeeR-EL2 uses 32-bit physical addressing, register bits 31:30 mapping + // to bits 33:32 of the physical address are always set to 0. (WARL) + + localparam PMPADDR0 = 12'h3b0; + localparam PMPADDR16 = 12'h3c0; + localparam PMPADDR32 = 12'h3d0; + localparam PMPADDR48 = 12'h3e0; + + assign wr_pmpaddr0_sel = dec_csr_wraddr_r[11:4] == PMPADDR0[11:4]; + assign wr_pmpaddr16_sel = dec_csr_wraddr_r[11:4] == PMPADDR16[11:4]; + assign wr_pmpaddr32_sel = dec_csr_wraddr_r[11:4] == PMPADDR32[11:4]; + assign wr_pmpaddr48_sel = dec_csr_wraddr_r[11:4] == PMPADDR48[11:4]; + assign wr_pmpaddr_r = dec_csr_wen_r_mod & (wr_pmpaddr0_sel | wr_pmpaddr16_sel | wr_pmpaddr32_sel | wr_pmpaddr48_sel); + + assign wr_pmpaddr_quarter[0] = wr_pmpaddr16_sel | wr_pmpaddr48_sel; + assign wr_pmpaddr_quarter[1] = wr_pmpaddr32_sel | wr_pmpaddr48_sel; + assign wr_pmpaddr_address = {wr_pmpaddr_quarter, dec_csr_wraddr_r[3:0]}; // entry address + + for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff + logic pmpaddr_lock; + logic pmpaddr_lock_next; + if (entry_idx+1 < pt.PMP_ENTRIES) + assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR; + else + assign pmpaddr_lock_next = 1'b0; + assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next; + assign pmp_pmpaddr[entry_idx][31:30] = 2'b00; + rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk), + .en(wr_pmpaddr_r & (wr_pmpaddr_address == entry_idx) + & (~pmpaddr_lock)), + .din(dec_csr_wrdata_r[29:0]), + .dout(pmp_pmpaddr[entry_idx][29:0])); + end + + // CSR read mux + + assign pmp_quarter_rdaddr = dec_csr_rdaddr_d[3:0]; + assign pmp_pmpcfg_rddata = { pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h3}], + pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h2}], + pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h1}], + pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h0}] + }; + assign dec_pmp_read_d = csr_pmpcfg | csr_pmpaddr0 | csr_pmpaddr16 | csr_pmpaddr32 | csr_pmpaddr48; + assign dec_pmp_rddata_d[31:0] = ( ({32{csr_pmpcfg}} & pmp_pmpcfg_rddata) | + ({32{csr_pmpaddr0}} & pmp_pmpaddr[{2'h0, pmp_quarter_rdaddr}]) | + ({32{csr_pmpaddr16}} & pmp_pmpaddr[{2'h1, pmp_quarter_rdaddr}]) | + ({32{csr_pmpaddr32}} & pmp_pmpaddr[{2'h2, pmp_quarter_rdaddr}]) | + ({32{csr_pmpaddr48}} & pmp_pmpaddr[{2'h3, pmp_quarter_rdaddr}]) + ); + +endmodule // dec_pmp_ctl diff --git a/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv b/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv index ff4789aa1..2c239eb58 100644 --- a/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv @@ -91,6 +91,7 @@ import el2_pkg::*; input logic [11:0] dec_csr_rdaddr_d, // read address for csr input logic dec_csr_wen_r, // csr write enable at wb + input logic [11:0] dec_csr_rdaddr_r, // read address for csr input logic [11:0] dec_csr_wraddr_r, // write address for csr input logic [31:0] dec_csr_wrdata_r, // csr write data at wb @@ -233,8 +234,24 @@ import el2_pkg::*; output logic dec_tlu_pic_clk_override, // override PIC clock domain gating output logic dec_tlu_picio_clk_override,// override PICIO clock domain gating output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating - output logic dec_tlu_icm_clk_override // override ICCM clock domain gating + output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating +`ifdef RV_USER_MODE + + // Privilege mode + // 0 - machine, 1 - user + output logic priv_mode, + output logic priv_mode_eff, + output logic priv_mode_ns, + + // mseccfg CSR content for PMP + output logic [2:0] mseccfg, + +`endif + + // pmp + output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES], + output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES] ); logic clk_override, e4e5_int_clk, nmi_fir_type, nmi_lsu_load_type, nmi_lsu_store_type, nmi_int_detected_f, nmi_lsu_load_type_f, @@ -254,6 +271,12 @@ import el2_pkg::*; logic [1:1] mpmc_b_ns, mpmc, mpmc_b; logic set_mie_pmu_fw_halt, fw_halted_ns, fw_halted; logic wr_mcountinhibit_r; +`ifdef RV_USER_MODE + logic wr_mcounteren_r; + logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY + logic wr_mseccfg_r; + logic [2:0] mseccfg_ns; +`endif logic [6:0] mcountinhibit; logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r; logic [31:0] mtdata2_t0, mtdata2_t1, mtdata2_t2, mtdata2_t3, mtdata2_tsel_out, mtdata1_tsel_out; @@ -261,7 +284,11 @@ import el2_pkg::*; logic [9:0] tdata_wrdata_r; logic [1:0] mtsel_ns, mtsel; logic tlu_i0_kill_writeb_r; +`ifdef RV_USER_MODE + logic [3:0] mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE +`else logic [1:0] mstatus_ns, mstatus; +`endif logic [1:0] mfdhs_ns, mfdhs; logic [31:0] force_halt_ctr, force_halt_ctr_f; logic force_halt; @@ -359,7 +386,7 @@ import el2_pkg::*; mpc_debug_halt_ack_f, mpc_debug_run_ack_f, dbg_run_state_f, mpc_debug_halt_req_sync_pulse, mpc_debug_run_req_sync_pulse, debug_brkpt_valid, debug_halt_req, debug_resume_req, dec_tlu_mpc_halted_only_ns; logic take_ext_int_start, ext_int_freeze, take_ext_int_start_d1, take_ext_int_start_d2, - take_ext_int_start_d3, ext_int_freeze_d1, csr_meicpct, ignore_ext_int_due_to_lsu_stall; + take_ext_int_start_d3, ext_int_freeze_d1, ignore_ext_int_due_to_lsu_stall; logic mcause_sel_nmi_store, mcause_sel_nmi_load, mcause_sel_nmi_ext, fast_int_meicpct; logic [1:0] mcause_fir_error_type; logic dbg_halt_req_held_ns, dbg_halt_req_held, dbg_halt_req_final; @@ -369,12 +396,10 @@ import el2_pkg::*; // internal timer, isolated for size reasons logic [31:0] dec_timer_rddata_d; logic dec_timer_read_d, dec_timer_t0_pulse, dec_timer_t1_pulse; - logic csr_mitctl0; - logic csr_mitctl1; - logic csr_mitb0; - logic csr_mitb1; - logic csr_mitcnt0; - logic csr_mitcnt1; + + // PMP unit, isolated for size reasons + logic [31:0] dec_pmp_rddata_d; + logic dec_pmp_read_d; logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw; logic csr_wr_clk; @@ -412,66 +437,6 @@ import el2_pkg::*; el2_inst_pkt_t pmu_i0_itype_qual; - logic csr_mfdht; - logic csr_mfdhs; - logic csr_misa; - logic csr_mvendorid; - logic csr_marchid; - logic csr_mimpid; - logic csr_mhartid; - logic csr_mstatus; - logic csr_mtvec; - logic csr_mip; - logic csr_mie; - logic csr_mcyclel; - logic csr_mcycleh; - logic csr_minstretl; - logic csr_minstreth; - logic csr_mscratch; - logic csr_mepc; - logic csr_mcause; - logic csr_mscause; - logic csr_mtval; - logic csr_mrac; - logic csr_dmst; - logic csr_mdseac; - logic csr_meihap; - logic csr_meivt; - logic csr_meipt; - logic csr_meicurpl; - logic csr_meicidpl; - logic csr_dcsr; - logic csr_mcgc; - logic csr_mfdc; - logic csr_dpc; - logic csr_mtsel; - logic csr_mtdata1; - logic csr_mtdata2; - logic csr_mhpmc3; - logic csr_mhpmc4; - logic csr_mhpmc5; - logic csr_mhpmc6; - logic csr_mhpmc3h; - logic csr_mhpmc4h; - logic csr_mhpmc5h; - logic csr_mhpmc6h; - logic csr_mhpme3; - logic csr_mhpme4; - logic csr_mhpme5; - logic csr_mhpme6; - logic csr_mcountinhibit; - logic csr_mpmc; - logic csr_micect; - logic csr_miccmect; - logic csr_mdccmect; - logic csr_dicawics; - logic csr_dicad0h; - logic csr_dicad0; - logic csr_dicad1; - logic csr_dicago; - logic presync; - logic postsync; - logic legal; logic dec_csr_wen_r_mod; logic flush_clkvalid; @@ -491,9 +456,46 @@ import el2_pkg::*; logic [3:0] ifu_mscause ; logic ifu_ic_error_start_f, ifu_iccm_rd_ecc_single_err_f; + // CSR address decoder + +// files "csrdecode_m" (machine mode only) and "csrdecode_mu" (machine mode plus +// user mode) are human readable that have all of the CSR decodes defined and +// are part of the git repo. Modify these files as needed. + +// to generate all the equations below from "csrdecode" except legal equation: + +// 1) coredecode -in csrdecode > corecsrdecode.e + +// 2) espresso -Dso -oeqntott < corecsrdecode.e | addassign > csrequations + +// to generate the legal CSR equation below: + +// 1) coredecode -in csrdecode -legal > csrlegal.e + +// 2) espresso -Dso -oeqntott < csrlegal.e | addassign > csrlegal_equation + +// coredecode -in csrdecode > corecsrdecode.e; espresso -Dso -oeqntott < corecsrdecode.e | addassign > csrequations; coredecode -in csrdecode -legal > csrlegal.e; espresso -Dso -oeqntott csrlegal.e | addassign > csrlegal_equation + +`ifdef RV_USER_MODE + + `include "el2_dec_csr_equ_mu.svh" + + logic csr_acc_r; // CSR access error + logic csr_wr_usr_r; // Write to an unprivileged/user-level CSR + logic csr_rd_usr_r; // REad from an unprivileged/user-level CSR + +`else + + `include "el2_dec_csr_equ_m.svh" + +`endif + el2_dec_timer_ctl #(.pt(pt)) int_timers(.*); // end of internal timers + el2_dec_pmp_ctl #(.pt(pt)) pmp(.*); + // end of pmp + assign clk_override = dec_tlu_dec_clk_override; // Async inputs to the core have to be sync'd to the core clock. @@ -537,26 +539,424 @@ import el2_pkg::*; assign nmi_lsu_detected = ~mdseac_locked_f & (lsu_imprecise_error_load_any | lsu_imprecise_error_store_any) & ~nmi_fir_type; -localparam MSTATUS_MIE = 0; -localparam MIP_MCEIP = 5; -localparam MIP_MITIP0 = 4; -localparam MIP_MITIP1 = 3; -localparam MIP_MEIP = 2; -localparam MIP_MTIP = 1; -localparam MIP_MSIP = 0; +localparam MSTATUS_MIE = 0; +localparam int MSTATUS_MPIE = 1; +`ifdef RV_USER_MODE +localparam MSTATUS_MPP = 2; +localparam MSTATUS_MPRV = 3; +`endif + +localparam MIP_MCEIP = 5; +localparam MIP_MITIP0 = 4; +localparam MIP_MITIP1 = 3; +localparam MIP_MEIP = 2; +localparam MIP_MTIP = 1; +localparam MIP_MSIP = 0; + +localparam MIE_MCEIE = 5; +localparam MIE_MITIE0 = 4; +localparam MIE_MITIE1 = 3; +localparam MIE_MEIE = 2; +localparam MIE_MTIE = 1; +localparam MIE_MSIE = 0; + +localparam DCSR_EBREAKM = 15; +localparam DCSR_STEPIE = 11; +localparam DCSR_STOPC = 10; +localparam DCSR_STEP = 2; + +`ifdef RV_USER_MODE +localparam MCOUNTEREN_CY = 0; +localparam MCOUNTEREN_IR = 1; +localparam MCOUNTEREN_HPM3 = 2; +localparam MCOUNTEREN_HPM4 = 3; +localparam MCOUNTEREN_HPM5 = 4; +localparam MCOUNTEREN_HPM6 = 5; + +localparam MSECCFG_RLB = 2; +localparam MSECCFG_MMWP = 1; +localparam MSECCFG_MML = 0; +`endif + + // ---------------------------------------------------------------------- + // MISA (RO) + // [31:30] XLEN - implementation width, 2'b01 - 32 bits + // [20] U - user mode support (if enabled in config) + // [12] M - integer mul/div + // [8] I - RV32I + // [2] C - Compressed extension + localparam MISA = 12'h301; + + // MVENDORID, MARCHID, MIMPID, MHARTID + localparam MVENDORID = 12'hf11; + localparam MARCHID = 12'hf12; + localparam MIMPID = 12'hf13; + localparam MHARTID = 12'hf14; + + + // ---------------------------------------------------------------------- + // MSTATUS (RW) + // [17] MPRV : Modify PRiVilege (if enabled in config) + // [12:11] MPP : Prior priv level, either 2'b11 (machine) or 2'b00 (user) + // [7] MPIE : Int enable previous [1] + // [3] MIE : Int enable [0] + localparam MSTATUS = 12'h300; + + // ---------------------------------------------------------------------- + // MTVEC (RW) + // [31:2] BASE : Trap vector base address + // [1] - Reserved, not implemented, reads zero + // [0] MODE : 0 = Direct, 1 = Asyncs are vectored to BASE + (4 * CAUSE) + localparam MTVEC = 12'h305; + + // ---------------------------------------------------------------------- + // MIP (RW) + // + // [30] MCEIP : (RO) M-Mode Correctable Error interrupt pending + // [29] MITIP0 : (RO) M-Mode Internal Timer0 interrupt pending + // [28] MITIP1 : (RO) M-Mode Internal Timer1 interrupt pending + // [11] MEIP : (RO) M-Mode external interrupt pending + // [7] MTIP : (RO) M-Mode timer interrupt pending + // [3] MSIP : (RO) M-Mode software interrupt pending + localparam MIP = 12'h344; + + // ---------------------------------------------------------------------- + // MIE (RW) + // [30] MCEIE : (RO) M-Mode Correctable Error interrupt enable + // [29] MITIE0 : (RO) M-Mode Internal Timer0 interrupt enable + // [28] MITIE1 : (RO) M-Mode Internal Timer1 interrupt enable + // [11] MEIE : (RW) M-Mode external interrupt enable + // [7] MTIE : (RW) M-Mode timer interrupt enable + // [3] MSIE : (RW) M-Mode software interrupt enable + localparam MIE = 12'h304; + + // ---------------------------------------------------------------------- + // MCYCLEL (RW) + // [31:0] : Lower Cycle count + + localparam MCYCLEL = 12'hb00; + localparam logic [11:0] CYCLEL = 12'hc00; + + // ---------------------------------------------------------------------- + // MCYCLEH (RW) + // [63:32] : Higher Cycle count + // Chained with mcyclel. Note: mcyclel overflow due to a mcycleh write gets ignored. + + localparam MCYCLEH = 12'hb80; + localparam logic [11:0] CYCLEH = 12'hc80; + + // ---------------------------------------------------------------------- + // MINSTRETL (RW) + // [31:0] : Lower Instruction retired count + // From the spec "Some CSRs, such as the instructions retired counter, instret, may be modified as side effects + // of instruction execution. In these cases, if a CSR access instruction reads a CSR, it reads the + // value prior to the execution of the instruction. If a CSR access instruction writes a CSR, the + // update occurs after the execution of the instruction. In particular, a value written to instret by + // one instruction will be the value read by the following instruction (i.e., the increment of instret + // caused by the first instruction retiring happens before the write of the new value)." + localparam MINSTRETL = 12'hb02; + localparam logic [11:0] INSTRETL = 12'hc02; + + // ---------------------------------------------------------------------- + // MINSTRETH (RW) + // [63:32] : Higher Instret count + // Chained with minstretl. Note: minstretl overflow due to a minstreth write gets ignored. + + localparam MINSTRETH = 12'hb82; + localparam logic [11:0] INSTRETH = 12'hc82; + + // ---------------------------------------------------------------------- + // MSCRATCH (RW) + // [31:0] : Scratch register + localparam MSCRATCH = 12'h340; + + // ---------------------------------------------------------------------- + // MEPC (RW) + // [31:1] : Exception PC + localparam MEPC = 12'h341; + + // ---------------------------------------------------------------------- + // MCAUSE (RW) + // [31:0] : Exception Cause + localparam MCAUSE = 12'h342; + + // ---------------------------------------------------------------------- + // MSCAUSE (RW) + // [2:0] : Secondary exception Cause + localparam MSCAUSE = 12'h7ff; + + // ---------------------------------------------------------------------- + // MTVAL (RW) + // [31:0] : Exception address if relevant + localparam MTVAL = 12'h343; + + // ---------------------------------------------------------------------- + // MCGC (RW) Clock gating control + // [31:10]: Reserved, reads 0x0 + // [9] : picio_clk_override + // [7] : dec_clk_override + // [6] : Unused + // [5] : ifu_clk_override + // [4] : lsu_clk_override + // [3] : bus_clk_override + // [2] : pic_clk_override + // [1] : dccm_clk_override + // [0] : icm_clk_override + // + localparam MCGC = 12'h7f8; + + // ---------------------------------------------------------------------- + // MFDC (RW) Feature Disable Control + // [31:19] : Reserved, reads 0x0 + // [18:16] : DMA QoS Prty + // [15:13] : Reserved, reads 0x0 + // [12] : Disable trace + // [11] : Disable external load forwarding + // [10] : Disable dual issue + // [9] : Disable pic multiple ints + // [8] : Disable core ecc + // [7] : Disable secondary alu?s + // [6] : Unused, 0x0 + // [5] : Disable non-blocking loads/divides + // [4] : Disable fast divide + // [3] : Disable branch prediction and return stack + // [2] : Disable write buffer coalescing + // [1] : Disable load misses that bypass the write buffer + // [0] : Disable pipelining - Enable single instruction execution + // + localparam MFDC = 12'h7f9; + + // ---------------------------------------------------------------------- + // MRAC (RW) + // [31:0] : Region Access Control Register, 16 regions, {side_effect, cachable} pairs + localparam MRAC = 12'h7c0; + + // ---------------------------------------------------------------------- + // MDEAU (WAR0) + // [31:0] : Dbus Error Address Unlock register + // + localparam MDEAU = 12'hbc0; + + // ---------------------------------------------------------------------- + // MDSEAC (R) + // [31:0] : Dbus Store Error Address Capture register + // + localparam MDSEAC = 12'hfc0; + + // ---------------------------------------------------------------------- + // MPMC (R0W1) + // [0] : FW halt + // [1] : Set MSTATUS[MIE] on halt + localparam MPMC = 12'h7c6; + + // ---------------------------------------------------------------------- + // MICECT (I-Cache error counter/threshold) + // [31:27] : Icache parity error threshold + // [26:0] : Icache parity error count + localparam MICECT = 12'h7f0; + + // ---------------------------------------------------------------------- + // MICCMECT (ICCM error counter/threshold) + // [31:27] : ICCM parity error threshold + // [26:0] : ICCM parity error count + localparam MICCMECT = 12'h7f1; + + // ---------------------------------------------------------------------- + // MDCCMECT (DCCM error counter/threshold) + // [31:27] : DCCM parity error threshold + // [26:0] : DCCM parity error count + localparam MDCCMECT = 12'h7f2; + + // ---------------------------------------------------------------------- + // MFDHT (Force Debug Halt Threshold) + // [5:1] : Halt timeout threshold (power of 2) + // [0] : Halt timeout enabled + localparam MFDHT = 12'h7ce; + + // ---------------------------------------------------------------------- + // MFDHS(RW) + // [1] : LSU operation pending when debug halt threshold reached + // [0] : IFU operation pending when debug halt threshold reached + localparam MFDHS = 12'h7cf; + + // ---------------------------------------------------------------------- + // MEIVT (External Interrupt Vector Table (R/W)) + // [31:10]: Base address (R/W) + // [9:0] : Reserved, reads 0x0 + localparam MEIVT = 12'hbc8; + + // ---------------------------------------------------------------------- + // MEICURPL (R/W) + // [31:4] : Reserved (read 0x0) + // [3:0] : CURRPRI - Priority level of current interrupt service routine (R/W) + localparam MEICURPL = 12'hbcc; + + // ---------------------------------------------------------------------- + // MEICIDPL (R/W) + // [31:4] : Reserved (read 0x0) + // [3:0] : External Interrupt Claim ID's Priority Level Register + localparam MEICIDPL = 12'hbcb; + + // ---------------------------------------------------------------------- + // MEICPCT (Capture CLAIMID in MEIHAP and PL in MEICIDPL + // [31:1] : Reserved (read 0x0) + // [0] : Capture (W1, Read 0) + localparam MEICPCT = 12'hbca; + + // ---------------------------------------------------------------------- + // MEIPT (External Interrupt Priority Threshold) + // [31:4] : Reserved (read 0x0) + // [3:0] : PRITHRESH + localparam MEIPT = 12'hbc9; + + // ---------------------------------------------------------------------- + // DCSR (R/W) (Only accessible in debug mode) + // [31:28] : xdebugver (hard coded to 0x4) RO + // [27:16] : 0x0, reserved + // [15] : ebreakm + // [14] : 0x0, reserved + // [13] : ebreaks (0x0 for this core) + // [12] : ebreaku (0x0 for this core) + // [11] : stepie + // [10] : stopcount + // [9] : 0x0 //stoptime + // [8:6] : cause (RO) + // [5:4] : 0x0, reserved + // [3] : nmip + // [2] : step + // [1:0] : prv (0x3 for this core) + // + localparam DCSR = 12'h7b0; + + // ---------------------------------------------------------------------- + // DPC (R/W) (Only accessible in debug mode) + // [31:0] : Debug PC + localparam DPC = 12'h7b1; + + // ---------------------------------------------------------------------- + // DICAWICS (R/W) (Only accessible in debug mode) + // [31:25] : Reserved + // [24] : Array select, 0 is data, 1 is tag + // [23:22] : Reserved + // [21:20] : Way select + // [19:17] : Reserved + // [16:3] : Index + // [2:0] : Reserved + localparam DICAWICS = 12'h7c8; + + // ---------------------------------------------------------------------- + // DICAD0 (R/W) (Only accessible in debug mode) + // + // If dicawics[array] is 0 + // [31:0] : inst data + // + // If dicawics[array] is 1 + // [31:16] : Tag + // [15:7] : Reserved + // [6:4] : LRU + // [3:1] : Reserved + // [0] : Valid + localparam DICAD0 = 12'h7c9; + + // ---------------------------------------------------------------------- + // DICAD0H (R/W) (Only accessible in debug mode) + // + // If dicawics[array] is 0 + // [63:32] : inst data + // + localparam DICAD0H = 12'h7cc; + + // ---------------------------------------------------------------------- + // DICAGO (R/W) (Only accessible in debug mode) + // [0] : Go + localparam DICAGO = 12'h7cb; + + // ---------------------------------------------------------------------- + // MHPMC3H(RW), MHPMC3(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 3 + localparam MHPMC3 = 12'hB03; + localparam MHPMC3H = 12'hB83; +`ifdef RV_USER_MODE + localparam HPMC3 = 12'hC03; + localparam HPMC3H = 12'hC83; +`endif + + // ---------------------------------------------------------------------- + // MHPMC4H(RW), MHPMC4(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 4 + localparam MHPMC4 = 12'hB04; + localparam MHPMC4H = 12'hB84; +`ifdef RV_USER_MODE + localparam HPMC4 = 12'hC04; + localparam HPMC4H = 12'hC84; +`endif + + // ---------------------------------------------------------------------- + // MHPMC5H(RW), MHPMC5(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 5 + localparam MHPMC5 = 12'hB05; + localparam MHPMC5H = 12'hB85; +`ifdef RV_USER_MODE + localparam HPMC5 = 12'hC05; + localparam HPMC5H = 12'hC85; +`endif + + // ---------------------------------------------------------------------- + // MHPMC6H(RW), MHPMC6(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 6 + localparam MHPMC6 = 12'hB06; + localparam MHPMC6H = 12'hB86; +`ifdef RV_USER_MODE + localparam HPMC6 = 12'hC06; + localparam HPMC6H = 12'hC86; +`endif + + // ---------------------------------------------------------------------- + // MHPME3(RW) + // [9:0] : Hardware Performance Monitor Event 3 + localparam MHPME3 = 12'h323; + + // ---------------------------------------------------------------------- + // MHPME4(RW) + // [9:0] : Hardware Performance Monitor Event 4 + localparam MHPME4 = 12'h324; + + // ---------------------------------------------------------------------- + // MHPME5(RW) + // [9:0] : Hardware Performance Monitor Event 5 + localparam MHPME5 = 12'h325; + + // ---------------------------------------------------------------------- + // MHPME6(RW) + // [9:0] : Hardware Performance Monitor Event 6 + localparam MHPME6 = 12'h326; + + // MCOUNTINHIBIT(RW) + // [31:7] : Reserved, read 0x0 + // [6] : HPM6 disable + // [5] : HPM5 disable + // [4] : HPM4 disable + // [3] : HPM3 disable + // [2] : MINSTRET disable + // [1] : reserved, read 0x0 + // [0] : MCYCLE disable + + localparam MCOUNTINHIBIT = 12'h320; -localparam MIE_MCEIE = 5; -localparam MIE_MITIE0 = 4; -localparam MIE_MITIE1 = 3; -localparam MIE_MEIE = 2; -localparam MIE_MTIE = 1; -localparam MIE_MSIE = 0; + // ---------------------------------------------------------------------- + // MTSEL (R/W) + // [1:0] : Trigger select : 00, 01, 10 are data/address triggers. 11 is inst count + localparam MTSEL = 12'h7a0; -localparam DCSR_EBREAKM = 15; -localparam DCSR_STEPIE = 11; -localparam DCSR_STOPC = 10; -localparam DCSR_STEP = 2; + // ---------------------------------------------------------------------- + // MTDATA1 (R/W) + // [31:0] : Trigger Data 1 + localparam MTDATA1 = 12'h7a1; + // ---------------------------------------------------------------------- + // MTDATA2 (R/W) + // [31:0] : Trigger Data 2 + localparam MTDATA2 = 12'h7a2; assign reset_delayed = reset_detect ^ reset_detected; @@ -869,6 +1269,16 @@ localparam MTDATA1_LD = 0; (~lsu_error_pkt_r.inst_type & lsu_error_pkt_r.single_ecc_error); // Final commit valids +`ifdef RV_USER_MODE + assign tlu_i0_commit_cmt = dec_tlu_i0_valid_r & + ~rfpc_i0_r & + ~lsu_i0_exc_r & + ~inst_acc_r & + ~dec_tlu_dbg_halted & + ~request_debug_mode_r_d1 & + ~i0_trigger_hit_r & + ~csr_acc_r; +`else assign tlu_i0_commit_cmt = dec_tlu_i0_valid_r & ~rfpc_i0_r & ~lsu_i0_exc_r & @@ -876,9 +1286,14 @@ localparam MTDATA1_LD = 0; ~dec_tlu_dbg_halted & ~request_debug_mode_r_d1 & ~i0_trigger_hit_r; +`endif // unified place to manage the killing of arch state writebacks +`ifdef RV_USER_MODE + assign tlu_i0_kill_writeb_r = rfpc_i0_r | lsu_i0_exc_r | inst_acc_r | (illegal_r & dec_tlu_dbg_halted) | i0_trigger_hit_r | csr_acc_r; +`else assign tlu_i0_kill_writeb_r = rfpc_i0_r | lsu_i0_exc_r | inst_acc_r | (illegal_r & dec_tlu_dbg_halted) | i0_trigger_hit_r; +`endif assign dec_tlu_i0_commit_cmt = tlu_i0_commit_cmt; @@ -924,8 +1339,13 @@ end // else: !if(pt.BTB_ENABLE==1) // only expect these in pipe 0 assign ebreak_r = (dec_tlu_packet_r.pmu_i0_itype == EBREAK) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr[DCSR_EBREAKM] & ~rfpc_i0_r; assign ecall_r = (dec_tlu_packet_r.pmu_i0_itype == ECALL) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r; +`ifdef RV_USER_MODE + assign illegal_r = (((dec_tlu_packet_r.pmu_i0_itype == MRET) & priv_mode) | ~dec_tlu_packet_r.legal) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r; + assign mret_r = ( (dec_tlu_packet_r.pmu_i0_itype == MRET) & ~priv_mode ) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r; +`else assign illegal_r = ~dec_tlu_packet_r.legal & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r; assign mret_r = (dec_tlu_packet_r.pmu_i0_itype == MRET) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r; +`endif // fence_i includes debug only fence_i's assign fence_i_r = (dec_tlu_packet_r.fence_i & dec_tlu_i0_valid_r & ~i0_trigger_hit_r) & ~rfpc_i0_r; assign ic_perr_r = ifu_ic_error_start_f & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f; @@ -941,6 +1361,54 @@ end // else: !if(pt.BTB_ENABLE==1) .dout(ebreak_to_debug_mode_r_d1)); assign dec_tlu_fence_i_r = fence_i_r; + +`ifdef RV_USER_MODE + + // CSR access + // Address bits 9:8 == 2'b00 indicate unprivileged / user-level CSR + assign csr_wr_usr_r = ~|dec_csr_wraddr_r[9:8]; + assign csr_rd_usr_r = ~|dec_csr_rdaddr_r[9:8]; + + // CSR access error + // cycle and instret CSR unprivileged access is controller by bits in mcounteren CSR + logic csr_wr_acc_r; + logic csr_rd_acc_r; + + assign csr_wr_acc_r = csr_wr_usr_r & ( + ((dec_csr_wraddr_r[11:0] == CYCLEL) & mcounteren[MCOUNTEREN_CY]) | + ((dec_csr_wraddr_r[11:0] == CYCLEH) & mcounteren[MCOUNTEREN_CY]) | + ((dec_csr_wraddr_r[11:0] == INSTRETL) & mcounteren[MCOUNTEREN_IR]) | + ((dec_csr_wraddr_r[11:0] == INSTRETH) & mcounteren[MCOUNTEREN_IR]) | + ((dec_csr_wraddr_r[11:0] == HPMC3) & mcounteren[MCOUNTEREN_HPM3]) | + ((dec_csr_wraddr_r[11:0] == HPMC3H) & mcounteren[MCOUNTEREN_HPM3]) | + ((dec_csr_wraddr_r[11:0] == HPMC4) & mcounteren[MCOUNTEREN_HPM4]) | + ((dec_csr_wraddr_r[11:0] == HPMC4H) & mcounteren[MCOUNTEREN_HPM4]) | + ((dec_csr_wraddr_r[11:0] == HPMC5) & mcounteren[MCOUNTEREN_HPM5]) | + ((dec_csr_wraddr_r[11:0] == HPMC5H) & mcounteren[MCOUNTEREN_HPM5]) | + ((dec_csr_wraddr_r[11:0] == HPMC6) & mcounteren[MCOUNTEREN_HPM6]) | + ((dec_csr_wraddr_r[11:0] == HPMC6H) & mcounteren[MCOUNTEREN_HPM6])); + + assign csr_rd_acc_r = csr_rd_usr_r & ( + ((dec_csr_rdaddr_r[11:0] == CYCLEL) & mcounteren[MCOUNTEREN_CY]) | + ((dec_csr_rdaddr_r[11:0] == CYCLEH) & mcounteren[MCOUNTEREN_CY]) | + ((dec_csr_rdaddr_r[11:0] == INSTRETL) & mcounteren[MCOUNTEREN_IR]) | + ((dec_csr_rdaddr_r[11:0] == INSTRETH) & mcounteren[MCOUNTEREN_IR]) | + ((dec_csr_rdaddr_r[11:0] == HPMC3) & mcounteren[MCOUNTEREN_HPM3]) | + ((dec_csr_rdaddr_r[11:0] == HPMC3H) & mcounteren[MCOUNTEREN_HPM3]) | + ((dec_csr_rdaddr_r[11:0] == HPMC4) & mcounteren[MCOUNTEREN_HPM4]) | + ((dec_csr_rdaddr_r[11:0] == HPMC4H) & mcounteren[MCOUNTEREN_HPM4]) | + ((dec_csr_rdaddr_r[11:0] == HPMC5) & mcounteren[MCOUNTEREN_HPM5]) | + ((dec_csr_rdaddr_r[11:0] == HPMC5H) & mcounteren[MCOUNTEREN_HPM5]) | + ((dec_csr_rdaddr_r[11:0] == HPMC6) & mcounteren[MCOUNTEREN_HPM6]) | + ((dec_csr_rdaddr_r[11:0] == HPMC6H) & mcounteren[MCOUNTEREN_HPM6])); + + assign csr_acc_r = priv_mode & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r & ( + (dec_tlu_packet_r.pmu_i0_itype == CSRREAD) & ~csr_rd_acc_r | + (dec_tlu_packet_r.pmu_i0_itype == CSRWRITE) & ~csr_wr_acc_r | + (dec_tlu_packet_r.pmu_i0_itype == CSRRW) & ~csr_rd_acc_r & ~csr_wr_acc_r); + +`endif + // // Exceptions // @@ -952,24 +1420,35 @@ end // else: !if(pt.BTB_ENABLE==1) // - MPIE <- MIE // - MIE <- 0 // +`ifdef RV_USER_MODE + assign i0_exception_valid_r = (ebreak_r | ecall_r | illegal_r | inst_acc_r | csr_acc_r) & ~rfpc_i0_r & ~dec_tlu_dbg_halted; +`else assign i0_exception_valid_r = (ebreak_r | ecall_r | illegal_r | inst_acc_r) & ~rfpc_i0_r & ~dec_tlu_dbg_halted; +`endif // Cause: // // 0x2 : illegal // 0x3 : breakpoint + // 0x8 : Environment call U-mode (if U-mode is enabled) // 0xb : Environment call M-mode - assign exc_cause_r[4:0] = ( ({5{take_ext_int}} & 5'h0b) | - ({5{take_timer_int}} & 5'h07) | - ({5{take_soft_int}} & 5'h03) | - ({5{take_int_timer0_int}} & 5'h1d) | - ({5{take_int_timer1_int}} & 5'h1c) | - ({5{take_ce_int}} & 5'h1e) | - ({5{illegal_r}} & 5'h02) | - ({5{ecall_r}} & 5'h0b) | - ({5{inst_acc_r}} & 5'h01) | + assign exc_cause_r[4:0] = ( ({5{take_ext_int}} & 5'h0b) | + ({5{take_timer_int}} & 5'h07) | + ({5{take_soft_int}} & 5'h03) | + ({5{take_int_timer0_int}} & 5'h1d) | + ({5{take_int_timer1_int}} & 5'h1c) | + ({5{take_ce_int}} & 5'h1e) | +`ifdef RV_USER_MODE + ({5{illegal_r| csr_acc_r}} & 5'h02) | + ({5{ecall_r & priv_mode}} & 5'h08) | + ({5{ecall_r & ~priv_mode}} & 5'h0b) | +`else + ({5{illegal_r}} & 5'h02) | + ({5{ecall_r}} & 5'h0b) | +`endif + ({5{inst_acc_r}} & 5'h01) | ({5{ebreak_r | i0_trigger_hit_r}} & 5'h03) | ({5{lsu_exc_ma_r & ~lsu_exc_st_r}} & 5'h04) | ({5{lsu_exc_acc_r & ~lsu_exc_st_r}} & 5'h05) | @@ -1114,6 +1593,23 @@ end .dout({interrupt_valid_r_d1, i0_exception_valid_r_d1, exc_or_int_valid_r_d1, exc_cause_wb[4:0], i0_valid_wb, trigger_hit_r_d1, take_nmi_r_d1, pause_expired_wb})); +`ifdef RV_USER_MODE + + // + // Privilege mode + // + assign priv_mode_ns = (mret_r & mstatus[MSTATUS_MPP]) | + (exc_or_int_valid_r & 1'b0 ) | + ((~mret_r & ~exc_or_int_valid_r) & priv_mode); + + rvdff #(1) priv_ff ( + .clk (free_l2clk), + .rst_l (rst_l), + .din (priv_mode_ns), + .dout (priv_mode) + ); + +`endif //---------------------------------------------------------------------- // @@ -1121,55 +1617,62 @@ end // //---------------------------------------------------------------------- - - // ---------------------------------------------------------------------- - // MISA (RO) - // [31:30] XLEN - implementation width, 2'b01 - 32 bits - // [12] M - integer mul/div - // [8] I - RV32I - // [2] C - Compressed extension - localparam MISA = 12'h301; - - // MVENDORID, MARCHID, MIMPID, MHARTID - localparam MVENDORID = 12'hf11; - localparam MARCHID = 12'hf12; - localparam MIMPID = 12'hf13; - localparam MHARTID = 12'hf14; - - // ---------------------------------------------------------------------- // MSTATUS (RW) - // [12:11] MPP : Prior priv level, always 2'b11, not flopped + // [17] MPRV : Modify PRiVilege (if enabled in config) + // [12:11] MPP : Prior priv level, either 2'b11 (machine) or 2'b00 (user) // [7] MPIE : Int enable previous [1] // [3] MIE : Int enable [0] - localparam MSTATUS = 12'h300; //When executing a MRET instruction, supposing MPP holds the value 3, MIE //is set to MPIE; the privilege mode is changed to 3; MPIE is set to 1; and MPP is set to 3 - +`ifdef RV_USER_MODE + assign dec_csr_wen_r_mod = dec_csr_wen_r & ~i0_trigger_hit_r & ~rfpc_i0_r & ~csr_acc_r; +`else assign dec_csr_wen_r_mod = dec_csr_wen_r & ~i0_trigger_hit_r & ~rfpc_i0_r; +`endif + assign wr_mstatus_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSTATUS); // set this even if we don't go to fwhalt due to debug halt. We committed the inst, so ... assign set_mie_pmu_fw_halt = ~mpmc_b_ns[1] & fw_halt_req; +`ifdef RV_USER_MODE + // mstatus[2] / mstatus_ns[2] actually stores inverse of the MPP field ! + assign mstatus_ns[3:0] = ( ({4{~wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MPRV], priv_mode, mstatus[MSTATUS_MIE], 1'b0}) | + ({4{ wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MPRV], priv_mode, dec_csr_wrdata_r[3], 1'b0}) | + ({4{mret_r & ~exc_or_int_valid_r}} & {mstatus[MSTATUS_MPRV] & ~mstatus[MSTATUS_MPP], 1'b1, 1'b1, mstatus[MSTATUS_MPIE]}) | + ({4{set_mie_pmu_fw_halt}} & {mstatus[3:2], mstatus[MSTATUS_MPIE], 1'b1}) | + ({4{wr_mstatus_r & ~exc_or_int_valid_r}} & {dec_csr_wrdata_r[17], ~dec_csr_wrdata_r[12], dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]}) | + ({4{~wr_mstatus_r & ~exc_or_int_valid_r & ~mret_r & ~set_mie_pmu_fw_halt}} & mstatus[3:0]) ); + + // gate MIE if we are single stepping and DCSR[STEPIE] is off + // in user mode machine interrupts are always enabled as per RISC-V privilege spec (chapter 3.1.6.1). + assign mstatus_mie_ns = (priv_mode | mstatus[MSTATUS_MIE]) & (~dcsr_single_step_running_f | dcsr[DCSR_STEPIE]); + + // set effective privilege mode according to MPRV and MPP + assign priv_mode_eff = ( mstatus[MSTATUS_MPRV] & mstatus[MSTATUS_MPP]) | // MPRV=1, use MPP + (~mstatus[MSTATUS_MPRV] & priv_mode); // MPRV=0, use current operating mode + +`else + assign mstatus_ns[1:0] = ( ({2{~wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MIE], 1'b0}) | ({2{ wr_mstatus_r & exc_or_int_valid_r}} & {dec_csr_wrdata_r[3], 1'b0}) | - ({2{mret_r & ~exc_or_int_valid_r}} & {1'b1, mstatus[1]}) | - ({2{set_mie_pmu_fw_halt}} & {mstatus[1], 1'b1}) | + ({2{mret_r & ~exc_or_int_valid_r}} & {1'b1, mstatus[MSTATUS_MPIE]}) | + ({2{set_mie_pmu_fw_halt}} & {mstatus[MSTATUS_MPIE], 1'b1}) | ({2{wr_mstatus_r & ~exc_or_int_valid_r}} & {dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]}) | ({2{~wr_mstatus_r & ~exc_or_int_valid_r & ~mret_r & ~set_mie_pmu_fw_halt}} & mstatus[1:0]) ); - // gate MIE if we are single stepping and DCSR[STEPIE] is off assign mstatus_mie_ns = mstatus[MSTATUS_MIE] & (~dcsr_single_step_running_f | dcsr[DCSR_STEPIE]); +`endif + // ---------------------------------------------------------------------- // MTVEC (RW) // [31:2] BASE : Trap vector base address // [1] - Reserved, not implemented, reads zero // [0] MODE : 0 = Direct, 1 = Asyncs are vectored to BASE + (4 * CAUSE) - localparam MTVEC = 12'h305; assign wr_mtvec_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVEC); assign mtvec_ns[30:0] = {dec_csr_wrdata_r[31:2], dec_csr_wrdata_r[0]} ; @@ -1184,7 +1687,6 @@ end // [11] MEIP : (RO) M-Mode external interrupt pending // [7] MTIP : (RO) M-Mode timer interrupt pending // [3] MSIP : (RO) M-Mode software interrupt pending - localparam MIP = 12'h344; assign ce_int = (mdccme_ce_req | miccme_ce_req | mice_ce_req); @@ -1198,7 +1700,6 @@ end // [11] MEIE : (RW) M-Mode external interrupt enable // [7] MTIE : (RW) M-Mode timer interrupt enable // [3] MSIE : (RW) M-Mode software interrupt enable - localparam MIE = 12'h304; assign wr_mie_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MIE); assign mie_ns[5:0] = wr_mie_r ? {dec_csr_wrdata_r[30:28], dec_csr_wrdata_r[11], dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]} : mie[5:0]; @@ -1209,8 +1710,6 @@ end // MCYCLEL (RW) // [31:0] : Lower Cycle count - localparam MCYCLEL = 12'hb00; - assign kill_ebreak_count_r = ebreak_to_debug_mode_r & dcsr[DCSR_STOPC]; assign wr_mcyclel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEL); @@ -1231,8 +1730,6 @@ end // [63:32] : Higher Cycle count // Chained with mcyclel. Note: mcyclel overflow due to a mcycleh write gets ignored. - localparam MCYCLEH = 12'hb80; - assign wr_mcycleh_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEH); assign mcycleh_inc[31:0] = mcycleh[31:0] + {31'b0, mcyclel_cout_f}; @@ -1249,7 +1746,6 @@ end // update occurs after the execution of the instruction. In particular, a value written to instret by // one instruction will be the value read by the following instruction (i.e., the increment of instret // caused by the first instruction retiring happens before the write of the new value)." - localparam MINSTRETL = 12'hb02; assign i0_valid_no_ebreak_ecall_r = dec_tlu_i0_valid_r & ~(ebreak_r | ecall_r | ebreak_to_debug_mode_r | illegal_r | mcountinhibit[2]); @@ -1275,8 +1771,6 @@ end // [63:32] : Higher Instret count // Chained with minstretl. Note: minstretl overflow due to a minstreth write gets ignored. - localparam MINSTRETH = 12'hb82; - assign wr_minstreth_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MINSTRETH); assign minstreth_inc[31:0] = minstreth[31:0] + {31'b0, minstretl_cout_f}; @@ -1288,8 +1782,6 @@ end // ---------------------------------------------------------------------- // MSCRATCH (RW) // [31:0] : Scratch register - localparam MSCRATCH = 12'h340; - assign wr_mscratch_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCRATCH); rvdffe #(32) mscratch_ff (.*, .en(wr_mscratch_r), .din(dec_csr_wrdata_r[31:0]), .dout(mscratch[31:0])); @@ -1297,7 +1789,6 @@ end // ---------------------------------------------------------------------- // MEPC (RW) // [31:1] : Exception PC - localparam MEPC = 12'h341; // NPC @@ -1334,7 +1825,6 @@ end // ---------------------------------------------------------------------- // MCAUSE (RW) // [31:0] : Exception Cause - localparam MCAUSE = 12'h342; assign wr_mcause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCAUSE); assign mcause_sel_nmi_store = exc_or_int_valid_r & take_nmi & nmi_lsu_store_type; @@ -1358,8 +1848,6 @@ end // ---------------------------------------------------------------------- // MSCAUSE (RW) // [2:0] : Secondary exception Cause - localparam MSCAUSE = 12'h7ff; - assign wr_mscause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCAUSE); assign ifu_mscause[3:0] = (dec_tlu_packet_r.icaf_type[1:0] == 2'b00) ? 4'b1001 : @@ -1380,7 +1868,6 @@ end // ---------------------------------------------------------------------- // MTVAL (RW) // [31:0] : Exception address if relevant - localparam MTVAL = 12'h343; assign wr_mtval_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVAL); assign mtval_capture_pc_r = exc_or_int_valid_r & (ebreak_r | (inst_acc_r & ~inst_acc_second_r) | mepc_trigger_hit_sel_pc_r) & ~take_nmi; @@ -1400,6 +1887,42 @@ end rvdffe #(32) mtval_ff (.*, .en(tlu_flush_lower_r | wr_mtval_r), .din(mtval_ns[31:0]), .dout(mtval[31:0])); + // ---------------------------------------------------------------------- + // MSECCFG + // [31:3] : Reserved, read 0x0 + // [2] : RLB + // [1] : MMWP + // [0] : MML + +`ifdef RV_USER_MODE + + localparam MSECCFG = 12'h747; + localparam MSECCFGH = 12'h757; + + // Detect if any PMP region is locked regardless of being enabled. This is + // necessary for mseccfg.RLB bit write behavior + logic [pt.PMP_ENTRIES-1:0] pmp_region_locked; + for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions + assign pmp_region_locked[r] = pmp_pmpcfg[r].lock; + end + + logic pmp_any_region_locked; + assign pmp_any_region_locked = |pmp_region_locked; + + // mseccfg + assign wr_mseccfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSECCFG); + rvdffs #(3) mseccfg_ff (.*, .clk(csr_wr_clk), .en(wr_mseccfg_r), .din(mseccfg_ns), .dout(mseccfg)); + + assign mseccfg_ns = { + pmp_any_region_locked ? + (dec_csr_wrdata_r[MSECCFG_RLB] & mseccfg[MSECCFG_RLB]) : // When any PMP region is locked this bit can only be cleared + dec_csr_wrdata_r[MSECCFG_RLB], // Otherwise regularly writeable + dec_csr_wrdata_r[MSECCFG_MMWP] | mseccfg[MSECCFG_MMWP], // Sticky bit, can only be set but not cleared + dec_csr_wrdata_r[MSECCFG_MML ] | mseccfg[MSECCFG_MML ] // Sticky bit, can only be set but never cleared + }; + +`endif + // ---------------------------------------------------------------------- // MCGC (RW) Clock gating control // [31:10]: Reserved, reads 0x0 @@ -1413,7 +1936,6 @@ end // [1] : dccm_clk_override // [0] : icm_clk_override // - localparam MCGC = 12'h7f8; assign wr_mcgc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCGC); assign mcgc_ns[9:0] = wr_mcgc_r ? {~dec_csr_wrdata_r[9], dec_csr_wrdata_r[8:0]} : mcgc_int[9:0]; @@ -1451,7 +1973,6 @@ end // [1] : Disable load misses that bypass the write buffer // [0] : Disable pipelining - Enable single instruction execution // - localparam MFDC = 12'h7f9; assign wr_mfdc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDC); @@ -1488,7 +2009,6 @@ end // ---------------------------------------------------------------------- // MRAC (RW) // [31:0] : Region Access Control Register, 16 regions, {side_effect, cachable} pairs - localparam MRAC = 12'h7c0; assign wr_mrac_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MRAC); @@ -1519,7 +2039,6 @@ end // MDEAU (WAR0) // [31:0] : Dbus Error Address Unlock register // - localparam MDEAU = 12'hbc0; assign wr_mdeau_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDEAU); @@ -1528,7 +2047,6 @@ end // MDSEAC (R) // [31:0] : Dbus Store Error Address Capture register // - localparam MDSEAC = 12'hfc0; // only capture error bus if the MDSEAC reg is not locked assign mdseac_locked_ns = mdseac_en | (mdseac_locked_f & ~wr_mdeau_r); @@ -1542,8 +2060,6 @@ end // [0] : FW halt // [1] : Set MSTATUS[MIE] on halt - localparam MPMC = 12'h7c6; - assign wr_mpmc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MPMC); // allow the cycle of the dbg halt flush that contains the wr_mpmc_r to @@ -1559,7 +2075,6 @@ end // MICECT (I-Cache error counter/threshold) // [31:27] : Icache parity error threshold // [26:0] : Icache parity error count - localparam MICECT = 12'h7f0; assign csr_sat[31:27] = (dec_csr_wrdata_r[31:27] > 5'd26) ? 5'd26 : dec_csr_wrdata_r[31:27]; @@ -1575,7 +2090,6 @@ end // MICCMECT (ICCM error counter/threshold) // [31:27] : ICCM parity error threshold // [26:0] : ICCM parity error count - localparam MICCMECT = 12'h7f1; assign wr_miccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MICCMECT); assign miccmect_inc[26:0] = miccmect[26:0] + {26'b0, iccm_sbecc_r | iccm_dma_sb_error}; @@ -1589,7 +2103,6 @@ end // MDCCMECT (DCCM error counter/threshold) // [31:27] : DCCM parity error threshold // [26:0] : DCCM parity error count - localparam MDCCMECT = 12'h7f2; assign wr_mdccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDCCMECT); assign mdccmect_inc[26:0] = mdccmect[26:0] + {26'b0, lsu_single_ecc_error_r_d1}; @@ -1604,7 +2117,6 @@ end // MFDHT (Force Debug Halt Threshold) // [5:1] : Halt timeout threshold (power of 2) // [0] : Halt timeout enabled - localparam MFDHT = 12'h7ce; assign wr_mfdht_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHT); @@ -1612,13 +2124,11 @@ end rvdffs #(6) mfdht_ff (.*, .clk(csr_wr_clk), .en(wr_mfdht_r), .din(mfdht_ns[5:0]), .dout(mfdht[5:0])); - // ---------------------------------------------------------------------- + // ---------------------------------------------------------------------- // MFDHS(RW) // [1] : LSU operation pending when debug halt threshold reached // [0] : IFU operation pending when debug halt threshold reached - localparam MFDHS = 12'h7cf; - assign wr_mfdhs_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHS); assign mfdhs_ns[1:0] = wr_mfdhs_r ? dec_csr_wrdata_r[1:0] : ((dbg_tlu_halted & ~dbg_tlu_halted_f) ? {~lsu_idle_any_f, ~ifu_miss_state_idle_f} : mfdhs[1:0]); @@ -1636,8 +2146,6 @@ end // MEIVT (External Interrupt Vector Table (R/W)) // [31:10]: Base address (R/W) // [9:0] : Reserved, reads 0x0 - localparam MEIVT = 12'hbc8; - assign wr_meivt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIVT); rvdffe #(22) meivt_ff (.*, .en(wr_meivt_r), .din(dec_csr_wrdata_r[31:10]), .dout(meivt[31:10])); @@ -1648,19 +2156,17 @@ end // [31:10]: Base address (R/W) // [9:2] : ClaimID (R) // [1:0] : Reserved, 0x0 - localparam MEIHAP = 12'hfc8; assign wr_meihap_r = wr_meicpct_r; rvdffe #(8) meihap_ff (.*, .en(wr_meihap_r), .din(pic_claimid[7:0]), .dout(meihap[9:2])); assign dec_tlu_meihap[31:2] = {meivt[31:10], meihap[9:2]}; + // ---------------------------------------------------------------------- // MEICURPL (R/W) // [31:4] : Reserved (read 0x0) // [3:0] : CURRPRI - Priority level of current interrupt service routine (R/W) - localparam MEICURPL = 12'hbcc; - assign wr_meicurpl_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICURPL); assign meicurpl_ns[3:0] = wr_meicurpl_r ? dec_csr_wrdata_r[3:0] : meicurpl[3:0]; @@ -1674,7 +2180,6 @@ end // MEICIDPL (R/W) // [31:4] : Reserved (read 0x0) // [3:0] : External Interrupt Claim ID's Priority Level Register - localparam MEICIDPL = 12'hbcb; assign wr_meicidpl_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICIDPL)) | take_ext_int_start; @@ -1685,15 +2190,12 @@ end // MEICPCT (Capture CLAIMID in MEIHAP and PL in MEICIDPL // [31:1] : Reserved (read 0x0) // [0] : Capture (W1, Read 0) - localparam MEICPCT = 12'hbca; - assign wr_meicpct_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICPCT)) | take_ext_int_start; // ---------------------------------------------------------------------- // MEIPT (External Interrupt Priority Threshold) // [31:4] : Reserved (read 0x0) // [3:0] : PRITHRESH - localparam MEIPT = 12'hbc9; assign wr_meipt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIPT); assign meipt_ns[3:0] = wr_meipt_r ? dec_csr_wrdata_r[3:0] : meipt[3:0]; @@ -1719,7 +2221,6 @@ end // [2] : step // [1:0] : prv (0x3 for this core) // - localparam DCSR = 12'h7b0; // RV has clarified that 'priority 4' in the spec means top priority. // 4. single step. 3. Debugger request. 2. Ebreak. 1. Trigger. @@ -1751,7 +2252,6 @@ end // ---------------------------------------------------------------------- // DPC (R/W) (Only accessible in debug mode) // [31:0] : Debug PC - localparam DPC = 12'h7b1; assign wr_dpc_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DPC); assign dpc_capture_npc = dbg_tlu_halted & ~dbg_tlu_halted_f & ~request_debug_mode_done; @@ -1772,7 +2272,6 @@ end // [19:17] : Reserved // [16:3] : Index // [2:0] : Reserved - localparam DICAWICS = 12'h7c8; assign dicawics_ns[16:0] = {dec_csr_wrdata_r[24], dec_csr_wrdata_r[21:20], dec_csr_wrdata_r[16:3]}; assign wr_dicawics_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAWICS); @@ -1791,7 +2290,6 @@ end // [6:4] : LRU // [3:1] : Reserved // [0] : Valid - localparam DICAD0 = 12'h7c9; assign dicad0_ns[31:0] = wr_dicad0_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[31:0]; @@ -1805,7 +2303,6 @@ end // If dicawics[array] is 0 // [63:32] : inst data // - localparam DICAD0H = 12'h7cc; assign dicad0h_ns[31:0] = wr_dicad0h_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[63:32]; @@ -1846,7 +2343,6 @@ end // ---------------------------------------------------------------------- // DICAGO (R/W) (Only accessible in debug mode) // [0] : Go - localparam DICAGO = 12'h7cb; if (pt.ICACHE_ECC == 1) assign dec_tlu_ic_diag_pkt.icache_wrdata[70:0] = { dicad1[6:0], dicad0h[31:0], dicad0[31:0]}; @@ -1866,7 +2362,6 @@ else // ---------------------------------------------------------------------- // MTSEL (R/W) // [1:0] : Trigger select : 00, 01, 10 are data/address triggers. 11 is inst count - localparam MTSEL = 12'h7a0; assign wr_mtsel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTSEL); assign mtsel_ns[1:0] = wr_mtsel_r ? {dec_csr_wrdata_r[1:0]} : mtsel[1:0]; @@ -1876,7 +2371,6 @@ else // ---------------------------------------------------------------------- // MTDATA1 (R/W) // [31:0] : Trigger Data 1 - localparam MTDATA1 = 12'h7a1; // for triggers 0, 1, 2 and 3 aka Match Control // [31:28] : type, hard coded to 0x2 @@ -1996,7 +2490,6 @@ else // ---------------------------------------------------------------------- // MTDATA2 (R/W) // [31:0] : Trigger Data 2 - localparam MTDATA2 = 12'h7a2; // If the DMODE bit is set, tdata2 can only be updated in debug_mode assign wr_mtdata2_t0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b0) & (~mtdata1_t0[MTDATA1_DMODE] | dbg_tlu_halted_f); @@ -2161,6 +2654,22 @@ else if(pt.FAST_INTERRUPT_REDIRECT) begin : genblock2 + +`ifdef RV_USER_MODE + rvdffie #(33) mstatus_ff (.*, .clk(free_l2clk), + .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r, + take_ext_int_start, take_ext_int_start_d1, take_ext_int_start_d2, ext_int_freeze, + mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in, + minstret_enable, minstretl_cout_ns, fw_halted_ns, + meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted, + mstatus_ns[3:0]}), + .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, + take_ext_int_start_d1, take_ext_int_start_d2, take_ext_int_start_d3, ext_int_freeze_d1, + mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f, + fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f, + mhpmc_inc_r_d1[3:0], perfcnt_halted_d1, + mstatus[3:0]})); +`else rvdffie #(31) mstatus_ff (.*, .clk(free_l2clk), .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r, take_ext_int_start, take_ext_int_start_d1, take_ext_int_start_d2, ext_int_freeze, @@ -2175,8 +2684,23 @@ else mhpmc_inc_r_d1[3:0], perfcnt_halted_d1, mstatus[1:0]})); +`endif + end else begin : genblock2 +`ifdef RV_USER_MODE + rvdffie #(29) mstatus_ff (.*, .clk(free_l2clk), + .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r, + mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in, + minstret_enable, minstretl_cout_ns, fw_halted_ns, + meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted, + mstatus_ns[3:0]}), + .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, + mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f, + fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f, + mhpmc_inc_r_d1[3:0], perfcnt_halted_d1, + mstatus[3:0]})); +`else rvdffie #(27) mstatus_ff (.*, .clk(free_l2clk), .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r, mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in, @@ -2188,8 +2712,9 @@ else fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f, mhpmc_inc_r_d1[3:0], perfcnt_halted_d1, mstatus[1:0]})); +`endif end - + assign perfcnt_halted = ((dec_tlu_dbg_halted & dcsr[DCSR_STOPC]) | dec_tlu_pmu_fw_halted); assign perfcnt_during_sleep[3:0] = {4{~(dec_tlu_dbg_halted & dcsr[DCSR_STOPC])}} & {mhpme_vec[3][9],mhpme_vec[2][9],mhpme_vec[1][9],mhpme_vec[0][9]}; @@ -2201,8 +2726,6 @@ else // ---------------------------------------------------------------------- // MHPMC3H(RW), MHPMC3(RW) // [63:32][31:0] : Hardware Performance Monitor Counter 3 - localparam MHPMC3 = 12'hB03; - localparam MHPMC3H = 12'hB83; assign mhpmc3_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC3); assign mhpmc3_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[0]) & (|(mhpmc_inc_r[0])); @@ -2219,8 +2742,6 @@ else // ---------------------------------------------------------------------- // MHPMC4H(RW), MHPMC4(RW) // [63:32][31:0] : Hardware Performance Monitor Counter 4 - localparam MHPMC4 = 12'hB04; - localparam MHPMC4H = 12'hB84; assign mhpmc4_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC4); assign mhpmc4_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[1]) & (|(mhpmc_inc_r[1])); @@ -2237,8 +2758,6 @@ else // ---------------------------------------------------------------------- // MHPMC5H(RW), MHPMC5(RW) // [63:32][31:0] : Hardware Performance Monitor Counter 5 - localparam MHPMC5 = 12'hB05; - localparam MHPMC5H = 12'hB85; assign mhpmc5_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC5); assign mhpmc5_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[2]) & (|(mhpmc_inc_r[2])); @@ -2255,8 +2774,6 @@ else // ---------------------------------------------------------------------- // MHPMC6H(RW), MHPMC6(RW) // [63:32][31:0] : Hardware Performance Monitor Counter 6 - localparam MHPMC6 = 12'hB06; - localparam MHPMC6H = 12'hB86; assign mhpmc6_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC6); assign mhpmc6_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[3]) & (|(mhpmc_inc_r[3])); @@ -2273,7 +2790,6 @@ else // ---------------------------------------------------------------------- // MHPME3(RW) // [9:0] : Hardware Performance Monitor Event 3 - localparam MHPME3 = 12'h323; // we only have events 0-56 with holes, 512-516, HPME* are WARL so zero otherwise. assign zero_event_r = ( (dec_csr_wrdata_r[9:0] > 10'd516) | @@ -2291,21 +2807,18 @@ else // ---------------------------------------------------------------------- // MHPME4(RW) // [9:0] : Hardware Performance Monitor Event 4 - localparam MHPME4 = 12'h324; assign wr_mhpme4_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME4); rvdffe #(10) mhpme4_ff (.*, .en(wr_mhpme4_r), .din(event_r[9:0]), .dout(mhpme4[9:0])); // ---------------------------------------------------------------------- // MHPME5(RW) // [9:0] : Hardware Performance Monitor Event 5 - localparam MHPME5 = 12'h325; assign wr_mhpme5_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME5); rvdffe #(10) mhpme5_ff (.*, .en(wr_mhpme5_r), .din(event_r[9:0]), .dout(mhpme5[9:0])); // ---------------------------------------------------------------------- // MHPME6(RW) // [9:0] : Hardware Performance Monitor Event 6 - localparam MHPME6 = 12'h326; assign wr_mhpme6_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME6); rvdffe #(10) mhpme6_ff (.*, .en(wr_mhpme6_r), .din(event_r[9:0]), .dout(mhpme6[9:0])); @@ -2315,6 +2828,22 @@ else //---------------------------------------------------------------------- // ---------------------------------------------------------------------- + // ---------------------------------------------------------------------- + // MCOUNTEREN + // [31:3] : Reserved, read 0x0 + // [2] : INSTRET user-mode access disable + // [1] : reserved, read 0x0 + // [0] : CYCLE user-mode access disable + +`ifdef RV_USER_MODE + + localparam MCOUNTEREN = 12'h306; + + assign wr_mcounteren_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCOUNTEREN); + rvdffs #(6) mcounteren_ff (.*, .clk(csr_wr_clk), .en(wr_mcounteren_r), .din({dec_csr_wrdata_r[6:2], dec_csr_wrdata_r[0]}), .dout(mcounteren)); + +`endif + // MCOUNTINHIBIT(RW) // [31:7] : Reserved, read 0x0 // [6] : HPM6 disable @@ -2325,8 +2854,6 @@ else // [1] : reserved, read 0x0 // [0] : MCYCLE disable - localparam MCOUNTINHIBIT = 12'h320; - assign wr_mcountinhibit_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCOUNTINHIBIT); rvdffs #(6) mcountinhibit_ff (.*, .clk(csr_wr_clk), .en(wr_mcountinhibit_r), .din({dec_csr_wrdata_r[6:2], dec_csr_wrdata_r[0]}), .dout({mcountinhibit[6:2], mcountinhibit[0]})); assign mcountinhibit[1] = 1'b0; @@ -2367,352 +2894,6 @@ else // CSR read mux // ---------------------------------------------------------------------- -// file "csrdecode" is human readable file that has all of the CSR decodes defined and is part of git repo -// modify this file as needed - -// to generate all the equations below from "csrdecode" except legal equation: - -// 1) coredecode -in csrdecode > corecsrdecode.e - -// 2) espresso -Dso -oeqntott corecsrdecode.e | addassign > csrequations - -// to generate the legal CSR equation below: - -// 1) coredecode -in csrdecode -legal > csrlegal.e - -// 2) espresso -Dso -oeqntott csrlegal.e | addassign > csrlegal_equation -// coredecode -in csrdecode > corecsrdecode.e; espresso -Dso -oeqntott corecsrdecode.e | addassign > csrequations; coredecode -in csrdecode -legal > csrlegal.e; espresso -Dso -oeqntott csrlegal.e | addassign > csrlegal_equation - -assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); - -assign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] - &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); - -assign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] - &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6] - &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); - -assign csr_mhartid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] - &dec_csr_rdaddr_d[2]); - -assign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]); - -assign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); - -assign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]); - -assign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]); - -assign csr_mcyclel = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] - &!dec_csr_rdaddr_d[1]); - -assign csr_mcycleh = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); - -assign csr_minstretl = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_minstreth = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1] - &dec_csr_rdaddr_d[0]); - -assign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] - &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mscause = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[2]); - -assign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[1] - &dec_csr_rdaddr_d[0]); - -assign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5] - &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); - -assign csr_dmst = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] - &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); - -assign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]); - -assign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] - &dec_csr_rdaddr_d[3]); - -assign csr_meivt = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6] - &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] - &!dec_csr_rdaddr_d[0]); - -assign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1] - &dec_csr_rdaddr_d[0]); - -assign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] - &dec_csr_rdaddr_d[2]); - -assign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] - &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); - -assign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]); - -assign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[0]); - -assign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); - -assign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]); - -assign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mtdata1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]); - -assign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5] - &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]); - -assign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[0]); - -assign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] - &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1] - &dec_csr_rdaddr_d[0]); - -assign csr_mhpmc6 = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mhpmc3h = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1] - &dec_csr_rdaddr_d[0]); - -assign csr_mhpmc4h = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] - &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mhpmc5h = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] - &dec_csr_rdaddr_d[0]); - -assign csr_mhpmc6h = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[0]); - -assign csr_mhpme4 = (dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] - &!dec_csr_rdaddr_d[0]); - -assign csr_mhpme5 = (dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] - &dec_csr_rdaddr_d[0]); - -assign csr_mhpme6 = (dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1] - &!dec_csr_rdaddr_d[0]); - -assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] - &!dec_csr_rdaddr_d[0]); - -assign csr_mitctl0 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mitctl1 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3] - &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); - -assign csr_mitb0 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); - -assign csr_mitb1 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mitcnt0 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]); - -assign csr_mitcnt1 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2] - &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); - -assign csr_mpmc = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] - &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); - -assign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] - &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_miccmect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] - &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]); - -assign csr_mdccmect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mfdht = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_mfdhs = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[0]); - -assign csr_dicawics = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] - &!dec_csr_rdaddr_d[0]); - -assign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] - &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); - -assign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4] - &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); - -assign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); - -assign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); - -assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7] - &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[5] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] - &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1] - &!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | ( - dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); - -assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] - &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]) | ( - !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] - &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7] - &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); - -assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] - &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] - &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] - &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | ( - !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] - &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( - dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] - &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] - &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] - &!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] - &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] - &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] - &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] - &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] - &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | ( - dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] - &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] - &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] - &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] - &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11] - &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] - &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] - &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( - !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] - &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] - &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] - &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11] - &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] - &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | ( - !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] - &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | ( - dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5] - &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | ( - dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5] - &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1] - &!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] - &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11] - &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] - &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | ( - !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]) | ( - !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] - &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] - &!dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] - &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] - &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | ( - dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] - &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] - &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] - &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11] - &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] - &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] - &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( - !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] - &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11] - &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] - &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | ( - !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] - &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] - &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (dec_csr_rdaddr_d[11] - &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] - &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]); - - - assign dec_tlu_presync_d = presync & dec_csr_any_unq_d & ~dec_csr_wen_unq_d; assign dec_tlu_postsync_d = postsync & dec_csr_any_unq_d; @@ -2727,12 +2908,21 @@ assign dec_csr_legal_d = ( dec_csr_any_unq_d & ~(dec_csr_wen_unq_d & (csr_mvendorid | csr_marchid | csr_mimpid | csr_mhartid | csr_mdseac | csr_meihap)) // that's not a write to a RO CSR ); // CSR read mux -assign dec_csr_rddata_d[31:0] = ( ({32{csr_misa}} & 32'h40001104) | +assign dec_csr_rddata_d[31:0] = ( +`ifdef RV_USER_MODE + ({32{csr_misa}} & 32'h40101104) | +`else + ({32{csr_misa}} & 32'h40001104) | +`endif ({32{csr_mvendorid}} & 32'h00000045) | ({32{csr_marchid}} & 32'h00000010) | ({32{csr_mimpid}} & 32'h4) | ({32{csr_mhartid}} & {core_id[31:4], 4'b0}) | - ({32{csr_mstatus}} & {19'b0, 2'b11, 3'b0, mstatus[1], 3'b0, mstatus[0], 3'b0}) | +`ifdef RV_USER_MODE + ({32{csr_mstatus}} & {14'b0, mstatus[MSTATUS_MPRV], 4'b0, ~mstatus[MSTATUS_MPP], ~mstatus[MSTATUS_MPP], 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0}) | +`else + ({32{csr_mstatus}} & {19'b0, 2'b11, 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0}) | +`endif ({32{csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]}) | ({32{csr_mip}} & {1'b0, mip[5:3], 16'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0}) | ({32{csr_mie}} & {1'b0, mie[5:3], 16'b0, mie[2], 3'b0, mie[1], 3'b0, mie[0], 3'b0}) | @@ -2780,9 +2970,29 @@ assign dec_csr_rddata_d[31:0] = ( ({32{csr_misa}} & 32'h40001104) | ({32{csr_mhpme4}} & {22'b0,mhpme4[9:0]}) | ({32{csr_mhpme5}} & {22'b0,mhpme5[9:0]}) | ({32{csr_mhpme6}} & {22'b0,mhpme6[9:0]}) | +`ifdef RV_USER_MODE + ({32{csr_menvcfg}} & 32'd0) | + ({32{csr_menvcfgh}} & 32'd0) | + ({32{csr_mcounteren}} & {25'b0, mcounteren[5:1], 1'b0, mcounteren[0]}) | + ({32{csr_cyclel}} & mcyclel[31:0]) | + ({32{csr_cycleh}} & mcycleh_inc[31:0]) | + ({32{csr_instretl}} & minstretl_read[31:0]) | + ({32{csr_instreth}} & minstreth_read[31:0]) | + ({32{csr_hpmc3}} & mhpmc3[31:0]) | + ({32{csr_hpmc4}} & mhpmc4[31:0]) | + ({32{csr_hpmc5}} & mhpmc5[31:0]) | + ({32{csr_hpmc6}} & mhpmc6[31:0]) | + ({32{csr_hpmc3h}} & mhpmc3h[31:0]) | + ({32{csr_hpmc4h}} & mhpmc4h[31:0]) | + ({32{csr_hpmc5h}} & mhpmc5h[31:0]) | + ({32{csr_hpmc6h}} & mhpmc6h[31:0]) | + ({32{csr_mseccfgl}} & {29'd0, mseccfg}) | + ({32{csr_mseccfgh}} & 32'd0) | // All bits are WPRI +`endif ({32{csr_mcountinhibit}} & {25'b0, mcountinhibit[6:0]}) | ({32{csr_mpmc}} & {30'b0, mpmc[1], 1'b0}) | - ({32{dec_timer_read_d}} & dec_timer_rddata_d[31:0]) + ({32{dec_timer_read_d}} & dec_timer_rddata_d[31:0]) | + ({32{dec_pmp_read_d}} & dec_pmp_rddata_d[31:0]) ); diff --git a/src/riscv_core/veer_el2/rtl/dmi/dmi_mux.v b/src/riscv_core/veer_el2/rtl/dmi/dmi_mux.v new file mode 100644 index 000000000..105ec7000 --- /dev/null +++ b/src/riscv_core/veer_el2/rtl/dmi/dmi_mux.v @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (c) 2023 Antmicro +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// DMI core aperture ranges from 0x00 to 0x4F. Addresses starting from 0x50 +// and above are considered uncore. + +module dmi_mux ( + + // Core access enable + input wire core_enable, + // Uncore access enable + input wire uncore_enable, + + // DMI upstream + input wire dmi_en, + input wire dmi_wr_en, + input wire [ 6:0] dmi_addr, + input wire [31:0] dmi_wdata, + output wire [31:0] dmi_rdata, + + // DMI downstream for core + output wire dmi_core_en, + output wire dmi_core_wr_en, + output wire [ 6:0] dmi_core_addr, + output wire [31:0] dmi_core_wdata, + input wire [31:0] dmi_core_rdata, + + // DMI downstream for uncore + output wire dmi_uncore_en, + output wire dmi_uncore_wr_en, + output wire [ 6:0] dmi_uncore_addr, + output wire [31:0] dmi_uncore_wdata, + input wire [31:0] dmi_uncore_rdata +); + logic is_uncore_aperture; + + // Uncore address decoder + assign is_uncore_aperture = (dmi_addr[6] & (dmi_addr[5] | dmi_addr[4])); + + // Core signals + assign dmi_core_en = dmi_en & ~is_uncore_aperture & core_enable; + assign dmi_core_wr_en = dmi_wr_en & ~is_uncore_aperture & core_enable; + assign dmi_core_addr = dmi_addr; + assign dmi_core_wdata = dmi_wdata; + + // Uncore signals + assign dmi_uncore_en = dmi_en & is_uncore_aperture & uncore_enable; + assign dmi_uncore_wr_en = dmi_wr_en & is_uncore_aperture & uncore_enable; + assign dmi_uncore_addr = dmi_addr; + assign dmi_uncore_wdata = dmi_wdata; + + // Read mux + assign dmi_rdata = is_uncore_aperture ? dmi_uncore_rdata : dmi_core_rdata; + +endmodule diff --git a/src/riscv_core/veer_el2/rtl/el2_mem.sv b/src/riscv_core/veer_el2/rtl/el2_mem.sv index fa3fbf9da..48d04d366 100644 --- a/src/riscv_core/veer_el2/rtl/el2_mem.sv +++ b/src/riscv_core/veer_el2/rtl/el2_mem.sv @@ -1,6 +1,7 @@ //******************************************************************************** // SPDX-License-Identifier: Apache-2.0 // Copyright 2020 Western Digital Corporation or its affiliates. +// Copyright (c) 2023 Antmicro // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -41,6 +42,7 @@ import el2_pkg::*; output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, + //ICCM ports input logic [pt.ICCM_BITS-1:1] iccm_rw_addr, input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle @@ -60,6 +62,8 @@ import el2_pkg::*; input logic ic_rd_en, input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic ic_sel_premux_data, // Premux data sel + input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, + input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC input logic [70:0] ic_debug_wr_data, // Debug wr cache. @@ -81,15 +85,15 @@ import el2_pkg::*; el2_mem_if.veer_sram_src mem_export, - input logic scan_mode ); logic active_clk; - el2_mem_if mem_export_local (); rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* ); + el2_mem_if mem_export_local (); + assign mem_export .clk = clk; assign mem_export_local.clk = clk; @@ -97,13 +101,17 @@ import el2_pkg::*; assign mem_export .iccm_wren_bank = mem_export_local.iccm_wren_bank; assign mem_export .iccm_addr_bank = mem_export_local.iccm_addr_bank; assign mem_export .iccm_bank_wr_data = mem_export_local.iccm_bank_wr_data; + assign mem_export .iccm_bank_wr_ecc = mem_export_local.iccm_bank_wr_ecc; assign mem_export_local.iccm_bank_dout = mem_export. iccm_bank_dout; + assign mem_export_local.iccm_bank_ecc = mem_export. iccm_bank_ecc; assign mem_export .dccm_clken = mem_export_local.dccm_clken; assign mem_export .dccm_wren_bank = mem_export_local.dccm_wren_bank; assign mem_export .dccm_addr_bank = mem_export_local.dccm_addr_bank; assign mem_export .dccm_wr_data_bank = mem_export_local.dccm_wr_data_bank; + assign mem_export .dccm_wr_ecc_bank = mem_export_local.dccm_wr_ecc_bank; assign mem_export_local.dccm_bank_dout = mem_export .dccm_bank_dout; + assign mem_export_local.dccm_bank_ecc = mem_export .dccm_bank_ecc; // DCCM Instantiation if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable diff --git a/src/riscv_core/veer_el2/rtl/el2_param.vh b/src/riscv_core/veer_el2/rtl/el2_param.vh index fe5735f99..eab3a4837 100644 --- a/src/riscv_core/veer_el2/rtl/el2_param.vh +++ b/src/riscv_core/veer_el2/rtl/el2_param.vh @@ -130,6 +130,7 @@ parameter el2_param_t pt = '{ ICCM_BANK_HI : 9'h003 , ICCM_BANK_INDEX_LO : 9'h004 , ICCM_BITS : 9'h011 , + ICCM_ECC_WIDTH : 7'h07 , ICCM_ENABLE : 5'h01 , ICCM_ICACHE : 5'h00 , ICCM_INDEX_BITS : 8'h0D , @@ -183,10 +184,13 @@ parameter el2_param_t pt = '{ PIC_SIZE : 13'h0020 , PIC_TOTAL_INT : 12'h01F , PIC_TOTAL_INT_PLUS1 : 13'h0020 , + PMP_ENTRIES : 11'h040 , RET_STACK_SIZE : 8'h08 , SB_BUS_ID : 5'h01 , SB_BUS_PRTY : 6'h02 , SB_BUS_TAG : 8'h01 , - TIMER_LEGAL_EN : 5'h01 + SMEPMP : 1'h1 , + TIMER_LEGAL_EN : 5'h01 , + USER_MODE : 1'h1 } -// parameter el2_param_t pt = 2271'h04840400010040010840000020908200002840004808220A0C848200060410C00000000000000000000000000000000000000000000000000000000000000000000000000000000003FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC104420401C21386810141400000000800820428042010840830C2010281840200081002008E0C0801004040800C01002100400606810104100C0811080340810404000000002002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF8001080C080822080003000000003C041804003E02008084021 +// parameter el2_param_t pt = 2291'h04840400010040010840000020908200002840004808220A0C848200060410C00000000000000000000000000000000000000000000000000000000000000000000000000000000003FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC104420401C21386810141400000000800820428042010840830C2010281840200081002008E0C0801004040800C01002100400606810104100C08110E10068102080800000000400420300000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF000210181010441000060000000078083008007C040100202100C3 diff --git a/src/riscv_core/veer_el2/rtl/el2_pdef.vh b/src/riscv_core/veer_el2/rtl/el2_pdef.vh index b41d35c3d..bdbb9acda 100644 --- a/src/riscv_core/veer_el2/rtl/el2_pdef.vh +++ b/src/riscv_core/veer_el2/rtl/el2_pdef.vh @@ -131,6 +131,7 @@ typedef struct packed { logic [8:0] ICCM_BANK_HI; logic [8:0] ICCM_BANK_INDEX_LO; logic [8:0] ICCM_BITS; + logic [6:0] ICCM_ECC_WIDTH; logic [4:0] ICCM_ENABLE; logic [4:0] ICCM_ICACHE; logic [7:0] ICCM_INDEX_BITS; @@ -184,10 +185,13 @@ typedef struct packed { logic [12:0] PIC_SIZE; logic [11:0] PIC_TOTAL_INT; logic [12:0] PIC_TOTAL_INT_PLUS1; + logic [10:0] PMP_ENTRIES; logic [7:0] RET_STACK_SIZE; logic [4:0] SB_BUS_ID; logic [5:0] SB_BUS_PRTY; logic [7:0] SB_BUS_TAG; + logic SMEPMP; logic [4:0] TIMER_LEGAL_EN; + logic USER_MODE; } el2_param_t; diff --git a/src/riscv_core/veer_el2/rtl/el2_pmp.sv b/src/riscv_core/veer_el2/rtl/el2_pmp.sv new file mode 100644 index 000000000..502b11f93 --- /dev/null +++ b/src/riscv_core/veer_el2/rtl/el2_pmp.sv @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright lowRISC contributors. +// Copyright 2023 Antmicro, Ltd. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module el2_pmp + import el2_pkg::*; +#( + parameter PMP_CHANNELS = 3, + // Granularity of NAPOT access, + // 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc. + parameter PMP_GRANULARITY = 0, // TODO: Move to veer.config + `include "el2_param.vh" +) ( + input logic clk, // Top level clock + input logic rst_l, // Reset + /* verilator coverage_off */ + input logic scan_mode, // Scan mode + /* verilator coverage_on */ + +`ifdef RV_SMEPMP + input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits +`endif + +`ifdef RV_USER_MODE + input logic priv_mode_ns, // operating privilege mode (next clock cycle) + input logic priv_mode_eff, // operating effective privilege mode +`endif + + input el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES], + input logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES], + + input logic [31:0] pmp_chan_addr[PMP_CHANNELS], + input el2_pmp_type_pkt_t pmp_chan_type[PMP_CHANNELS], + output logic pmp_chan_err [PMP_CHANNELS] +); + + logic [ 33:0] csr_pmp_addr_i [pt.PMP_ENTRIES]; + logic [ 33:0] pmp_req_addr_i [ PMP_CHANNELS]; + + logic [ 33:0] region_start_addr [pt.PMP_ENTRIES]; + logic [33:PMP_GRANULARITY+2] region_addr_mask [pt.PMP_ENTRIES]; + logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_gt; + logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_lt; + logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_eq; + logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_all; + logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_basic_perm_check; + logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check; + +`ifdef RV_USER_MODE + logic any_region_enabled; +`endif + + /////////////////////// + // Functions for PMP // + /////////////////////// + + // Flow of the PMP checking operation follows as below + // + // basic_perm_check ---> perm_check_wrapper ---> orig_perm_check ---/ + // | + // region_match_all -----------------> access_fault_check <---------- + // | + // \--> pmp_chan_err + + // A wrapper function in which it is decided which form of permission check function gets called + function automatic logic perm_check_wrapper(el2_mseccfg_pkt_t csr_pmp_mseccfg, + el2_pmp_cfg_pkt_t csr_pmp_cfg, + el2_pmp_type_pkt_t req_type, + logic priv_mode, + logic permission_check); + + return csr_pmp_mseccfg.MML ? mml_perm_check(csr_pmp_cfg, + req_type, + priv_mode, + permission_check) : + orig_perm_check(csr_pmp_cfg.lock, + priv_mode, + permission_check); + endfunction + + // Compute permissions checks that apply when MSECCFG.MML is set. Added for Smepmp support. + function automatic logic mml_perm_check(el2_pmp_cfg_pkt_t csr_pmp_cfg, + el2_pmp_type_pkt_t pmp_req_type, + logic priv_mode, + logic permission_check); + logic result; + logic unused_cfg = |csr_pmp_cfg.mode; + + if (!csr_pmp_cfg.read && csr_pmp_cfg.write) begin + // Special-case shared regions where R = 0, W = 1 + unique case ({csr_pmp_cfg.lock, csr_pmp_cfg.execute}) + // Read/write in M, read only in U + 2'b00: result = + (pmp_req_type == READ) | + ((pmp_req_type == WRITE) & ~priv_mode); + // Read/write in M/U + 2'b01: result = + (pmp_req_type == READ) | + (pmp_req_type == WRITE); + // Execute only on M/U + 2'b10: result = (pmp_req_type == EXEC); + // Read/execute in M, execute only on U + 2'b11: result = + (pmp_req_type == EXEC) | + ((pmp_req_type == READ) & ~priv_mode); + /* verilator coverage_off */ + default: ; + /* verilator coverage_on */ + endcase + end else begin + if (csr_pmp_cfg.read & csr_pmp_cfg.write & csr_pmp_cfg.execute & csr_pmp_cfg.lock) begin + // Special-case shared read only region when R = 1, W = 1, X = 1, L = 1 + result = (pmp_req_type == READ); + end else begin + // Otherwise use basic permission check. Permission is always denied if in U mode and + // L is set or if in M mode and L is unset. + result = permission_check & (priv_mode ? ~csr_pmp_cfg.lock : csr_pmp_cfg.lock); + end + end + return result; + endfunction + + // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP + // behaviour before Smepmp was added. + function automatic logic orig_perm_check(logic pmp_cfg_lock, + logic priv_mode, + logic permission_check); + // For M-mode, any region which matches with the L-bit clear, or with sufficient + // access permissions will be allowed. + // For other modes, the lock bit doesn't matter + return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check); + endfunction + + // Access fault determination / prioritization + function automatic logic access_fault_check(el2_mseccfg_pkt_t csr_pmp_mseccfg, + el2_pmp_type_pkt_t req_type, + logic [pt.PMP_ENTRIES-1:0] match_all, + logic any_region_enabled, + logic priv_mode, + logic [pt.PMP_ENTRIES-1:0] final_perm_check); + +`ifdef RV_USER_MODE + `ifdef RV_SMEPMP + // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other + // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC. + logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode | + (csr_pmp_mseccfg.MML && (req_type == EXEC)); + `else + // When in user mode and at least one PMP region is enabled deny access by default. + logic access_fail = any_region_enabled & priv_mode; + `endif +`else + logic access_fail = 1'b0; +`endif + + logic matched = 1'b0; + + // PMP entries are statically prioritized, from 0 to N-1 + // The lowest-numbered PMP entry which matches an address determines accessibility + for (int r = 0; r < pt.PMP_ENTRIES; r++) begin + if (!matched && match_all[r]) begin + access_fail = ~final_perm_check[r]; + matched = 1'b1; + end + end + return access_fail; + endfunction + + // --------------- + // Access checking + // --------------- + +`ifdef RV_USER_MODE + logic [pt.PMP_ENTRIES-1:0] region_enabled; + for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_reg_ena + assign region_enabled[r] = pmp_pmpcfg[r].mode != OFF; + end + assign any_region_enabled = |region_enabled; +`endif + + for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_addr_exp + assign csr_pmp_addr_i[r] = { + pmp_pmpaddr[r], 2'b00 + }; // addr conv.: word @ 32-bit -> byte @ 34-bit + // Start address for TOR matching + if (r == 0) begin : g_entry0 + assign region_start_addr[r] = (pmp_pmpcfg[r].mode == TOR) ? 34'h000000000 : csr_pmp_addr_i[r]; + end else begin : g_oth + assign region_start_addr[r] = (pmp_pmpcfg[r].mode == TOR) ? csr_pmp_addr_i[r-1] : + csr_pmp_addr_i[r]; + end + // Address mask for NA matching + for (genvar b = PMP_GRANULARITY + 2; b < 34; b++) begin : g_bitmask + if (b == 2) begin : g_bit0 + // Always mask bit 2 for NAPOT + assign region_addr_mask[r][b] = (pmp_pmpcfg[r].mode != NAPOT); + end else begin : g_others + // We will mask this bit if it is within the programmed granule + // i.e. addr = yyyy 0111 + // ^ + // | This bit pos is the top of the mask, all lower bits set + // thus mask = 1111 0000 + if (PMP_GRANULARITY == 0) begin : g_region_addr_mask_zero_granularity + assign region_addr_mask[r][b] = (pmp_pmpcfg[r].mode != NAPOT) | + ~&csr_pmp_addr_i[r][b-1:2]; + end else begin : g_region_addr_mask_other_granularity + assign region_addr_mask[r][b] = (pmp_pmpcfg[r].mode != NAPOT) | + ~&csr_pmp_addr_i[r][b-1:PMP_GRANULARITY+1]; + end + end + end + end + +`ifdef RV_USER_MODE + logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff; + for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_priv_mode_eff + assign pmp_priv_mode_eff[c] = ( + ((pmp_chan_type[c] == EXEC) & priv_mode_ns) | + ((pmp_chan_type[c] != EXEC) & priv_mode_eff)); // RW affected by mstatus.MPRV + end +`endif + + for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_access_check + assign pmp_req_addr_i[c] = {2'b00, pmp_chan_addr[c]}; // addr. widening: 32-bit -> 34-bit + for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions + // Comparators are sized according to granularity + assign region_match_eq[c][r] = (pmp_req_addr_i[c][33:PMP_GRANULARITY+2] & + region_addr_mask[r]) == + (region_start_addr[r][33:PMP_GRANULARITY+2] & + region_addr_mask[r]); + assign region_match_gt[c][r] = pmp_req_addr_i[c][33:PMP_GRANULARITY+2] > + region_start_addr[r][33:PMP_GRANULARITY+2]; + assign region_match_lt[c][r] = pmp_req_addr_i[c][33:PMP_GRANULARITY+2] < + csr_pmp_addr_i[r][33:PMP_GRANULARITY+2]; + + always_comb begin + region_match_all[c][r] = 1'b0; + unique case (pmp_pmpcfg[r].mode) + OFF: region_match_all[c][r] = 1'b0; + NA4: region_match_all[c][r] = region_match_eq[c][r]; + NAPOT: region_match_all[c][r] = region_match_eq[c][r]; + TOR: begin + region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) & + region_match_lt[c][r]; + end + default: region_match_all[c][r] = 1'b0; + endcase + end + + // Basic permission check compares cfg register only. + assign region_basic_perm_check[c][r] = + ((pmp_chan_type[c] == EXEC) & pmp_pmpcfg[r].execute) | + ((pmp_chan_type[c] == WRITE) & pmp_pmpcfg[r].write) | + ((pmp_chan_type[c] == READ) & pmp_pmpcfg[r].read); + + // Check specific required permissions since the behaviour is different + // between Smepmp implementation and original PMP. + assign region_perm_check[c][r] = perm_check_wrapper( +`ifdef RV_SMEPMP + mseccfg, +`else + 3'b000, +`endif + pmp_pmpcfg[r], + pmp_chan_type[c], +`ifdef RV_USER_MODE + pmp_priv_mode_eff[c], +`else + 1'b0, +`endif + region_basic_perm_check[c][r] + ); + + // Address bits below PMP granularity (which starts at 4 byte) are deliberately unused. + logic unused_sigs; + assign unused_sigs = ^{region_start_addr[r][PMP_GRANULARITY+2-1:0], + pmp_req_addr_i[c][PMP_GRANULARITY+2-1:0]}; + end + + // Once the permission checks of the regions are done, decide if the access is + // denied by figuring out the matching region and its permission check. + assign pmp_chan_err[c] = access_fault_check( +`ifdef RV_SMEPMP + mseccfg, +`else + 3'b000, +`endif + pmp_chan_type[c], + region_match_all[c], +`ifdef RV_USER_MODE + any_region_enabled, + pmp_priv_mode_eff[c], +`else + 1'b0, + 1'b0, +`endif + region_perm_check[c]); + + end + +endmodule // el2_pmp diff --git a/src/riscv_core/veer_el2/rtl/el2_veer.sv b/src/riscv_core/veer_el2/rtl/el2_veer.sv index 39590a63e..de7fe13c5 100644 --- a/src/riscv_core/veer_el2/rtl/el2_veer.sv +++ b/src/riscv_core/veer_el2/rtl/el2_veer.sv @@ -134,13 +134,22 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, output logic [31:0] lsu_axi_awaddr, output logic [3:0] lsu_axi_awregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_awsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_awburst, output logic lsu_axi_awlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_awcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_awprot, output logic [3:0] lsu_axi_awqos, + /*verilator coverage_on*/ output logic lsu_axi_wvalid, input logic lsu_axi_wready, @@ -149,7 +158,10 @@ import el2_pkg::*; output logic lsu_axi_wlast, input logic lsu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] lsu_axi_bresp, input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, @@ -159,16 +171,28 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, output logic [31:0] lsu_axi_araddr, output logic [3:0] lsu_axi_arregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_arsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_arburst, output logic lsu_axi_arlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_arcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_arprot, output logic [3:0] lsu_axi_arqos, + /*verilator coverage_on*/ input logic lsu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_rready, + /*verilator coverage_on*/ input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid, input logic [63:0] lsu_axi_rdata, input logic [1:0] lsu_axi_rresp, @@ -176,8 +200,13 @@ import el2_pkg::*; //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_awvalid, + /*verilator coverage_on*/ input logic ifu_axi_awready, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid, output logic [31:0] ifu_axi_awaddr, output logic [3:0] ifu_axi_awregion, @@ -190,13 +219,20 @@ import el2_pkg::*; output logic [3:0] ifu_axi_awqos, output logic ifu_axi_wvalid, + /*verilator coverage_on*/ input logic ifu_axi_wready, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [63:0] ifu_axi_wdata, output logic [7:0] ifu_axi_wstrb, output logic ifu_axi_wlast, + /*verilator coverage_on*/ input logic ifu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] ifu_axi_bresp, input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid, @@ -206,6 +242,8 @@ import el2_pkg::*; output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid, output logic [31:0] ifu_axi_araddr, output logic [3:0] ifu_axi_arregion, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [7:0] ifu_axi_arlen, output logic [2:0] ifu_axi_arsize, output logic [1:0] ifu_axi_arburst, @@ -213,9 +251,13 @@ import el2_pkg::*; output logic [3:0] ifu_axi_arcache, output logic [2:0] ifu_axi_arprot, output logic [3:0] ifu_axi_arqos, + /*verilator coverage_on*/ input logic ifu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_rready, + /*verilator coverage_on*/ input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid, input logic [63:0] ifu_axi_rdata, input logic [1:0] ifu_axi_rresp, @@ -225,16 +267,25 @@ import el2_pkg::*; // AXI Write Channels output logic sb_axi_awvalid, input logic sb_axi_awready, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid, + /*verilator coverage_on*/ output logic [31:0] sb_axi_awaddr, output logic [3:0] sb_axi_awregion, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [7:0] sb_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] sb_axi_awsize, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [1:0] sb_axi_awburst, output logic sb_axi_awlock, output logic [3:0] sb_axi_awcache, output logic [2:0] sb_axi_awprot, output logic [3:0] sb_axi_awqos, + /*verilator coverage_on*/ output logic sb_axi_wvalid, input logic sb_axi_wready, @@ -250,19 +301,31 @@ import el2_pkg::*; // AXI Read Channels output logic sb_axi_arvalid, input logic sb_axi_arready, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid, + /*verilator coverage_on*/ output logic [31:0] sb_axi_araddr, output logic [3:0] sb_axi_arregion, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [7:0] sb_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] sb_axi_arsize, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [1:0] sb_axi_arburst, output logic sb_axi_arlock, output logic [3:0] sb_axi_arcache, output logic [2:0] sb_axi_arprot, output logic [3:0] sb_axi_arqos, + /*verilator coverage_on*/ input logic sb_axi_rvalid, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic sb_axi_rready, + /*verilator coverage_on*/ input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid, input logic [63:0] sb_axi_rdata, input logic [1:0] sb_axi_rresp, @@ -311,8 +374,11 @@ import el2_pkg::*; //// AHB LITE BUS output logic [31:0] haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] hburst, output logic hmastlock, + /*verilator coverage_on*/ output logic [3:0] hprot, output logic [2:0] hsize, output logic [1:0] htrans, @@ -324,8 +390,11 @@ import el2_pkg::*; // LSU AHB Master output logic [31:0] lsu_haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_hburst, output logic lsu_hmastlock, + /*verilator coverage_on*/ output logic [3:0] lsu_hprot, output logic [2:0] lsu_hsize, output logic [1:0] lsu_htrans, @@ -338,8 +407,11 @@ import el2_pkg::*; //System Bus Debug Master output logic [31:0] sb_haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] sb_hburst, output logic sb_hmastlock, + /*verilator coverage_on*/ output logic [3:0] sb_hprot, output logic [2:0] sb_hsize, output logic [1:0] sb_htrans, @@ -377,11 +449,11 @@ import el2_pkg::*; input logic [31:0] dmi_reg_wdata, // write data output logic [31:0] dmi_reg_rdata, - // Caliptra ECC status signals - output logic cptra_iccm_ecc_single_error, - output logic cptra_iccm_ecc_double_error, - output logic cptra_dccm_ecc_single_error, - output logic cptra_dccm_ecc_double_error, + // ICCM/DCCM ECC status + output logic iccm_ecc_single_error, + output logic iccm_ecc_double_error, + output logic dccm_ecc_single_error, + output logic dccm_ecc_double_error, input logic [pt.PIC_TOTAL_INT:1] extintsrc_req, input logic timer_int, @@ -399,9 +471,11 @@ import el2_pkg::*; logic ifu_pmu_instr_aligned; logic ifu_ic_error_start; + logic ifu_iccm_dma_rd_ecc_single_err; logic ifu_iccm_rd_ecc_single_err; - logic cptra_iccm_dma_rd_ecc_single_err; - logic cptra_iccm_rd_ecc_double_err; + logic ifu_iccm_rd_ecc_double_err; + logic lsu_dccm_rd_ecc_single_err; + logic lsu_dccm_rd_ecc_double_err; logic lsu_axi_awready_ahb; logic lsu_axi_wready_ahb; @@ -482,25 +556,40 @@ import el2_pkg::*; logic sb_axi_rlast_int; logic dma_axi_awvalid_ahb; + /* exclude signals that are tied to constant value in ahb_to_axi4.sv */ + /*verilator coverage_off*/ logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_ahb; + /*verilator coverage_on*/ logic [31:0] dma_axi_awaddr_ahb; logic [2:0] dma_axi_awsize_ahb; + /* exclude signals that are tied to constant value in ahb_to_axi4.sv */ + /*verilator coverage_off*/ logic [2:0] dma_axi_awprot_ahb; logic [7:0] dma_axi_awlen_ahb; logic [1:0] dma_axi_awburst_ahb; + /*verilator coverage_on*/ logic dma_axi_wvalid_ahb; logic [63:0] dma_axi_wdata_ahb; logic [7:0] dma_axi_wstrb_ahb; + /* exclude signals that are tied to constant value in ahb_to_axi4.sv */ + /*verilator coverage_off*/ logic dma_axi_wlast_ahb; logic dma_axi_bready_ahb; + /*verilator coverage_on*/ logic dma_axi_arvalid_ahb; + /* exclude signals that are tied to constant value in ahb_to_axi4.sv */ + /*verilator coverage_off*/ logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid_ahb; + /*verilator coverage_on*/ logic [31:0] dma_axi_araddr_ahb; logic [2:0] dma_axi_arsize_ahb; + /* exclude signals that are tied to constant value in ahb_to_axi4.sv */ + /*verilator coverage_off*/ logic [2:0] dma_axi_arprot_ahb; logic [7:0] dma_axi_arlen_ahb; logic [1:0] dma_axi_arburst_ahb; logic dma_axi_rready_ahb; + /*verilator coverage_on*/ logic dma_axi_awvalid_int; logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_int; @@ -734,6 +823,22 @@ import el2_pkg::*; assign dccm_clk_override = dec_tlu_dccm_clk_override; // dccm memory assign icm_clk_override = dec_tlu_icm_clk_override; // icache/iccm memory + // PMP Signals + el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES]; + logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES]; + logic [31:0] pmp_chan_addr [3]; + el2_pmp_type_pkt_t pmp_chan_type [3]; + logic pmp_chan_err [3]; + + logic [31:1] ifu_pmp_addr; + logic ifu_pmp_error; + logic [31:0] lsu_pmp_addr_start; + logic lsu_pmp_error_start; + logic [31:0] lsu_pmp_addr_end; + logic lsu_pmp_error_end; + logic lsu_pmp_we; + logic lsu_pmp_re; + // -----------------------DEBUG START ------------------------------- logic [31:0] dbg_cmd_addr; // the address of the debug command to used by the core @@ -866,6 +971,19 @@ import el2_pkg::*; assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode); +`ifdef RV_USER_MODE + + // Operating privilege mode, 0 - machine, 1 - user + logic priv_mode; + // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv) + logic priv_mode_eff; + // Next privilege mode + logic priv_mode_ns; + + el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP + +`endif + // fetch el2_ifu #(.pt(pt)) ifu ( .clk(active_l2clk), @@ -885,10 +1003,11 @@ import el2_pkg::*; .* ); - assign cptra_iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err || cptra_iccm_dma_rd_ecc_single_err; - assign cptra_iccm_ecc_double_error = cptra_iccm_rd_ecc_double_err; + assign iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err || ifu_iccm_dma_rd_ecc_single_err; + assign iccm_ecc_double_error = ifu_iccm_rd_ecc_double_err; + el2_dec #(.pt(pt)) dec ( .clk(active_l2clk), .dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]), @@ -926,6 +1045,8 @@ import el2_pkg::*; ); + assign dccm_ecc_single_error = lsu_dccm_rd_ecc_single_err; + assign dccm_ecc_double_error = lsu_dccm_rd_ecc_double_err; el2_pic_ctrl #(.pt(pt)) pic_ctrl_inst ( .clk(free_l2clk), @@ -964,6 +1085,25 @@ import el2_pkg::*; .* ); + assign pmp_chan_addr[0] = {ifu_pmp_addr, 1'b0}; + assign pmp_chan_type[0] = EXEC; + assign ifu_pmp_error = pmp_chan_err[0]; + assign pmp_chan_addr[1] = lsu_pmp_addr_start; + assign pmp_chan_type[1] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE); + assign lsu_pmp_error_start = pmp_chan_err[1]; + assign pmp_chan_addr[2] = lsu_pmp_addr_end; + assign pmp_chan_type[2] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE); + assign lsu_pmp_error_end = pmp_chan_err[2]; + + el2_pmp #( + .PMP_CHANNELS(3), + .pt(pt) + ) pmp ( + .clk (active_l2clk), + .rst_l(core_rst_l), + .* + ); + if (pt.BUILD_AHB_LITE == 1) begin: Gen_AXI_To_AHB // AXI4 -> AHB Gasket for LSU diff --git a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv old mode 100755 new mode 100644 index be7cc84da..3d6e179c2 --- a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv +++ b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv @@ -1,5 +1,6 @@ // SPDX-License-Identifier: Apache-2.0 // Copyright 2020 Western Digital Corporation or its affiliates. +// Copyright (c) 2023 Antmicro // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -22,7 +23,6 @@ //******************************************************************************** module el2_veer_wrapper import el2_pkg::*; -import soc_ifc_pkg::*; #( `include "el2_param.vh" ) @@ -52,13 +52,22 @@ import soc_ifc_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, output logic [31:0] lsu_axi_awaddr, output logic [3:0] lsu_axi_awregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_awsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_awburst, output logic lsu_axi_awlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_awcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_awprot, output logic [3:0] lsu_axi_awqos, + /*verilator coverage_on*/ output logic lsu_axi_wvalid, input logic lsu_axi_wready, @@ -67,7 +76,10 @@ import soc_ifc_pkg::*; output logic lsu_axi_wlast, input logic lsu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] lsu_axi_bresp, input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, @@ -77,16 +89,28 @@ import soc_ifc_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, output logic [31:0] lsu_axi_araddr, output logic [3:0] lsu_axi_arregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_arsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_arburst, output logic lsu_axi_arlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_arcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_arprot, output logic [3:0] lsu_axi_arqos, + /*verilator coverage_on*/ input logic lsu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_rready, + /*verilator coverage_on*/ input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid, input logic [63:0] lsu_axi_rdata, input logic [1:0] lsu_axi_rresp, @@ -94,8 +118,13 @@ import soc_ifc_pkg::*; //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_awvalid, + /*verilator coverage_on*/ input logic ifu_axi_awready, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid, output logic [31:0] ifu_axi_awaddr, output logic [3:0] ifu_axi_awregion, @@ -108,13 +137,20 @@ import soc_ifc_pkg::*; output logic [3:0] ifu_axi_awqos, output logic ifu_axi_wvalid, + /*verilator coverage_on*/ input logic ifu_axi_wready, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [63:0] ifu_axi_wdata, output logic [7:0] ifu_axi_wstrb, output logic ifu_axi_wlast, + /*verilator coverage_on*/ input logic ifu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] ifu_axi_bresp, input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid, @@ -124,6 +160,8 @@ import soc_ifc_pkg::*; output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid, output logic [31:0] ifu_axi_araddr, output logic [3:0] ifu_axi_arregion, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [7:0] ifu_axi_arlen, output logic [2:0] ifu_axi_arsize, output logic [1:0] ifu_axi_arburst, @@ -131,9 +169,13 @@ import soc_ifc_pkg::*; output logic [3:0] ifu_axi_arcache, output logic [2:0] ifu_axi_arprot, output logic [3:0] ifu_axi_arqos, + /*verilator coverage_on*/ input logic ifu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_rready, + /*verilator coverage_on*/ input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid, input logic [63:0] ifu_axi_rdata, input logic [1:0] ifu_axi_rresp, @@ -143,16 +185,25 @@ import soc_ifc_pkg::*; // AXI Write Channels output logic sb_axi_awvalid, input logic sb_axi_awready, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid, + /*verilator coverage_on*/ output logic [31:0] sb_axi_awaddr, output logic [3:0] sb_axi_awregion, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [7:0] sb_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] sb_axi_awsize, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [1:0] sb_axi_awburst, output logic sb_axi_awlock, output logic [3:0] sb_axi_awcache, output logic [2:0] sb_axi_awprot, output logic [3:0] sb_axi_awqos, + /*verilator coverage_on*/ output logic sb_axi_wvalid, input logic sb_axi_wready, @@ -168,19 +219,31 @@ import soc_ifc_pkg::*; // AXI Read Channels output logic sb_axi_arvalid, input logic sb_axi_arready, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid, + /*verilator coverage_on*/ output logic [31:0] sb_axi_araddr, output logic [3:0] sb_axi_arregion, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [7:0] sb_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] sb_axi_arsize, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [1:0] sb_axi_arburst, output logic sb_axi_arlock, output logic [3:0] sb_axi_arcache, output logic [2:0] sb_axi_arprot, output logic [3:0] sb_axi_arqos, + /*verilator coverage_on*/ input logic sb_axi_rvalid, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic sb_axi_rready, + /*verilator coverage_on*/ input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid, input logic [63:0] sb_axi_rdata, input logic [1:0] sb_axi_rresp, @@ -190,7 +253,10 @@ import soc_ifc_pkg::*; // AXI Write Channels input logic dma_axi_awvalid, output logic dma_axi_awready, + /* exclude signals that are tied to constant value in tb_top.sv */ + /*verilator coverage_off*/ input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid, + /*verilator coverage_on*/ input logic [31:0] dma_axi_awaddr, input logic [2:0] dma_axi_awsize, input logic [2:0] dma_axi_awprot, @@ -212,7 +278,10 @@ import soc_ifc_pkg::*; // AXI Read Channels input logic dma_axi_arvalid, output logic dma_axi_arready, + /* exclude signals that are tied to constant value in tb_top.sv */ + /*verilator coverage_off*/ input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid, + /*verilator coverage_on*/ input logic [31:0] dma_axi_araddr, input logic [2:0] dma_axi_arsize, input logic [2:0] dma_axi_arprot, @@ -230,45 +299,65 @@ import soc_ifc_pkg::*; `ifdef RV_BUILD_AHB_LITE //// AHB LITE BUS output logic [31:0] haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] hburst, output logic hmastlock, + /*verilator coverage_on*/ output logic [3:0] hprot, output logic [2:0] hsize, output logic [1:0] htrans, output logic hwrite, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ input logic [63:0] hrdata, input logic hready, input logic hresp, + /*verilator coverage_on*/ // LSU AHB Master output logic [31:0] lsu_haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_hburst, output logic lsu_hmastlock, + /*verilator coverage_on*/ output logic [3:0] lsu_hprot, output logic [2:0] lsu_hsize, output logic [1:0] lsu_htrans, output logic lsu_hwrite, output logic [63:0] lsu_hwdata, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ input logic [63:0] lsu_hrdata, input logic lsu_hready, input logic lsu_hresp, + /*verilator coverage_on*/ // Debug Syster Bus AHB output logic [31:0] sb_haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] sb_hburst, output logic sb_hmastlock, + /*verilator coverage_on*/ output logic [3:0] sb_hprot, output logic [2:0] sb_hsize, output logic [1:0] sb_htrans, output logic sb_hwrite, output logic [63:0] sb_hwdata, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ input logic [63:0] sb_hrdata, input logic sb_hready, input logic sb_hresp, + /*verilator coverage_on*/ // DMA Slave + /* exclude signals that are tied to constant value in tb_top.sv */ + /*verilator coverage_off*/ input logic dma_hsel, input logic [31:0] dma_haddr, input logic [2:0] dma_hburst, @@ -278,6 +367,7 @@ import soc_ifc_pkg::*; input logic [1:0] dma_htrans, input logic dma_hwrite, input logic [63:0] dma_hwdata, + /*verilator coverage_on*/ input logic dma_hreadyin, output logic [63:0] dma_hrdata, @@ -290,6 +380,17 @@ import soc_ifc_pkg::*; input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface + // ICCM/DCCM ECC status + output logic iccm_ecc_single_error, + output logic iccm_ecc_double_error, + output logic dccm_ecc_single_error, + output logic dccm_ecc_double_error, + + // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not) + + input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, + input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, + input logic timer_int, input logic soft_int, input logic [pt.PIC_TOTAL_INT:1] extintsrc_req, @@ -307,26 +408,11 @@ import soc_ifc_pkg::*; output logic jtag_tdo, // JTAG TDO output logic jtag_tdoEn, // JTAG Test Data Output enable - //caliptra uncore jtag ports - output logic cptra_uncore_dmi_reg_en, - output logic cptra_uncore_dmi_reg_wr_en, - input logic [31:0] cptra_uncore_dmi_reg_rdata, - output logic [6:0] cptra_uncore_dmi_reg_addr, - output logic [31:0] cptra_uncore_dmi_reg_wdata, - input security_state_t cptra_security_state_Latched, - output logic cptra_dmi_reg_en_preQ, - input logic [31:4] core_id, - // Caliptra Memory Export Interface + // Memory Export Interface el2_mem_if.veer_sram_src el2_mem_export, - // Caliptra ECC status signals - output logic cptra_iccm_ecc_single_error, - output logic cptra_iccm_ecc_double_error, - output logic cptra_dccm_ecc_single_error, - output logic cptra_dccm_ecc_double_error, - // external MPC halt/run interface input logic mpc_debug_halt_req, // Async halt request input logic mpc_debug_run_req, // Async run request @@ -341,8 +427,22 @@ import soc_ifc_pkg::*; output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request input logic i_cpu_run_req, // Async restart req to CPU output logic o_cpu_run_ack, // Core response to run req + + /* exclude signals that are tied to constant value or left unconnected in tb_top.sv */ + /* verilator coverage_off */ input logic scan_mode, // To enable scan mode - input logic mbist_mode // to enable mbist + input logic mbist_mode, // to enable mbist + + // DMI port for uncore + input logic dmi_core_enable, + input logic dmi_uncore_enable, + output logic dmi_uncore_en, + output logic dmi_uncore_wr_en, + output logic [ 6:0] dmi_uncore_addr, + output logic [31:0] dmi_uncore_wdata, + input logic [31:0] dmi_uncore_rdata, + output logic dmi_active + /* verilator coverage_on */ ); logic active_l2clk; @@ -413,6 +513,8 @@ import soc_ifc_pkg::*; // zero out the signals not presented at the wrapper instantiation level `ifdef RV_BUILD_AXI4 + // Since all the signals in this block are tied to constant, we exclude this from coverage analysis + /*verilator coverage_off*/ //// AHB LITE BUS logic [31:0] haddr; @@ -497,10 +599,14 @@ import soc_ifc_pkg::*; assign dma_hwdata[63:0] = '0; assign dma_hreadyin = '0; + /*verilator coverage_on*/ + `endif // `ifdef RV_BUILD_AXI4 `ifdef RV_BUILD_AHB_LITE + // Since all the signals in this block are tied to constant, we exclude this from coverage analysis + /*verilator coverage_off*/ wire lsu_axi_awvalid; wire lsu_axi_awready; wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid; @@ -745,15 +851,24 @@ import soc_ifc_pkg::*; assign ifu_axi_bvalid = '0; assign ifu_axi_bresp[1:0] = '0; assign ifu_axi_bid[pt.IFU_BUS_TAG-1:0] = '0; + + /*verilator coverage_on*/ `endif // `ifdef RV_BUILD_AHB_LITE - logic dmi_reg_en, dmi_reg_en_preQ; + // DMI (core) + logic dmi_en; + logic [6:0] dmi_addr; + logic dmi_wr_en; + logic [31:0] dmi_wdata; + logic [31:0] dmi_rdata; + + // DMI (core) + logic dmi_reg_en; logic [6:0] dmi_reg_addr; - logic dmi_reg_wr_en, dmi_reg_wr_en_preQ; + logic dmi_reg_wr_en; logic [31:0] dmi_reg_wdata; - logic [31:0] dmi_reg_rdata, dmi_reg_rdata_PostQ; - logic cptra_uncore_tap_aperture; + logic [31:0] dmi_reg_rdata; // Instantiate the el2_veer core el2_veer #(.pt(pt)) veer ( @@ -782,57 +897,46 @@ import soc_ifc_pkg::*; // Processor Signals .core_rst_n (dbg_rst_l), // Debug reset, active low .core_clk (clk), // Core clock - .rd_data (dmi_reg_rdata_PostQ), // Read data from Processor - .reg_wr_data (dmi_reg_wdata), // Write data to Processor - .reg_wr_addr (dmi_reg_addr), // Write address to Processor - .reg_en (dmi_reg_en_preQ), // Write interface bit to Processor - .reg_wr_en (dmi_reg_wr_en_preQ), // Write enable to Processor + .rd_data (dmi_rdata), // Read data from Processor + .reg_wr_data (dmi_wdata), // Write data to Processor + .reg_wr_addr (dmi_addr), // Write address to Processor + .reg_en (dmi_en), // Write interface bit to Processor + .reg_wr_en (dmi_wr_en), // Write enable to Processor .dmi_hard_reset () ); - logic cptra_dmi_reg_en_jtag_acccess_allowed, cptra_dmi_reg_wr_en_jtag_acccess_allowed, cptra_jtag_access_allowed; - logic veer_dmi_reg_en_jtag_acccess_allowed, veer_dmi_reg_wr_en_jtag_acccess_allowed, veer_jtag_access_allowed; - - // reg enable towards core is not enabled unless it is equal to or less than 0x4F - as in 0x50 to 0x7F are not routed - // Core tap reg aperture is 0x0 to 0x4F and uncore is 0x50 to 0x7F - assign cptra_uncore_tap_aperture = (dmi_reg_addr[6] & (dmi_reg_addr[5] | dmi_reg_addr[4])); - - // JTAG Accesses are permissable to VeeR aperture only when debug is unlocked - assign veer_jtag_access_allowed = ~(cptra_security_state_Latched.debug_locked); - - // Cptra JTAG accesses are blocked unless debug mode or manufacturing mode is enabled - // JTAG access is allowed if Caliptra is in debug or manuf mode (driven by SOC security_state inputs) when caliptra reset is deasserted - // Any change to debug or manuf mode bits after Caliptra reset is deasserted will keep JTAG locked. - assign cptra_jtag_access_allowed = ~(cptra_security_state_Latched.debug_locked) | - ((cptra_security_state_Latched.debug_locked) & (cptra_security_state_Latched.device_lifecycle == DEVICE_MANUFACTURING)); - - assign cptra_dmi_reg_en_jtag_acccess_allowed = dmi_reg_en_preQ & cptra_jtag_access_allowed; - assign cptra_dmi_reg_wr_en_jtag_acccess_allowed = dmi_reg_wr_en_preQ & cptra_jtag_access_allowed; - - assign veer_dmi_reg_en_jtag_acccess_allowed = dmi_reg_en_preQ & veer_jtag_access_allowed; - assign veer_dmi_reg_wr_en_jtag_acccess_allowed = dmi_reg_wr_en_preQ & veer_jtag_access_allowed; - - assign cptra_dmi_reg_en_preQ = dmi_reg_en_preQ; - - // Driving core vs uncore enables based on the right aperture - assign dmi_reg_en = cptra_uncore_tap_aperture ? '0 : veer_dmi_reg_en_jtag_acccess_allowed; - assign cptra_uncore_dmi_reg_en = cptra_uncore_tap_aperture ? cptra_dmi_reg_en_jtag_acccess_allowed : '0; - assign dmi_reg_wr_en = cptra_uncore_tap_aperture ? '0 : veer_dmi_reg_wr_en_jtag_acccess_allowed; - assign cptra_uncore_dmi_reg_wr_en = cptra_uncore_tap_aperture ? cptra_dmi_reg_wr_en_jtag_acccess_allowed : '0; - - // Qualified read data from core vs uncore - assign dmi_reg_rdata_PostQ = cptra_uncore_tap_aperture ? cptra_uncore_dmi_reg_rdata : dmi_reg_rdata; + // DMI core/uncore mux + dmi_mux dmi_mux ( + .core_enable (dmi_core_enable), + .uncore_enable (dmi_uncore_enable), + + .dmi_en (dmi_en), + .dmi_wr_en (dmi_wr_en), + .dmi_addr (dmi_addr), + .dmi_wdata (dmi_wdata), + .dmi_rdata (dmi_rdata), + + .dmi_core_en (dmi_reg_en), + .dmi_core_wr_en (dmi_reg_wr_en), + .dmi_core_addr (dmi_reg_addr), + .dmi_core_wdata (dmi_reg_wdata), + .dmi_core_rdata (dmi_reg_rdata), + + .dmi_uncore_en (dmi_uncore_en), + .dmi_uncore_wr_en (dmi_uncore_wr_en), + .dmi_uncore_addr (dmi_uncore_addr), + .dmi_uncore_wdata (dmi_uncore_wdata), + .dmi_uncore_rdata (dmi_uncore_rdata) + ); - // Passing the address and data without qualification is fine because the enables are qualified with JTAG allowed bits - assign cptra_uncore_dmi_reg_wdata = dmi_reg_wdata; - assign cptra_uncore_dmi_reg_addr = dmi_reg_addr; + always_comb dmi_active = dmi_en; `ifdef RV_ASSERT_ON -// to avoid internal assertions failure at time 0 -initial begin + // to avoid internal assertions failure at time 0 + initial begin $assertoff(0, veer); - @ (negedge clk) $asserton(0, veer); -end + @(negedge clk) $asserton(0, veer); + end `endif endmodule diff --git a/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv b/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv index 749077f3b..5fd027692 100644 --- a/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv @@ -337,8 +337,8 @@ import el2_pkg::*; bitmanip_dw_lzd_enc[5:0]= 6'b0; found = 1'b0; - for (int i=0; i<32 && found==0; i++) begin - if (bitmanip_lzd_os[31] == 1'b0) begin + for (int i=0; i<32; i++) begin + if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin bitmanip_dw_lzd_enc[5:0]= bitmanip_dw_lzd_enc[5:0] + 6'b00_0001; bitmanip_lzd_os[31:0] = bitmanip_lzd_os[31:0] << 1; end diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv index 0c1ed5f18..1d9858d13 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv @@ -48,6 +48,8 @@ import el2_pkg::*; //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_awvalid, output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid, output logic [31:0] ifu_axi_awaddr, @@ -66,6 +68,7 @@ import el2_pkg::*; output logic ifu_axi_wlast, output logic ifu_axi_bready, + /*verilator coverage_on*/ // AXI Read Channels output logic ifu_axi_arvalid, @@ -73,6 +76,8 @@ import el2_pkg::*; output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid, output logic [31:0] ifu_axi_araddr, output logic [3:0] ifu_axi_arregion, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [7:0] ifu_axi_arlen, output logic [2:0] ifu_axi_arsize, output logic [1:0] ifu_axi_arburst, @@ -80,9 +85,13 @@ import el2_pkg::*; output logic [3:0] ifu_axi_arcache, output logic [2:0] ifu_axi_arprot, output logic [3:0] ifu_axi_arqos, + /*verilator coverage_on*/ input logic ifu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_rready, + /*verilator coverage_on*/ input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid, input logic [63:0] ifu_axi_rdata, input logic [1:0] ifu_axi_rresp, @@ -149,9 +158,10 @@ import el2_pkg::*; input logic [63:0] iccm_rd_data, // Data read from ICCM. input logic [77:0] iccm_rd_data_ecc, // Data + ECC read from ICCM. - output logic ifu_iccm_rd_ecc_single_err, // This fetch has a single ICCM ecc error. - output logic cptra_iccm_dma_rd_ecc_single_err, // Active DMA access has a single ICCM ecc error. - output logic cptra_iccm_rd_ecc_double_err, // Output added for Caliptra reporting + // ICCM ECC status + output logic ifu_iccm_dma_rd_ecc_single_err, // This fetch has a single ICCM DMA ECC error. + output logic ifu_iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error. + output logic ifu_iccm_rd_ecc_double_err, // This fetch has a double ICCM ECC error. // Perf counter sigs output logic ifu_pmu_ic_miss, // ic miss @@ -195,6 +205,8 @@ import el2_pkg::*; output logic [15:0] ifu_i0_cinst, + output logic [31:1] ifu_pmp_addr, + input logic ifu_pmp_error, /// Icache debug input el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt , @@ -211,11 +223,13 @@ import el2_pkg::*; logic ifu_fb_consume1, ifu_fb_consume2; logic [31:1] ifc_fetch_addr_f; logic [31:1] ifc_fetch_addr_bf; + assign ifu_pmp_addr = ifc_fetch_addr_bf; logic [1:0] ifu_fetch_val; // valids on a 2B boundary, left justified [7] implies valid fetch logic [31:1] ifu_fetch_pc; // starting pc of fetch - logic iccm_rd_ecc_single_err, ic_error_start; + logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start; + assign ifu_iccm_dma_rd_ecc_single_err = iccm_dma_rd_ecc_single_err; assign ifu_iccm_rd_ecc_single_err = iccm_rd_ecc_single_err; assign ifu_ic_error_start = ic_error_start; @@ -248,9 +262,9 @@ import el2_pkg::*; logic [31:0] ifu_fetch_data_f; logic ifc_fetch_req_f; logic ifc_fetch_req_f_raw; + logic iccm_dma_rd_ecc_double_err; logic [1:0] iccm_rd_ecc_double_err; // This fetch has an iccm double error. - logic iccm_dma_rd_ecc_single_err; // Active DMA access has a single ICCM ecc error. - logic iccm_dma_rd_ecc_double_err; // Active DMA access has a double ICCM ecc error. + assign ifu_iccm_rd_ecc_double_err = |iccm_rd_ecc_double_err || |iccm_dma_rd_ecc_double_err; logic ifu_async_error_start; @@ -285,8 +299,7 @@ import el2_pkg::*; assign ifu_bp_inst_mask_f = 1'b1; end - assign cptra_iccm_dma_rd_ecc_single_err = iccm_dma_rd_ecc_single_err; - assign cptra_iccm_rd_ecc_double_err = |iccm_rd_ecc_double_err || |iccm_dma_rd_ecc_double_err; + // aligner diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_compress_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_compress_ctl.sv index 2b5932ae5..5f1d1d249 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_compress_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_compress_ctl.sv @@ -362,20 +362,23 @@ assign o[1] = 1'b1; assign o[0] = 1'b1; -assign legal = (!i[13]&!i[12]&i[11]&i[1]&!i[0]) | (!i[13]&!i[12]&i[6]&i[1]&!i[0]) | ( - !i[15]&!i[13]&i[11]&!i[1]) | (!i[13]&!i[12]&i[5]&i[1]&!i[0]) | ( - !i[13]&!i[12]&i[10]&i[1]&!i[0]) | (!i[15]&!i[13]&i[6]&!i[1]) | ( - i[15]&!i[12]&!i[1]&i[0]) | (!i[13]&!i[12]&i[9]&i[1]&!i[0]) | (!i[12] - &i[6]&!i[1]&i[0]) | (!i[15]&!i[13]&i[5]&!i[1]) | (!i[13]&!i[12]&i[8] - &i[1]&!i[0]) | (!i[12]&i[5]&!i[1]&i[0]) | (!i[15]&!i[13]&i[10]&!i[1]) | ( - !i[13]&!i[12]&i[7]&i[1]&!i[0]) | (i[12]&i[11]&!i[10]&!i[1]&i[0]) | ( - !i[15]&!i[13]&i[9]&!i[1]) | (!i[13]&!i[12]&i[4]&i[1]&!i[0]) | (i[13] - &i[12]&!i[1]&i[0]) | (!i[15]&!i[13]&i[8]&!i[1]) | (!i[13]&!i[12]&i[3] - &i[1]&!i[0]) | (i[13]&i[4]&!i[1]&i[0]) | (!i[13]&!i[12]&i[2]&i[1] - &!i[0]) | (!i[15]&!i[13]&i[7]&!i[1]) | (i[13]&i[3]&!i[1]&i[0]) | ( - i[13]&i[2]&!i[1]&i[0]) | (i[14]&!i[13]&!i[1]) | (!i[14]&!i[12]&!i[1] - &i[0]) | (i[15]&!i[13]&i[12]&i[1]&!i[0]) | (!i[15]&!i[13]&!i[12]&i[1] - &!i[0]) | (!i[15]&!i[13]&i[12]&!i[1]) | (i[14]&!i[13]&!i[0]); +assign legal = (!i[13]&!i[12]&i[11]&i[1]&!i[0]) | (!i[13]&!i[12]&i[10]&i[1]&!i[0]) | ( + !i[15]&!i[13]&i[11]&!i[1]) | (!i[13]&!i[12]&i[9]&i[1]&!i[0]) | ( + !i[13]&!i[12]&i[8]&i[1]&!i[0]) | (!i[15]&!i[13]&i[6]&!i[1]) | (i[15] + &!i[12]&!i[1]&i[0]) | (!i[13]&!i[12]&i[7]&i[1]&!i[0]) | (!i[15]&!i[13] + &i[5]&!i[1]) | (!i[12]&i[6]&!i[1]&i[0]) | (i[15]&!i[13]&i[6]&i[1] + &!i[0]) | (!i[15]&!i[13]&i[10]&!i[1]) | (!i[12]&i[5]&!i[1]&i[0]) | ( + i[12]&i[11]&!i[10]&!i[1]&i[0]) | (i[15]&!i[13]&i[5]&i[1]&!i[0]) | ( + !i[15]&!i[13]&i[9]&!i[1]) | (i[13]&i[12]&!i[1]&i[0]) | (i[15]&!i[13] + &i[4]&i[1]&!i[0]) | (!i[15]&!i[13]&i[8]&!i[1]) | (i[15]&!i[13]&i[3] + &i[1]&!i[0]) | (i[13]&i[4]&!i[1]&i[0]) | (i[15]&!i[13]&i[2]&i[1]&!i[0]) | ( + !i[15]&!i[13]&i[7]&!i[1]) | (i[13]&i[3]&!i[1]&i[0]) | (i[13]&i[2] + &!i[1]&i[0]) | (!i[14]&!i[12]&!i[1]&i[0]) | (i[15]&!i[13]&i[12]&i[1] + &!i[0]) | (i[14]&!i[13]&i[7]&!i[0]) | (i[14]&!i[13]&i[8]&!i[0]) | ( + i[14]&!i[13]&i[9]&!i[0]) | (!i[15]&!i[14]&!i[13]&!i[12]&i[1]&!i[0]) | ( + i[14]&!i[13]&i[10]&!i[0]) | (i[14]&!i[13]&i[11]&!i[0]) | (!i[15] + &!i[13]&i[12]&!i[1]) | (i[15]&i[14]&!i[13]&!i[0]) | (i[14]&!i[13] + &!i[1]); diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv index fe37ec8be..7e9765ae3 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv @@ -49,7 +49,8 @@ import el2_pkg::*; output logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr, // ecc error per bank input logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid from the I$ tag valid outside (in flops). - + input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc + input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, // this is being driven by the top level for soc testing/etc output logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit, // ic_rd_hit[3:0] output logic ic_tag_perr, // Tag Parity error @@ -111,6 +112,7 @@ import el2_pkg::*; input logic ic_sel_premux_data, // Select the pre_muxed data input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit, + input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc input logic scan_mode ) ; @@ -256,17 +258,17 @@ import el2_pkg::*; .Q (wb_dout_pre_up[i][k]), \ .CLK (clk), \ .ROP ( ), \ - .TEST1(1'b0), \ - .RME(1'b0), \ - .RM(4'b0000), \ + .TEST1(ic_data_ext_in_pkt[i][k].TEST1), \ + .RME(ic_data_ext_in_pkt[i][k].RME), \ + .RM(ic_data_ext_in_pkt[i][k].RM), \ \ - .LS(1'b0), \ - .DS(1'b0), \ - .SD(1'b0), \ + .LS(ic_data_ext_in_pkt[i][k].LS), \ + .DS(ic_data_ext_in_pkt[i][k].DS), \ + .SD(ic_data_ext_in_pkt[i][k].SD), \ \ - .TEST_RNM(1'b0), \ - .BC1(1'b0), \ - .BC2(1'b0) \ + .TEST_RNM(ic_data_ext_in_pkt[i][k].TEST_RNM), \ + .BC1(ic_data_ext_in_pkt[i][k].BC1), \ + .BC2(ic_data_ext_in_pkt[i][k].BC2) \ ); \ if (pt.ICACHE_BYPASS_ENABLE == 1) begin \ assign wrptr_in_up[i][k] = (wrptr_up[i][k] == (pt.ICACHE_NUM_BYPASS-1)) ? '0 : (wrptr_up[i][k] + 1'd1); \ @@ -408,17 +410,17 @@ if (pt.ICACHE_BYPASS_ENABLE == 1) begin \ .Q (wb_packeddout_pre[k]), \ .ME (|ic_bank_way_clken_final[k]), \ .ROP ( ), \ - .TEST1 (1'b0 ), \ - .RME (1'b0 ), \ - .RM (4'b0000 ), \ + .TEST1 (ic_data_ext_in_pkt[0][k].TEST1), \ + .RME (ic_data_ext_in_pkt[0][k].RME), \ + .RM (ic_data_ext_in_pkt[0][k].RM), \ \ - .LS (1'b0 ), \ - .DS (1'b0 ), \ - .SD (1'b0 ), \ + .LS (ic_data_ext_in_pkt[0][k].LS), \ + .DS (ic_data_ext_in_pkt[0][k].DS), \ + .SD (ic_data_ext_in_pkt[0][k].SD), \ \ - .TEST_RNM (1'b0 ), \ - .BC1 (1'b0 ), \ - .BC2 (1'b0 ) \ + .TEST_RNM (ic_data_ext_in_pkt[0][k].TEST_RNM), \ + .BC1 (ic_data_ext_in_pkt[0][k].BC1), \ + .BC2 (ic_data_ext_in_pkt[0][k].BC2) \ ); \ \ if (pt.ICACHE_BYPASS_ENABLE == 1) begin \ @@ -815,7 +817,7 @@ import el2_pkg::*; input logic ic_debug_wr_en, // Icache debug wr input logic ic_debug_tag_array, // Debug tag array input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. - + input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, output logic [25:0] ictag_debug_rd_data, input logic [70:0] ic_debug_wr_data, // Debug wr cache. @@ -966,17 +968,17 @@ end // block: OTHERS .CLK (clk), \ .ROP ( ), \ \ - .TEST1 (1'b0 ), \ - .RME (1'b0 ), \ - .RM (4'b0000 ), \ + .TEST1(ic_tag_ext_in_pkt[i].TEST1), \ + .RME(ic_tag_ext_in_pkt[i].RME), \ + .RM(ic_tag_ext_in_pkt[i].RM), \ \ - .LS (1'b0 ), \ - .DS (1'b0 ), \ - .SD (1'b0 ), \ + .LS(ic_tag_ext_in_pkt[i].LS), \ + .DS(ic_tag_ext_in_pkt[i].DS), \ + .SD(ic_tag_ext_in_pkt[i].SD), \ \ - .TEST_RNM(1'b0 ), \ - .BC1 (1'b0 ), \ - .BC2 (1'b0 ) \ + .TEST_RNM(ic_tag_ext_in_pkt[i].TEST_RNM), \ + .BC1(ic_tag_ext_in_pkt[i].BC1), \ + .BC2(ic_tag_ext_in_pkt[i].BC2) \ \ ); \ \ @@ -1170,17 +1172,17 @@ end // block: OTHERS .CLK (clk), \ .ROP ( ), \ \ - .TEST1 (1'b0 ), \ - .RME (1'b0 ), \ - .RM (4'b0000 ), \ + .TEST1 (ic_tag_ext_in_pkt[0].TEST1), \ + .RME (ic_tag_ext_in_pkt[0].RME), \ + .RM (ic_tag_ext_in_pkt[0].RM), \ \ - .LS (1'b0 ), \ - .DS (1'b0 ), \ - .SD (1'b0 ), \ + .LS (ic_tag_ext_in_pkt[0].LS), \ + .DS (ic_tag_ext_in_pkt[0].DS), \ + .SD (ic_tag_ext_in_pkt[0].SD), \ \ - .TEST_RNM (1'b0 ), \ - .BC1 (1'b0 ), \ - .BC2 (1'b0 ) \ + .TEST_RNM (ic_tag_ext_in_pkt[0].TEST_RNM), \ + .BC1 (ic_tag_ext_in_pkt[0].BC1), \ + .BC2 (ic_tag_ext_in_pkt[0].BC2) \ \ ); \ \ diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv index 772d1ec93..2ae73d762 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv @@ -1,6 +1,7 @@ //******************************************************************************** // SPDX-License-Identifier: Apache-2.0 // Copyright 2020 Western Digital Corporation or its affiliates. +// Copyright (c) 2023 Antmicro // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -37,7 +38,7 @@ import el2_pkg::*; input logic [2:0] iccm_wr_size, // ICCM write size input logic [77:0] iccm_wr_data, // ICCM write data - el2_mem_if.veer_iccm iccm_mem_export, // RAM repositioned in testbench and connected by this interface + el2_mem_if.veer_iccm iccm_mem_export, // RAM repositioned in testbench and connected by this interface output logic [63:0] iccm_rd_data, // ICCM read data output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc @@ -108,19 +109,22 @@ import el2_pkg::*; ((addr_bank_inc[pt.ICCM_BANK_HI:2] == i) ? addr_bank_inc[pt.ICCM_BITS-1 : pt.ICCM_BANK_INDEX_LO] : iccm_rw_addr[pt.ICCM_BITS-1 : pt.ICCM_BANK_INDEX_LO]); - always_comb begin - iccm_mem_export.iccm_clken[i] = iccm_clken[i]; - iccm_mem_export.iccm_wren_bank [i] = wren_bank [i]; - iccm_mem_export.iccm_addr_bank [i] = addr_bank [i]; - iccm_mem_export.iccm_bank_wr_data[i][38:0] = iccm_bank_wr_data[i][38:0]; - iccm_bank_dout[i][38:0] = iccm_mem_export.iccm_bank_dout[i][38:0]; - end - - // match the redundant rows - assign sel_red1[i] = (redundant_valid[1] & (((iccm_rw_addr[pt.ICCM_BITS-1:2] == redundant_address[1][pt.ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) | + + always_comb begin + iccm_mem_export.iccm_clken[i] = iccm_clken[i]; + iccm_mem_export.iccm_wren_bank[i] = wren_bank[i]; + iccm_mem_export.iccm_addr_bank[i] = addr_bank[i]; + iccm_mem_export.iccm_bank_wr_data[i] = iccm_bank_wr_data[i][31:0]; + iccm_mem_export.iccm_bank_wr_ecc[i] = iccm_bank_wr_data[i][32+pt.ICCM_ECC_WIDTH-1:32]; + iccm_bank_dout[i][31:0] = iccm_mem_export.iccm_bank_dout[i]; + iccm_bank_dout[i][32+pt.ICCM_ECC_WIDTH-1:32] = iccm_mem_export.iccm_bank_ecc[i]; + end + + // match the redundant rows + assign sel_red1[i] = (redundant_valid[1] & (((iccm_rw_addr[pt.ICCM_BITS-1:2] == redundant_address[1][pt.ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) | ((addr_bank_inc[pt.ICCM_BITS-1:2]== redundant_address[1][pt.ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i)))); - assign sel_red0[i] = (redundant_valid[0] & (((iccm_rw_addr[pt.ICCM_BITS-1:2] == redundant_address[0][pt.ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) | + assign sel_red0[i] = (redundant_valid[0] & (((iccm_rw_addr[pt.ICCM_BITS-1:2] == redundant_address[0][pt.ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) | ((addr_bank_inc[pt.ICCM_BITS-1:2]== redundant_address[0][pt.ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i)))); rvdff #(1) selred0 (.*, diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv index f6c7896af..48ff2ab49 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv @@ -64,6 +64,8 @@ import el2_pkg::*; //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic ifu_axi_awvalid, output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid, output logic [31:0] ifu_axi_awaddr, @@ -82,6 +84,7 @@ import el2_pkg::*; output logic ifu_axi_wlast, output logic ifu_axi_bready, + /*verilator coverage_on*/ // AXI Read Channels output logic ifu_axi_arvalid, @@ -89,6 +92,8 @@ import el2_pkg::*; output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid, output logic [31:0] ifu_axi_araddr, output logic [3:0] ifu_axi_arregion, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [7:0] ifu_axi_arlen, output logic [2:0] ifu_axi_arsize, output logic [1:0] ifu_axi_arburst, @@ -96,9 +101,13 @@ import el2_pkg::*; output logic [3:0] ifu_axi_arcache, output logic [2:0] ifu_axi_arprot, output logic [3:0] ifu_axi_arqos, + /*verilator coverage_on*/ input logic ifu_axi_rvalid, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic ifu_axi_rready, + /*verilator coverage_on*/ input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid, input logic [63:0] ifu_axi_rdata, input logic [1:0] ifu_axi_rresp, @@ -162,10 +171,10 @@ import el2_pkg::*; output logic ic_hit_f, // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f) output logic [1:0] ic_access_fault_f, // Access fault (bus error or ICCM access in region but out of offset range). output logic [1:0] ic_access_fault_type_f, // Access fault types - output logic iccm_rd_ecc_single_err, // This fetch has a single ICCM ecc error. - output logic [1:0] iccm_rd_ecc_double_err, // This fetch has a double ICCM ecc error. - output logic iccm_dma_rd_ecc_single_err, // Active DMA access has a single ICCM ecc error. - output logic iccm_dma_rd_ecc_double_err, // Active DMA access has a double ICCM ecc error. + output logic iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error. + output logic [1:0] iccm_rd_ecc_double_err, // This fetch has a double ICCM ECC error. + output logic iccm_dma_rd_ecc_single_err, // This fetch has a single ICCM DMA ECC error. + output logic iccm_dma_rd_ecc_double_err, // This fetch has a double ICCM DMA ECC error. output logic ic_error_start, // This has any I$ errors ( data/tag/ecc/parity ) output logic ifu_async_error_start, // Or of the sb iccm, and all the icache errors sent to aligner to stop @@ -182,6 +191,8 @@ import el2_pkg::*; output logic iccm_buf_correct_ecc, output logic iccm_correction_state, + input logic ifu_pmp_error, + input logic scan_mode ); @@ -281,11 +292,6 @@ import el2_pkg::*; logic sel_mb_status_addr ; logic [63:0] ic_final_data; - logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_ff ; - logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_ff ; - logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_w_debug ; - logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_w_debug ; - logic [pt.ICACHE_STATUS_BITS-1:0] way_status_new_ff ; logic way_status_wr_en_ff ; logic [pt.ICACHE_TAG_DEPTH-1:0][pt.ICACHE_STATUS_BITS-1:0] way_status_out ; @@ -529,10 +535,12 @@ import el2_pkg::*; exu_flush_final ? ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE; miss_state_en = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt; end + /*verilator coverage_off*/ default: begin : def_case miss_nxtstate = IDLE; miss_state_en = 1'b0; end + /*verilator coverage_on*/ endcase end rvdffs #(($bits(miss_state_t))) miss_state_ff (.clk(active_clk), .din(miss_nxtstate), .dout({miss_state}), .en(miss_state_en), .*); @@ -914,13 +922,13 @@ assign ic_miss_buff_half[63:0] = {ic_miss_buff_data[{other_tag,1'b1}],ic_miss ///////////////////////////////////////////////////////////////////////////////////// -assign ic_rd_parity_final_err = ic_tag_perr & ~exu_flush_final & sel_ic_data & ~(ifc_region_acc_fault_final_f | (|ifc_bus_acc_fault_f)) & + assign ic_rd_parity_final_err = ic_tag_perr & ~exu_flush_final & sel_ic_data & ~(ifc_region_acc_fault_final_f | (|ifc_bus_acc_fault_f)) & (fetch_req_icache_f & ~reset_all_tags & (~miss_pending | (miss_state==HIT_U_MISS)) & ~sel_mb_addr_ff); -logic [pt.ICACHE_NUM_WAYS-1:0] perr_err_inv_way; -logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] perr_ic_index_ff; -logic perr_sel_invalidate; -logic perr_sb_write_status ; + logic [pt.ICACHE_NUM_WAYS-1:0] perr_err_inv_way; + logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] perr_ic_index_ff; + logic perr_sel_invalidate; + logic perr_sb_write_status; assign perr_err_inv_way[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{perr_sel_invalidate}} ; @@ -941,39 +949,39 @@ logic perr_sb_write_status ; always_comb begin : ERROR_SM perr_nxtstate = ERR_IDLE; perr_state_en = 1'b0; - perr_sb_write_status = 1'b0; perr_sel_invalidate = 1'b0; + perr_sb_write_status = 1'b0; - case (perr_state) - ERR_IDLE: begin : err_idle - perr_nxtstate = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF; - perr_state_en = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt; - perr_sb_write_status = perr_state_en; - end - IC_WFF: begin : icache_wff // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state - perr_nxtstate = ERR_IDLE ; - perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt ; - perr_sel_invalidate = (dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb); - end - ECC_WFF: begin : ecc_wff - perr_nxtstate = ((~dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb ) | dec_tlu_force_halt) ? ERR_IDLE : ECC_CORR ; - perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt ; - end - DMA_SB_ERR : begin : dma_sb_ecc - perr_nxtstate = dec_tlu_force_halt ? ERR_IDLE : ECC_CORR; - perr_state_en = 1'b1; - end - ECC_CORR: begin : ecc_corr - perr_nxtstate = ERR_IDLE ; - perr_state_en = 1'b1 ; - end - default: begin : def_case - perr_nxtstate = ERR_IDLE; - perr_state_en = 1'b0; - perr_sb_write_status = 1'b0; - perr_sel_invalidate = 1'b0; - end - endcase + case (perr_state) + ERR_IDLE: begin : err_idle + perr_nxtstate = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF; + perr_state_en = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt; + perr_sb_write_status = perr_state_en; + end + IC_WFF: begin : icache_wff // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state + perr_nxtstate = ERR_IDLE; + perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt; + perr_sel_invalidate = (dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb); + end + ECC_WFF: begin : ecc_wff + perr_nxtstate = ((~dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb ) | dec_tlu_force_halt) ? ERR_IDLE : ECC_CORR; + perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt; + end + DMA_SB_ERR: begin : dma_sb_ecc + perr_nxtstate = dec_tlu_force_halt ? ERR_IDLE : ECC_CORR; + perr_state_en = 1'b1; + end + ECC_CORR: begin : ecc_corr + perr_nxtstate = ERR_IDLE; + perr_state_en = 1'b1; + end + default: begin : def_case + perr_nxtstate = ERR_IDLE; + perr_state_en = 1'b0; + perr_sel_invalidate = 1'b0; + perr_sb_write_status = 1'b0; + end + endcase end rvdffs #(($bits(perr_state_t))) perr_state_ff (.clk(active_clk), .din(perr_nxtstate), .dout({perr_state}), .en(perr_state_en), .*); @@ -1015,6 +1023,7 @@ logic perr_sb_write_status ; iccm_correction_state = 1'b1; end + /*verilator coverage_off*/ default: begin : def_case err_stop_nxtstate = ERR_STOP_IDLE; err_stop_state_en = 1'b0; @@ -1022,6 +1031,7 @@ logic perr_sb_write_status ; iccm_correction_state = 1'b1; end + /*verilator coverage_on*/ endcase end rvdffs #(($bits(err_stop_state_t))) err_stop_state_ff (.clk(active_clk), .din(err_stop_nxtstate), .dout({err_stop_state}), .en(err_stop_state_en), .*); @@ -1274,8 +1284,9 @@ ifc_dma_access_ok_prev,dma_iccm_req_f}) assign iccm_rw_addr[pt.ICCM_BITS-1:1] = ( ifc_dma_access_q_ok & dma_iccm_req & ~iccm_correct_ecc) ? dma_mem_addr[pt.ICCM_BITS-1:1] : (~(ifc_dma_access_q_ok & dma_iccm_req) & iccm_correct_ecc) ? {iccm_ecc_corr_index_ff[pt.ICCM_BITS-1:2],1'b0} : ifc_fetch_addr_bf[pt.ICCM_BITS-1:1] ; - assign iccm_dma_rd_ecc_single_err = iccm_dma_sb_error; - assign iccm_dma_rd_ecc_double_err = iccm_dma_rvalid && iccm_dma_ecc_error; + + assign iccm_dma_rd_ecc_single_err = iccm_dma_sb_error; + assign iccm_dma_rd_ecc_double_err = iccm_dma_rvalid && iccm_dma_ecc_error; ///////////////////////////////////////////////////////////////////////////////////// @@ -1391,9 +1402,15 @@ assign ic_write_stall = write_ic_16_bytes & ~((((miss_state== C /////////////////////////////////////////////////////////////// logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid_unq; if (pt.ICACHE_ENABLE == 1 ) begin: icache_enabled - assign ic_valid = ~ifu_wr_cumulative_err_data & ~(reset_ic_in | reset_ic_ff) & ~reset_tag_valid_for_miss; + logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_w_debug; + logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_ff ; + logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_w_debug; + logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_ff; + logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] perr_ic_index_ff; - assign ifu_status_wr_addr_w_debug[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] = ((ic_debug_rd_en | ic_debug_wr_en ) & ic_debug_tag_array) ? + assign ic_valid = ~ifu_wr_cumulative_err_data & ~(reset_ic_in | reset_ic_ff) & ~reset_tag_valid_for_miss; + + assign ifu_status_wr_addr_w_debug[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] = ((ic_debug_rd_en | ic_debug_wr_en ) & ic_debug_tag_array) ? ic_debug_addr[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] : ifu_status_wr_addr[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]; @@ -1628,8 +1645,9 @@ assign ic_debug_rd_en = dec_tlu_ic_diag_pkt.icache_rd_valid ; assign ic_debug_wr_en = dec_tlu_ic_diag_pkt.icache_wr_valid ; -assign ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] = {(ic_debug_way_enc[0] == 1'b1), - (ic_debug_way_enc[0] == 1'b0) }; +for (genvar i = 0; i < pt.ICACHE_NUM_WAYS; i = i + 1) begin : ic_debug_way_loop + assign ic_debug_way[i] = (ic_debug_way_enc == i[1:0]); +end assign ic_debug_tag_wr_en[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{ic_debug_wr_en & ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ; @@ -1670,7 +1688,12 @@ assign ACCESS7_okay = pt.INST_ACCESS_ENABLE7 & ((({ifc_fetch_addr_bf[31:1],1'b0} // memory protection - equation to look identical to the LSU equation - assign ifc_region_acc_okay = (~(|{pt.INST_ACCESS_ENABLE0,pt.INST_ACCESS_ENABLE1,pt.INST_ACCESS_ENABLE2,pt.INST_ACCESS_ENABLE3,pt.INST_ACCESS_ENABLE4,pt.INST_ACCESS_ENABLE5,pt.INST_ACCESS_ENABLE6,pt.INST_ACCESS_ENABLE7})) + if (pt.PMP_ENTRIES != 0) begin : g_ifc_access_check_pmp + assign ifc_region_acc_okay = ~ifu_pmp_error; + assign ifc_region_acc_fault_memory_bf = ~ifc_region_acc_okay & ifc_fetch_req_bf; + end + else begin : g_ifc_access_check + assign ifc_region_acc_okay = (~(|{pt.INST_ACCESS_ENABLE0,pt.INST_ACCESS_ENABLE1,pt.INST_ACCESS_ENABLE2,pt.INST_ACCESS_ENABLE3,pt.INST_ACCESS_ENABLE4,pt.INST_ACCESS_ENABLE5,pt.INST_ACCESS_ENABLE6,pt.INST_ACCESS_ENABLE7})) | ACCESS0_okay | ACCESS1_okay | ACCESS2_okay @@ -1681,11 +1704,9 @@ assign ACCESS7_okay = pt.INST_ACCESS_ENABLE7 & ((({ifc_fetch_addr_bf[31:1],1'b0} | ACCESS7_okay ; - assign ifc_region_acc_fault_memory_bf = ~ifc_iccm_access_bf & ~ifc_region_acc_okay & ifc_fetch_req_bf; + assign ifc_region_acc_fault_memory_bf = ~ifc_iccm_access_bf & ~ifc_region_acc_okay & ifc_fetch_req_bf; + end assign ifc_region_acc_fault_final_bf = ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf; - - - endmodule // el2_ifu_mem_ctl diff --git a/src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_m.svh b/src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_m.svh new file mode 100644 index 000000000..528d55de8 --- /dev/null +++ b/src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_m.svh @@ -0,0 +1,462 @@ +logic csr_misa; +logic csr_mvendorid; +logic csr_marchid; +logic csr_mimpid; +logic csr_mhartid; +logic csr_mstatus; +logic csr_mtvec; +logic csr_mip; +logic csr_mie; +logic csr_mcyclel; +logic csr_mcycleh; +logic csr_minstretl; +logic csr_minstreth; +logic csr_mscratch; +logic csr_mepc; +logic csr_mcause; +logic csr_mscause; +logic csr_mtval; +logic csr_mrac; +logic csr_dmst; +logic csr_mdseac; +logic csr_meihap; +logic csr_meivt; +logic csr_meipt; +logic csr_meicurpl; +logic csr_meicidpl; +logic csr_dcsr; +logic csr_mcgc; +logic csr_mfdc; +logic csr_dpc; +logic csr_mtsel; +logic csr_mtdata1; +logic csr_mtdata2; +logic csr_mhpmc3; +logic csr_mhpmc4; +logic csr_mhpmc5; +logic csr_mhpmc6; +logic csr_mhpmc3h; +logic csr_mhpmc4h; +logic csr_mhpmc5h; +logic csr_mhpmc6h; +logic csr_mhpme3; +logic csr_mhpme4; +logic csr_mhpme5; +logic csr_mhpme6; +logic csr_mcountinhibit; +logic csr_mitctl0; +logic csr_mitctl1; +logic csr_mitb0; +logic csr_mitb1; +logic csr_mitcnt0; +logic csr_mitcnt1; +logic csr_perfva; +logic csr_perfvb; +logic csr_perfvc; +logic csr_perfvd; +logic csr_perfve; +logic csr_perfvf; +logic csr_perfvg; +logic csr_perfvh; +logic csr_perfvi; +logic csr_mpmc; +logic csr_mcpc; +logic csr_meicpct; +logic csr_mdeau; +logic csr_micect; +logic csr_miccmect; +logic csr_mdccmect; +logic csr_mfdht; +logic csr_mfdhs; +logic csr_dicawics; +logic csr_dicad0h; +logic csr_dicad0; +logic csr_dicad1; +logic csr_dicago; +logic csr_pmpcfg; +logic csr_pmpaddr0; +logic csr_pmpaddr16; +logic csr_pmpaddr32; +logic csr_pmpaddr48; +logic valid_only; +logic presync; +logic postsync; +assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); + +assign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_mhartid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[2]); + +assign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]); + +assign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); + +assign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]); + +assign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]); + +assign csr_mcyclel = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]); + +assign csr_mcycleh = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_minstretl = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_minstreth = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mscause = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[2]); + +assign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]); + +assign csr_dmst = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]); + +assign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[3]); + +assign csr_meivt = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[2]); + +assign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]); + +assign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[0]); + +assign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]); + +assign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mtdata1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]); + +assign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]); + +assign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpmc6 = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpmc3h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpmc4h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpmc5h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpmc6h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpme4 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]); + +assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[0]); + +assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]); + +assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[0]); + +assign csr_mitcnt1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_perfva = 1'b0; + +assign csr_perfvb = 1'b0; + +assign csr_perfvc = 1'b0; + +assign csr_perfvd = 1'b0; + +assign csr_perfve = 1'b0; + +assign csr_perfvf = 1'b0; + +assign csr_perfvg = 1'b0; + +assign csr_perfvh = 1'b0; + +assign csr_perfvi = 1'b0; + +assign csr_mpmc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); + +assign csr_mcpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); + +assign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mdeau = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]); + +assign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_miccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]); + +assign csr_mdccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mfdht = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mfdhs = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); + +assign csr_dicawics = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_pmpcfg = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]); + +assign csr_pmpaddr0 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]); + +assign csr_pmpaddr16 = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]); + +assign csr_pmpaddr32 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[4]); + +assign csr_pmpaddr48 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]); + +assign valid_only = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | ( + !dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[4]) | ( + !dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | ( + !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[3]); + +assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]) | ( + dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | ( + dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +logic legal; +assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | ( + dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( + dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (!dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | ( + dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]); + diff --git a/src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_mu.svh b/src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_mu.svh new file mode 100644 index 000000000..c5b17061f --- /dev/null +++ b/src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_mu.svh @@ -0,0 +1,555 @@ +logic csr_misa; +logic csr_mvendorid; +logic csr_marchid; +logic csr_mimpid; +logic csr_mhartid; +logic csr_mstatus; +logic csr_mtvec; +logic csr_mip; +logic csr_mie; +logic csr_mcyclel; +logic csr_mcycleh; +logic csr_minstretl; +logic csr_minstreth; +logic csr_mscratch; +logic csr_mepc; +logic csr_mcause; +logic csr_mscause; +logic csr_mtval; +logic csr_mrac; +logic csr_dmst; +logic csr_mdseac; +logic csr_meihap; +logic csr_meivt; +logic csr_meipt; +logic csr_meicurpl; +logic csr_meicidpl; +logic csr_dcsr; +logic csr_mcgc; +logic csr_mfdc; +logic csr_dpc; +logic csr_mtsel; +logic csr_mtdata1; +logic csr_mtdata2; +logic csr_mhpmc3; +logic csr_mhpmc4; +logic csr_mhpmc5; +logic csr_mhpmc6; +logic csr_mhpmc3h; +logic csr_mhpmc4h; +logic csr_mhpmc5h; +logic csr_mhpmc6h; +logic csr_mhpme3; +logic csr_mhpme4; +logic csr_mhpme5; +logic csr_mhpme6; +logic csr_mcounteren; +logic csr_mcountinhibit; +logic csr_mitctl0; +logic csr_mitctl1; +logic csr_mitb0; +logic csr_mitb1; +logic csr_mitcnt0; +logic csr_mitcnt1; +logic csr_perfva; +logic csr_perfvb; +logic csr_perfvc; +logic csr_perfvd; +logic csr_perfve; +logic csr_perfvf; +logic csr_perfvg; +logic csr_perfvh; +logic csr_perfvi; +logic csr_mpmc; +logic csr_mcpc; +logic csr_meicpct; +logic csr_mdeau; +logic csr_micect; +logic csr_miccmect; +logic csr_mdccmect; +logic csr_mfdht; +logic csr_mfdhs; +logic csr_dicawics; +logic csr_dicad0h; +logic csr_dicad0; +logic csr_dicad1; +logic csr_dicago; +logic csr_menvcfg; +logic csr_menvcfgh; +logic csr_pmpcfg; +logic csr_pmpaddr0; +logic csr_pmpaddr16; +logic csr_pmpaddr32; +logic csr_pmpaddr48; +logic csr_cyclel; +logic csr_cycleh; +logic csr_instretl; +logic csr_instreth; +logic csr_hpmc3; +logic csr_hpmc4; +logic csr_hpmc5; +logic csr_hpmc6; +logic csr_hpmc3h; +logic csr_hpmc4h; +logic csr_hpmc5h; +logic csr_hpmc6h; +logic csr_mseccfgl; +logic csr_mseccfgh; +logic valid_only; +logic presync; +logic postsync; +assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); + +assign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_mhartid = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]); + +assign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]); + +assign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); + +assign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[0]); + +assign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mcyclel = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_mcycleh = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_minstretl = (dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_minstreth = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mscause = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[2]); + +assign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]); + +assign csr_dmst = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]); + +assign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[3]); + +assign csr_meivt = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[2]); + +assign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]); + +assign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[0]); + +assign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]); + +assign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mtdata1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]); + +assign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]); + +assign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); + +assign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_mhpmc6 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpmc3h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); + +assign csr_mhpmc4h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpmc5h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_mhpmc6h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpme4 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]); + +assign csr_mcounteren = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); + +assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[0]); + +assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]); + +assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[0]); + +assign csr_mitcnt1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_perfva = 1'b0; + +assign csr_perfvb = 1'b0; + +assign csr_perfvc = 1'b0; + +assign csr_perfvd = 1'b0; + +assign csr_perfve = 1'b0; + +assign csr_perfvf = 1'b0; + +assign csr_perfvg = 1'b0; + +assign csr_perfvh = 1'b0; + +assign csr_perfvi = 1'b0; + +assign csr_mpmc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]); + +assign csr_mcpc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); + +assign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mdeau = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]); + +assign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_miccmect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]); + +assign csr_mdccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mfdht = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mfdhs = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); + +assign csr_dicawics = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_menvcfg = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]); + +assign csr_menvcfgh = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]); + +assign csr_pmpcfg = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]); + +assign csr_pmpaddr0 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]); + +assign csr_pmpaddr16 = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]); + +assign csr_pmpaddr32 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[4]); + +assign csr_pmpaddr48 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]); + +assign csr_cyclel = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_cycleh = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_instretl = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_instreth = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_hpmc3 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_hpmc4 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_hpmc5 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_hpmc6 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); + +assign csr_hpmc3h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_hpmc4h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_hpmc5h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_hpmc6h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); + +assign csr_mseccfgl = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]); + +assign csr_mseccfgh = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[4]); + +assign valid_only = (!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]); + +assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | ( + dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | ( + dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); + +assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | ( + dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | ( + !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +logic legal; +assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]) | ( + dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9] + &!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | ( + !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | ( + !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | ( + dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | ( + !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | ( + dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (!dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | ( + dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]); + diff --git a/src/riscv_core/veer_el2/rtl/include/el2_def.sv b/src/riscv_core/veer_el2/rtl/include/el2_def.sv index 5c5cc2b81..eec1d9dbe 100644 --- a/src/riscv_core/veer_el2/rtl/include/el2_def.sv +++ b/src/riscv_core/veer_el2/rtl/include/el2_def.sv @@ -1,6 +1,5 @@ -//******************************************************************************** // SPDX-License-Identifier: Apache-2.0 -// Copyright 2020 Western Digital Corporation or its affiliates. +// Copyright (c) 2023 Antmicro // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -13,8 +12,6 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -//******************************************************************************** - // performance monitor stuff //`ifndef EL2_DEF_SV @@ -124,7 +121,7 @@ typedef struct packed { logic i0div; logic csrwen; logic csrwonly; - logic [11:0] csrwaddr; + logic [11:0] csraddr; // likely to change logic [4:0] i0rd; logic i0load; @@ -422,6 +419,39 @@ typedef struct packed { logic icache_rd_valid; logic icache_wr_valid; } el2_cache_debug_pkt_t; + + + typedef enum logic [2:0] { + NONE = 3'b000, + READ = 3'b001, + WRITE = 3'b010, + EXEC = 3'b100 + } el2_pmp_type_pkt_t; + + + typedef enum logic [1:0] { + OFF = 2'b00, + TOR = 2'b01, + NA4 = 2'b10, + NAPOT = 2'b11 + } el2_pmp_mode_pkt_t; + + + typedef struct packed { + logic lock; + logic [1:0] reserved; + el2_pmp_mode_pkt_t mode; + logic execute; + logic write; + logic read; + } el2_pmp_cfg_pkt_t; + + typedef struct packed { + logic RLB; + logic MMWP; + logic MML; + } el2_mseccfg_pkt_t; + //`endif endpackage // el2_pkg diff --git a/src/riscv_core/veer_el2/rtl/lib/ahb_to_axi4.sv b/src/riscv_core/veer_el2/rtl/lib/ahb_to_axi4.sv index 8c8226b33..a6afc9639 100644 --- a/src/riscv_core/veer_el2/rtl/lib/ahb_to_axi4.sv +++ b/src/riscv_core/veer_el2/rtl/lib/ahb_to_axi4.sv @@ -30,7 +30,9 @@ import el2_pkg::*; ( input clk, input rst_l, + /* verilator coverage_off */ input scan_mode, + /* verilator coverage_on */ input bus_clk_en, input clk_override, @@ -38,45 +40,76 @@ import el2_pkg::*; // AXI Write Channels output logic axi_awvalid, input logic axi_awready, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [TAG-1:0] axi_awid, + /*verilator coverage_on*/ output logic [31:0] axi_awaddr, output logic [2:0] axi_awsize, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [2:0] axi_awprot, output logic [7:0] axi_awlen, output logic [1:0] axi_awburst, + /*verilator coverage_on*/ output logic axi_wvalid, input logic axi_wready, output logic [63:0] axi_wdata, output logic [7:0] axi_wstrb, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic axi_wlast, + /*verilator coverage_on*/ input logic axi_bvalid, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic axi_bready, + /*verilator coverage_on*/ input logic [1:0] axi_bresp, + /* Exclude unused AXI rid since it has no equivalent in AHB */ + /*verilator coverage_off*/ input logic [TAG-1:0] axi_bid, + /*verilator coverage_on*/ // AXI Read Channels output logic axi_arvalid, input logic axi_arready, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [TAG-1:0] axi_arid, + /*verilator coverage_on*/ output logic [31:0] axi_araddr, output logic [2:0] axi_arsize, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [2:0] axi_arprot, output logic [7:0] axi_arlen, output logic [1:0] axi_arburst, + /*verilator coverage_on*/ input logic axi_rvalid, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic axi_rready, + /*verilator coverage_on*/ + /* Exclude unused AXI rid since it has no equivalent in AHB */ + /*verilator coverage_off*/ input logic [TAG-1:0] axi_rid, + /*verilator coverage_on*/ input logic [63:0] axi_rdata, input logic [1:0] axi_rresp, // AHB-Lite signals input logic [31:0] ahb_haddr, // ahb bus address + // Exclude input signals that are unused in this file (their AXI equivalents + // are tied to constants) + /*verilator coverage_off*/ input logic [2:0] ahb_hburst, // tied to 0 input logic ahb_hmastlock, // tied to 0 input logic [3:0] ahb_hprot, // tied to 4'b0011 + /*verilator coverage_on*/ input logic [2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3) input logic [1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now) input logic ahb_hwrite, // ahb bus write @@ -110,7 +143,6 @@ import el2_pkg::*; logic [2:0] ahb_hsize_q; logic ahb_hwrite_q; logic [31:0] ahb_haddr_q; - logic [63:0] ahb_hwdata_q; logic ahb_hresp_q; //Miscellaneous signals @@ -286,4 +318,4 @@ import el2_pkg::*; `endif -endmodule // ahb_to_axi4 \ No newline at end of file +endmodule // ahb_to_axi4 diff --git a/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv b/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv index 45be48c35..51abd8403 100644 --- a/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv +++ b/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv @@ -72,9 +72,12 @@ import el2_pkg::*; // AHB-Lite signals output logic [31:0] ahb_haddr, // ahb bus address + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [2:0] ahb_hburst, // tied to 0 output logic ahb_hmastlock, // tied to 0 - output logic [3:0] ahb_hprot, // tied to 4'b0011 + /*verilator coverage_on*/ + output logic [3:0] ahb_hprot, // [3:1] are tied to 3'b001 output logic [2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3) output logic [1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now) output logic ahb_hwrite, // ahb bus write @@ -88,11 +91,21 @@ import el2_pkg::*; localparam ID = 1; localparam PRTY = 1; - typedef enum logic [2:0] {IDLE=3'b000, CMD_RD=3'b001, CMD_WR=3'b010, DATA_RD=3'b011, DATA_WR=3'b100, DONE=3'b101, STREAM_RD=3'b110, STREAM_ERR_RD=3'b111} state_t; + typedef enum logic [3:0] { + IDLE = 4'b0000, + CMD_RD = 4'b0001, + CMD_WR = 4'b1001, + DATA_RD = 4'b0010, + DATA_WR = 4'b1010, + DONE_RD = 4'b0011, + DONE_WR = 4'b1011, + STREAM_RD = 4'b0101, + STREAM_ERR_RD = 4'b0110 + } state_t; + state_t buf_state, buf_nxtstate; logic slave_valid; - logic slave_ready; logic [TAG-1:0] slave_tag; logic [63:0] slave_rdata; logic [3:0] slave_opc; @@ -245,15 +258,14 @@ import el2_pkg::*; assign master_wdata[63:0] = wrbuf_data[63:0]; // AXI response channel signals - assign axi_bvalid = slave_valid & slave_ready & slave_opc[3]; + assign axi_bvalid = slave_valid & slave_opc[3]; assign axi_bresp[1:0] = slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b0); assign axi_bid[TAG-1:0] = slave_tag[TAG-1:0]; - assign axi_rvalid = slave_valid & slave_ready & (slave_opc[3:2] == 2'b0); + assign axi_rvalid = slave_valid & (slave_opc[3:2] == 2'b0); assign axi_rresp[1:0] = slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b0); assign axi_rid[TAG-1:0] = slave_tag[TAG-1:0]; assign axi_rdata[63:0] = slave_rdata[63:0]; - assign slave_ready = axi_bready & axi_rready; // FIFO state machine always_comb begin @@ -324,7 +336,7 @@ import el2_pkg::*; ahb_htrans[1:0] = 2'b10 & {2{~buf_state_en}}; end DATA_RD: begin - buf_nxtstate = DONE; + buf_nxtstate = DONE_RD; buf_state_en = (ahb_hready_q | ahb_hresp_q); buf_data_wr_en = buf_state_en; slvbuf_error_in= ahb_hresp_q; @@ -345,8 +357,8 @@ import el2_pkg::*; end DATA_WR: begin buf_state_en = (cmd_doneQ & ahb_hready_q) | ahb_hresp_q; - master_ready = buf_state_en & ~ahb_hresp_q & slave_ready; // Ready to accept new command if current command done and no error - buf_nxtstate = (ahb_hresp_q | ~slave_ready) ? DONE : + master_ready = buf_state_en & ~ahb_hresp_q & axi_bready; // Ready to accept new command if current command done and no error + buf_nxtstate = (ahb_hresp_q | ~axi_bready) ? DONE_WR : ((master_valid & master_ready) ? ((master_opc[2:1] == 2'b01) ? CMD_WR : CMD_RD) : IDLE); slvbuf_error_in = ahb_hresp_q; slvbuf_error_en = buf_state_en; @@ -359,19 +371,29 @@ import el2_pkg::*; ((buf_cmd_byte_ptrQ == 3'b111) | (buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1)] == 1'b0)))); bypass_en = buf_state_en & buf_write_in & (buf_nxtstate == CMD_WR); // Only bypass for writes for the time being ahb_htrans[1:0] = {2{(~(cmd_done | cmd_doneQ) | bypass_en)}} & 2'b10; - slave_valid_pre = buf_state_en & (buf_nxtstate != DONE); + slave_valid_pre = buf_state_en & (buf_nxtstate != DONE_WR); trxn_done = ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q[1:0] != 2'b0); buf_cmd_byte_ptr_en = trxn_done | bypass_en; buf_cmd_byte_ptr = bypass_en ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1) : buf_cmd_byte_ptrQ; - end - DONE: begin + end + DONE_WR: begin + buf_nxtstate = IDLE; + buf_state_en = axi_bvalid & axi_bready; + slvbuf_error_en = 1'b1; + slave_valid_pre = 1'b1; + end + DONE_RD: begin buf_nxtstate = IDLE; - buf_state_en = slave_ready; + buf_state_en = axi_rvalid & axi_rready; // axi_rlast == 1 slvbuf_error_en = 1'b1; slave_valid_pre = 1'b1; end + default: begin + buf_nxtstate = IDLE; + buf_state_en = 1'b1; + end endcase end @@ -403,7 +425,7 @@ import el2_pkg::*; assign slave_valid = slave_valid_pre;// & (~slvbuf_posted_write | slvbuf_error); assign slave_opc[3:2] = slvbuf_write ? 2'b11 : 2'b00; assign slave_opc[1:0] = {2{slvbuf_error}} & 2'b10; - assign slave_rdata[63:0] = slvbuf_error ? {2{last_bus_addr[31:0]}} : ((buf_state == DONE) ? buf_data[63:0] : ahb_hrdata_q[63:0]); + assign slave_rdata[63:0] = slvbuf_error ? {2{last_bus_addr[31:0]}} : ((buf_state == DONE_RD) ? buf_data[63:0] : ahb_hrdata_q[63:0]); assign slave_tag[TAG-1:0] = slvbuf_tag[TAG-1:0]; assign last_addr_en = (ahb_htrans[1:0] != 2'b0) & ahb_hready & ahb_hwrite ; diff --git a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv index 6cc12baf7..083989933 100644 --- a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv +++ b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv @@ -15,7 +15,6 @@ // all flops call the rvdff flop -`include "common_defines.sv" module rvdff #( parameter WIDTH=1, SHORT=0 ) ( diff --git a/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv b/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv index d71acf06e..8b5df04d3 100644 --- a/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv +++ b/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv @@ -1,6 +1,5 @@ -//******************************************************************************** // SPDX-License-Identifier: Apache-2.0 -// Copyright 2020 Western Digital Corporation or its affiliates. +// Copyright (c) 2023 Antmicro // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -13,7 +12,6 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -//******************************************************************************** module el2_btb_tag_hash import el2_pkg::*; diff --git a/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv b/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv index 1d0a83723..0e38efaff 100644 --- a/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv +++ b/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv @@ -1,6 +1,8 @@ //******************************************************************************** // SPDX-License-Identifier: Apache-2.0 // Copyright 2020 Western Digital Corporation or its affiliates. +// Copyright 2022 Microsoft Corporation +// Copyright (c) 2023 Antmicro // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -16,93 +18,74 @@ //******************************************************************************** -// ************************************************* -// -// Filename: el2_mem_if.sv -// Contributing company: MICROSOFT -// Creation Date: 2022/9/16 -// -// Description: -// This file is added to the VeeR-EL2 code-base after -// the initial download, specifically for the Caliptra -// security module project. -// This file is used to bring synthesizable memory -// components to the top-level of an SoC project so that -// they may be manipulated according to the target fabrication -// process. Exported memory blocks include: -// - I-Cache -// - ICCM -// - DCCM -// -// LICENSE NOTES: -// -// ************************************************* - import el2_pkg::*; interface el2_mem_if #( `include "el2_param.vh" -) ( -); - - -////////////////////////////////////////// -// Clock -logic clk; - - -////////////////////////////////////////// -// ICCM -logic [pt.ICCM_NUM_BANKS-1:0] iccm_clken; -logic [pt.ICCM_NUM_BANKS-1:0] iccm_wren_bank; -logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank; - -logic [pt.ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data; -logic [pt.ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_dout; - - -////////////////////////////////////////// -// DCCM -logic [pt.DCCM_NUM_BANKS-1:0] dccm_clken; -logic [pt.DCCM_NUM_BANKS-1:0] dccm_wren_bank; -logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank; -logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_bank; -logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_FDATA_WIDTH-1:0] dccm_bank_dout; - - -////////////////////////////////////////// -// MODPORTS -modport veer_iccm ( - input clk, - // ICCM - output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, - input iccm_bank_dout -); - -modport veer_dccm ( - input clk, - // DCCM - output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, - input dccm_bank_dout -); - -modport veer_sram_src ( - output clk, - // ICCM - output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, - input iccm_bank_dout, - // DCCM - output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, - input dccm_bank_dout -); - -modport veer_sram_sink ( - input clk, - // ICCM - input iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, - output iccm_bank_dout, - // DCCM - input dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, - output dccm_bank_dout -); +) (); + localparam DCCM_ECC_WIDTH = pt.DCCM_FDATA_WIDTH - pt.DCCM_DATA_WIDTH; + + ////////////////////////////////////////// + // Clock + logic clk; + + + ////////////////////////////////////////// + // ICCM + logic [pt.ICCM_NUM_BANKS-1:0] iccm_clken; + logic [pt.ICCM_NUM_BANKS-1:0] iccm_wren_bank; + logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank; + + logic [pt.ICCM_NUM_BANKS-1:0][ 31:0] iccm_bank_wr_data; + logic [pt.ICCM_NUM_BANKS-1:0][ pt.ICCM_ECC_WIDTH-1:0] iccm_bank_wr_ecc; + logic [pt.ICCM_NUM_BANKS-1:0][ 31:0] iccm_bank_dout; + logic [pt.ICCM_NUM_BANKS-1:0][ pt.ICCM_ECC_WIDTH-1:0] iccm_bank_ecc; + + + ////////////////////////////////////////// + // DCCM + logic [pt.DCCM_NUM_BANKS-1:0] dccm_clken; + logic [pt.DCCM_NUM_BANKS-1:0] dccm_wren_bank; + logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank; + logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank; + logic [pt.DCCM_NUM_BANKS-1:0][ DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank; + logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout; + logic [pt.DCCM_NUM_BANKS-1:0][ DCCM_ECC_WIDTH-1:0] dccm_bank_ecc; + + + ////////////////////////////////////////// + // MODPORTS + modport veer_iccm( + input clk, + // ICCM + output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc, + input iccm_bank_dout, iccm_bank_ecc + ); + + modport veer_dccm( + input clk, + // DCCM + output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank, + input dccm_bank_dout, dccm_bank_ecc + ); + + modport veer_sram_src( + output clk, + // ICCM + output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc, + input iccm_bank_dout, iccm_bank_ecc, + // DCCM + output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank, + input dccm_bank_dout, dccm_bank_ecc + ); + + modport veer_sram_sink( + input clk, + // ICCM + input iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc, + output iccm_bank_dout, iccm_bank_ecc, + // DCCM + input dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank, + output dccm_bank_dout, dccm_bank_ecc + ); endinterface diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv index 5b238fd37..fd58f71cd 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv @@ -118,13 +118,22 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, output logic [31:0] lsu_axi_awaddr, output logic [3:0] lsu_axi_awregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_awsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_awburst, output logic lsu_axi_awlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_awcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_awprot, output logic [3:0] lsu_axi_awqos, + /*verilator coverage_on*/ output logic lsu_axi_wvalid, input logic lsu_axi_wready, @@ -133,7 +142,10 @@ import el2_pkg::*; output logic lsu_axi_wlast, input logic lsu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] lsu_axi_bresp, input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, @@ -143,16 +155,28 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, output logic [31:0] lsu_axi_araddr, output logic [3:0] lsu_axi_arregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_arsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_arburst, output logic lsu_axi_arlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_arcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_arprot, output logic [3:0] lsu_axi_arqos, + /*verilator coverage_on*/ input logic lsu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_rready, + /*verilator coverage_on*/ input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid, input logic [63:0] lsu_axi_rdata, input logic [1:0] lsu_axi_rresp, @@ -174,14 +198,21 @@ import el2_pkg::*; output logic [63:0] dccm_dma_rdata, // lsu data for DMA dccm read output logic dccm_ready, // lsu ready for DMA access - // Caliptra ECC status signals - output logic cptra_dccm_ecc_single_error, - output logic cptra_dccm_ecc_double_error, + // DCCM ECC status + output logic lsu_dccm_rd_ecc_single_err, + output logic lsu_dccm_rd_ecc_double_err, input logic scan_mode, // scan mode input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. - input logic rst_l // reset, active low + input logic rst_l, // reset, active low + + output logic [31:0] lsu_pmp_addr_start, + output logic [31:0] lsu_pmp_addr_end, + input logic lsu_pmp_error_start, + input logic lsu_pmp_error_end, + output logic lsu_pmp_we, + output logic lsu_pmp_re ); @@ -208,14 +239,20 @@ import el2_pkg::*; logic lsu_single_ecc_error_r; logic lsu_double_ecc_error_r; logic ld_single_ecc_error_r, ld_single_ecc_error_r_ff; + assign lsu_dccm_rd_ecc_single_err = lsu_single_ecc_error_r; + assign lsu_dccm_rd_ecc_double_err = lsu_double_ecc_error_r; logic [31:0] picm_mask_data_m; logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r; logic [31:0] end_addr_d, end_addr_m, end_addr_r; + assign lsu_pmp_addr_start = lsu_addr_d; + assign lsu_pmp_addr_end = end_addr_d; el2_lsu_pkt_t lsu_pkt_d, lsu_pkt_m, lsu_pkt_r; logic lsu_i0_valid_d, lsu_i0_valid_m, lsu_i0_valid_r; + assign lsu_pmp_we = lsu_pkt_d.store & lsu_pkt_d.valid; + assign lsu_pmp_re = lsu_pkt_d.load & lsu_pkt_d.valid; // Store Buffer signals logic store_stbuf_reqvld_r; @@ -310,8 +347,8 @@ import el2_pkg::*; // Store buffer now have only non-dma dccm stores // stbuf_empty not needed since it has only dccm stores assign lsu_idle_any = ~((lsu_pkt_m.valid & ~lsu_pkt_m.dma) | - (lsu_pkt_r.valid & ~lsu_pkt_r.dma)) & - lsu_bus_buffer_empty_any; + (lsu_pkt_r.valid & ~lsu_pkt_r.dma)) & + lsu_bus_buffer_empty_any; assign lsu_active = (lsu_pkt_m.valid | lsu_pkt_r.valid | ld_single_ecc_error_r_ff) | ~lsu_bus_buffer_empty_any; // This includes DMA. Used for gating top clock @@ -361,9 +398,6 @@ import el2_pkg::*; .* ); - assign cptra_dccm_ecc_single_error = lsu_single_ecc_error_r; - assign cptra_dccm_ecc_double_error = lsu_double_ecc_error_r; - el2_lsu_trigger #(.pt(pt)) trigger ( .store_data_m(store_data_m[31:0]), .* diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv index 711de464d..16e6a6979 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv @@ -50,6 +50,9 @@ import el2_pkg::*; output logic fir_dccm_access_error_d, // Fast interrupt dccm access error output logic fir_nondccm_access_error_d,// Fast interrupt dccm access error + input logic lsu_pmp_error_start, + input logic lsu_pmp_error_end, + input logic scan_mode // Scan mode ); @@ -124,8 +127,8 @@ import el2_pkg::*; assign csr_idx[4:0] = {start_addr_d[31:28], 1'b1}; assign is_sideeffects_d = dec_tlu_mrac_ff[csr_idx] & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & lsu_pkt_d.valid & (lsu_pkt_d.store | lsu_pkt_d.load); //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions assign is_aligned_d = (lsu_pkt_d.word & (start_addr_d[1:0] == 2'b0)) | - (lsu_pkt_d.half & (start_addr_d[0] == 1'b0)) | - lsu_pkt_d.by; + (lsu_pkt_d.half & (start_addr_d[0] == 1'b0)) | + lsu_pkt_d.by; logic ACCESS0_STARTOK; logic ACCESS1_STARTOK; @@ -161,6 +164,7 @@ import el2_pkg::*; assign ACCESS6_ENDOK = pt.DATA_ACCESS_ENABLE6 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK6)) == (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6); assign ACCESS7_ENDOK = pt.DATA_ACCESS_ENABLE7 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK7)) == (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7); + if (pt.PMP_ENTRIES == 0) begin assign non_dccm_access_ok = (~(|{pt.DATA_ACCESS_ENABLE0,pt.DATA_ACCESS_ENABLE1,pt.DATA_ACCESS_ENABLE2,pt.DATA_ACCESS_ENABLE3,pt.DATA_ACCESS_ENABLE4,pt.DATA_ACCESS_ENABLE5,pt.DATA_ACCESS_ENABLE6,pt.DATA_ACCESS_ENABLE7})) | (( ACCESS0_STARTOK| ACCESS1_STARTOK| @@ -178,6 +182,7 @@ import el2_pkg::*; ACCESS5_ENDOK| ACCESS6_ENDOK| ACCESS7_ENDOK)); + end // Access fault logic // 0. Unmapped local memory : Addr in dccm region but not in dccm offset OR Addr in picm region but not in picm offset OR DCCM -> PIC cross when DCCM/PIC in same region @@ -193,13 +198,21 @@ import el2_pkg::*; (end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d)) | // 0. Addr in dccm/pic region but not in dccm/pic offset (start_addr_in_dccm_d & end_addr_in_pic_d) | // 0. DCCM -> PIC cross when DCCM/PIC in same region (start_addr_in_pic_d & end_addr_in_dccm_d)); // 0. DCCM -> PIC cross when DCCM/PIC in same region - assign mpu_access_fault_d = (~start_addr_in_dccm_region_d & ~non_dccm_access_ok); // 3. Address is not in a populated non-dccm region + if (pt.PMP_ENTRIES > 0) begin + assign mpu_access_fault_d = (lsu_pmp_error_start | lsu_pmp_error_end); // X. Address is in blocked region + end else begin + assign mpu_access_fault_d = (~start_addr_in_dccm_region_d & ~non_dccm_access_ok); // 3. Address is not in a populated non-dccm region + end end else begin assign unmapped_access_fault_d = ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | // 0. Addr in dccm region but not in dccm offset (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d) | // 0. Addr in dccm region but not in dccm offset (start_addr_in_pic_region_d & ~start_addr_in_pic_d) | // 0. Addr in picm region but not in picm offset (end_addr_in_pic_region_d & ~end_addr_in_pic_d)); // 0. Addr in picm region but not in picm offset - assign mpu_access_fault_d = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok); // 3. Address is not in a populated non-dccm region + if (pt.PMP_ENTRIES > 0) begin + assign mpu_access_fault_d = (lsu_pmp_error_start | lsu_pmp_error_end); // X. Address is in blocked region + end else begin + assign mpu_access_fault_d = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok); // 3. Address is not in a populated non-dccm region + end end assign access_fault_d = (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & lsu_pkt_d.valid & ~lsu_pkt_d.dma; @@ -217,7 +230,7 @@ import el2_pkg::*; // Fast interrupt error logic assign fir_dccm_access_error_d = ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | - (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & lsu_pkt_d.valid & lsu_pkt_d.fast_int; + (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & lsu_pkt_d.valid & lsu_pkt_d.fast_int; assign fir_nondccm_access_error_d = ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & lsu_pkt_d.valid & lsu_pkt_d.fast_int; rvdff #(.WIDTH(1)) is_sideeffects_mff (.din(is_sideeffects_d), .dout(is_sideeffects_m), .clk(lsu_c2_m_clk), .*); diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv index 7da9b1f1b..80a97ddae 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv @@ -106,13 +106,22 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, output logic [31:0] lsu_axi_awaddr, output logic [3:0] lsu_axi_awregion, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_awsize, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_awburst, output logic lsu_axi_awlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_awcache, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_awprot, output logic [3:0] lsu_axi_awqos, + /*verilator coverage_on*/ output logic lsu_axi_wvalid, input logic lsu_axi_wready, @@ -121,7 +130,10 @@ import el2_pkg::*; output logic lsu_axi_wlast, input logic lsu_axi_bvalid, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic lsu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] lsu_axi_bresp, input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, @@ -131,16 +143,28 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, output logic [31:0] lsu_axi_araddr, output logic [3:0] lsu_axi_arregion, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_arsize, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_arburst, output logic lsu_axi_arlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_arcache, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_arprot, output logic [3:0] lsu_axi_arqos, + /*verilator coverage_on*/ input logic lsu_axi_rvalid, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic lsu_axi_rready, + /*verilator coverage_on*/ input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid, input logic [63:0] lsu_axi_rdata, input logic [1:0] lsu_axi_rresp, diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv index 2efcbfe81..71622e92f 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv @@ -102,13 +102,22 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, output logic [31:0] lsu_axi_awaddr, output logic [3:0] lsu_axi_awregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_awsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_awburst, output logic lsu_axi_awlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_awcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_awprot, output logic [3:0] lsu_axi_awqos, + /*verilator coverage_on*/ output logic lsu_axi_wvalid, input logic lsu_axi_wready, @@ -117,7 +126,10 @@ import el2_pkg::*; output logic lsu_axi_wlast, input logic lsu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] lsu_axi_bresp, input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, @@ -127,16 +139,28 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, output logic [31:0] lsu_axi_araddr, output logic [3:0] lsu_axi_arregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_arsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_arburst, output logic lsu_axi_arlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_arcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_arprot, output logic [3:0] lsu_axi_arqos, + /*verilator coverage_on*/ input logic lsu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_rready, + /*verilator coverage_on*/ input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid, input logic [63:0] lsu_axi_rdata, input logic [1:0] lsu_axi_rresp, diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv index 374e28e55..83bf5a90a 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv @@ -1,5 +1,6 @@ // SPDX-License-Identifier: Apache-2.0 // Copyright 2020 Western Digital Corporation or its affiliates. +// Copyright (c) 2023 Antmicro // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -26,10 +27,8 @@ // // //******************************************************************************** - - module el2_lsu_dccm_mem -import el2_pkg::*; + import el2_pkg::*; #( `include "el2_param.vh" )( @@ -46,8 +45,7 @@ import el2_pkg::*; input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data - - el2_mem_if.veer_dccm dccm_mem_export, // RAM repositioned in testbench and connected by this interface + el2_mem_if.veer_dccm dccm_mem_export, // RAM repositioned in testbench and connected by this interface output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank @@ -99,15 +97,17 @@ import el2_pkg::*; // clock gating section assign dccm_clken[i] = (wren_bank[i] | rden_bank[i] | clk_override) ; // end clock gating section - - // Connect to exported RAM Banks - always_comb begin - dccm_mem_export.dccm_clken[i] = dccm_clken[i]; - dccm_mem_export.dccm_wren_bank[i] = wren_bank[i]; - dccm_mem_export.dccm_addr_bank[i] = addr_bank[i]; - dccm_mem_export.dccm_wr_data_bank[i] = wr_data_bank[i]; - dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0] = dccm_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]; - end + + // Connect to exported RAM Banks + always_comb begin + dccm_mem_export.dccm_clken[i] = dccm_clken[i]; + dccm_mem_export.dccm_wren_bank[i] = wren_bank[i]; + dccm_mem_export.dccm_addr_bank[i] = addr_bank[i]; + dccm_mem_export.dccm_wr_data_bank[i] = wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]; + dccm_mem_export.dccm_wr_ecc_bank[i] = wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:pt.DCCM_DATA_WIDTH]; + dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0] = dccm_mem_export.dccm_bank_dout[i]; + dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:pt.DCCM_DATA_WIDTH] = dccm_mem_export.dccm_bank_ecc[i]; + end end : mem_bank @@ -115,7 +115,6 @@ import el2_pkg::*; rvdff #(pt.DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS]), .clk(active_clk)); rvdff #(pt.DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS]), .clk(active_clk)); - endmodule // el2_lsu_dccm_mem diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv index 80bf8fb6e..75d95acda 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv @@ -111,6 +111,9 @@ import el2_pkg::*; output el2_lsu_pkt_t lsu_pkt_m, output el2_lsu_pkt_t lsu_pkt_r, + input logic lsu_pmp_error_start, + input logic lsu_pmp_error_end, + input logic scan_mode // Scan mode ); @@ -256,17 +259,17 @@ import el2_pkg::*; // this is really R stage signal assign lsu_result_m[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_r[7:0]}) | - ({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_r[15:0]}) | - ({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_r[7]}}, lsu_ld_datafn_r[7:0]}) | - ({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_r[15]}},lsu_ld_datafn_r[15:0]}) | - ({32{lsu_pkt_r.word}} & lsu_ld_datafn_r[31:0]); + ({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_r[15:0]}) | + ({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_r[7]}}, lsu_ld_datafn_r[7:0]}) | + ({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_r[15]}},lsu_ld_datafn_r[15:0]}) | + ({32{lsu_pkt_r.word}} & lsu_ld_datafn_r[31:0]); // this signal is used for gpr update assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) | - ({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_corr_r[15:0]}) | - ({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]}) | - ({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_corr_r[15]}},lsu_ld_datafn_corr_r[15:0]}) | - ({32{lsu_pkt_r.word}} & lsu_ld_datafn_corr_r[31:0]); + ({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_corr_r[15:0]}) | + ({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]}) | + ({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_corr_r[15]}},lsu_ld_datafn_corr_r[15:0]}) | + ({32{lsu_pkt_r.word}} & lsu_ld_datafn_corr_r[31:0]); end else begin: L2U1_Plus1_0 // block: L2U1_Plus1_1 logic [31:0] lsu_ld_datafn_m, lsu_ld_datafn_corr_r; @@ -276,17 +279,17 @@ import el2_pkg::*; // this result must look at prior stores and merge them in assign lsu_result_m[31:0] = ({32{ lsu_pkt_m.unsign & lsu_pkt_m.by }} & {24'b0,lsu_ld_datafn_m[7:0]}) | - ({32{ lsu_pkt_m.unsign & lsu_pkt_m.half}} & {16'b0,lsu_ld_datafn_m[15:0]}) | - ({32{~lsu_pkt_m.unsign & lsu_pkt_m.by }} & {{24{ lsu_ld_datafn_m[7]}}, lsu_ld_datafn_m[7:0]}) | - ({32{~lsu_pkt_m.unsign & lsu_pkt_m.half}} & {{16{ lsu_ld_datafn_m[15]}},lsu_ld_datafn_m[15:0]}) | - ({32{lsu_pkt_m.word}} & lsu_ld_datafn_m[31:0]); + ({32{ lsu_pkt_m.unsign & lsu_pkt_m.half}} & {16'b0,lsu_ld_datafn_m[15:0]}) | + ({32{~lsu_pkt_m.unsign & lsu_pkt_m.by }} & {{24{ lsu_ld_datafn_m[7]}}, lsu_ld_datafn_m[7:0]}) | + ({32{~lsu_pkt_m.unsign & lsu_pkt_m.half}} & {{16{ lsu_ld_datafn_m[15]}},lsu_ld_datafn_m[15:0]}) | + ({32{lsu_pkt_m.word}} & lsu_ld_datafn_m[31:0]); // this signal is used for gpr update assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) | - ({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_corr_r[15:0]}) | - ({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]}) | - ({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_corr_r[15]}},lsu_ld_datafn_corr_r[15:0]}) | - ({32{lsu_pkt_r.word}} & lsu_ld_datafn_corr_r[31:0]); + ({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_corr_r[15:0]}) | + ({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]}) | + ({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_corr_r[15]}},lsu_ld_datafn_corr_r[15:0]}) | + ({32{lsu_pkt_r.word}} & lsu_ld_datafn_corr_r[31:0]); end // Fast interrupt address diff --git a/src/riscv_core/veer_el2/rtl/riscv_rev_info b/src/riscv_core/veer_el2/rtl/riscv_rev_info new file mode 100644 index 000000000..275dc24c4 --- /dev/null +++ b/src/riscv_core/veer_el2/rtl/riscv_rev_info @@ -0,0 +1,8 @@ +commit ad30bae95f921c7356abebaf9f1f65230c5c7b9f +Merge: d4e359372f8 0ec4c4d5db0 +Author: Tomasz Michalak +Date: Thu Oct 24 13:13:26 2024 +0200 + + Merge pull request #253 from chipsalliance/wsip/ci_fix + + CI fix: use docker image diff --git a/src/soc_ifc/config/soc_ifc_tb.vf b/src/soc_ifc/config/soc_ifc_tb.vf index 0bb6c17fd..8c79918fb 100644 --- a/src/soc_ifc/config/soc_ifc_tb.vf +++ b/src/soc_ifc/config/soc_ifc_tb.vf @@ -10,6 +10,7 @@ +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/tb +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include +incdir+${CALIPTRA_ROOT}/src/sha512/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh diff --git a/src/soc_ifc/config/soc_ifc_top.vf b/src/soc_ifc/config/soc_ifc_top.vf index 66bec0f70..fcc93a0c9 100644 --- a/src/soc_ifc/config/soc_ifc_top.vf +++ b/src/soc_ifc/config/soc_ifc_top.vf @@ -8,6 +8,7 @@ +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include +incdir+${CALIPTRA_ROOT}/src/sha512/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh @@ -84,6 +85,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv @@ -91,8 +94,6 @@ ${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv diff --git a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf index bf8fff797..18e96e77b 100644 --- a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf +++ b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf @@ -46,6 +46,7 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include +incdir+${CALIPTRA_ROOT}/src/sha512/rtl ${UVM_HOME}/src/uvm_pkg.sv ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh @@ -202,6 +203,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv @@ -209,8 +212,6 @@ ${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv diff --git a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf index 830cb5d1e..2ce15aaba 100644 --- a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf +++ b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf @@ -41,6 +41,7 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include +incdir+${CALIPTRA_ROOT}/src/sha512/rtl ${UVM_HOME}/src/uvm_pkg.sv ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh @@ -190,6 +191,8 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv @@ -197,8 +200,6 @@ ${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv diff --git a/tools/scripts/veer_build_command.sh b/tools/scripts/veer_build_command.sh index 7b7745434..ce2132742 100644 --- a/tools/scripts/veer_build_command.sh +++ b/tools/scripts/veer_build_command.sh @@ -22,14 +22,9 @@ # cd Cores-VeeR-EL2 # 2. in the shell, run: # export RV_ROOT=${PWD} -# 3. edit Cores-VeeR-EL2/configs/veer.config, line 841 -# change -# "reset_vec" => "0x80000000", # Testbench, Overridable -# to -# "reset_vec" => "0x00000000", # Testbench, Overridable -# 4. Run this script with 1 argument : name of snapshot to use +# 3. Run this script with 1 argument : name of snapshot to use # source /veer_build_command.sh -# 5. AFTER this script completes, you can merge contents into Caliptra repo +# 4. AFTER this script completes, you can merge contents into Caliptra repo # (Output files will be located in $RV_ROOT/snapshots/) ######################################################################## if [[ -z ${RV_ROOT+"empty"} ]]; then @@ -42,7 +37,6 @@ if [[ $# -ne 1 ]]; then fi $RV_ROOT/configs/veer.config \ -target=default_ahb \ ---iccm_region=0x4 \ -set=ret_stack_size=8 \ -set=btb_enable=1 \ -set=btb_fullya=0 \ @@ -57,7 +51,6 @@ $RV_ROOT/configs/veer.config \ -set=dccm_size=128 \ -set=dma_buf_depth=5 \ -set=fast_interrupt_redirect=1 \ --set=iccm_enable=1 \ -set=icache_enable=0 \ -set=icache_waypack=1 \ -set=icache_ecc=1 \ @@ -68,9 +61,11 @@ $RV_ROOT/configs/veer.config \ -set=icache_num_bypass=2 \ -set=icache_num_tag_bypass=2 \ -set=icache_tag_bypass_enable=1 \ +-set=iccm_enable=1 \ +-set=iccm_num_banks=4 \ +-set=iccm_region=0x4 \ -set=iccm_offset=0x0 \ -set=iccm_size=128 \ --set=iccm_num_banks=4 \ -set=lsu_stbuf_depth=4 \ -set=lsu_num_nbload=4 \ -set=load_to_use_plus1=0 \ @@ -89,6 +84,10 @@ $RV_ROOT/configs/veer.config \ -set=bitmanip_zbp=0 \ -set=bitmanip_zbr=0 \ -set=bitmanip_zbs=1 \ +-set=user_mode=1 \ +-set=pmp_entries=64 \ +-set=smepmp=1 \ +-set=reset_vec=0x00000000 \ -fpga_optimize=0 \ -snapshot=$1 #-text_in_iccm=0