From 19dbece0f44d19d29818d5090a30281a5a982ee5 Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Fri, 6 Dec 2024 21:01:06 -0800 Subject: [PATCH] Interface binding --- include/Surelog/Design/ModuleInstance.h | 1 + src/DesignCompile/CompileFileContent.cpp | 6 +- src/DesignCompile/DesignElaboration.cpp | 3 + tests/AssertDelayError/AssertDelayError.log | 798 +------- tests/AssertTempError/AssertTempError.log | 618 +----- tests/BindStmt2/BindStmt2.log | 197 +- tests/BindingPort/BindingPort.log | 103 +- tests/InterfaceBinding/InterfaceBinding.log | 1705 +++++++++++++++++ tests/InterfaceBinding/InterfaceBinding.sl | 1 + tests/InterfaceBinding/dut.sv | 42 + third_party/UHDM | 2 +- .../tests/CoresSweRVMP/CoresSweRVMP.log | 6 +- third_party/tests/SimpleUVM/SimpleUVM.log | 35 +- 13 files changed, 1982 insertions(+), 1535 deletions(-) create mode 100644 tests/InterfaceBinding/InterfaceBinding.log create mode 100644 tests/InterfaceBinding/InterfaceBinding.sl create mode 100644 tests/InterfaceBinding/dut.sv diff --git a/include/Surelog/Design/ModuleInstance.h b/include/Surelog/Design/ModuleInstance.h index 630e7e1d57..f0eab34361 100644 --- a/include/Surelog/Design/ModuleInstance.h +++ b/include/Surelog/Design/ModuleInstance.h @@ -83,6 +83,7 @@ class ModuleInstance final : public ValuedComponentI { } } ModuleInstance* getParent() const { return m_parent; } + void setParent(ModuleInstance* parent) { m_parent = parent; } const FileContent* getFileContent() const { return m_fileContent; } PathId getFileId() const; NodeId getNodeId() const { return m_nodeId; } diff --git a/src/DesignCompile/CompileFileContent.cpp b/src/DesignCompile/CompileFileContent.cpp index 994aa1a913..02783c1496 100644 --- a/src/DesignCompile/CompileFileContent.cpp +++ b/src/DesignCompile/CompileFileContent.cpp @@ -108,8 +108,10 @@ bool CompileFileContent::collectObjects_() { break; } case VObjectType::paBind_directive: { - m_helper.compileBindStmt(m_fileContent, fC, id, m_compileDesign, - nullptr); + if (!m_declOnly) { + m_helper.compileBindStmt(m_fileContent, fC, id, m_compileDesign, + nullptr); + } break; } case VObjectType::paParameter_declaration: { diff --git a/src/DesignCompile/DesignElaboration.cpp b/src/DesignCompile/DesignElaboration.cpp index dfaf419d9b..498be7140b 100644 --- a/src/DesignCompile/DesignElaboration.cpp +++ b/src/DesignCompile/DesignElaboration.cpp @@ -660,6 +660,9 @@ ModuleInstance* DesignElaboration::createBindInstance_( if (instance) { std::vector parentSubInstances; instance->setInstanceBinding(parent); + if (instance->getParent() == nullptr) { + instance->setParent(parent); + } NodeId parameterOverloading = fC->Sibling(bindNodeId); if (fC->Type(parameterOverloading) == VObjectType::paHierarchical_instance) { diff --git a/tests/AssertDelayError/AssertDelayError.log b/tests/AssertDelayError/AssertDelayError.log index 90d69edc2f..48868dda16 100644 --- a/tests/AssertDelayError/AssertDelayError.log +++ b/tests/AssertDelayError/AssertDelayError.log @@ -952,7 +952,7 @@ AST_DEBUG_END [NTE:EL0503] ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:2:1: Top level module "work@tb_left_rotation". [NTE:EL0508] Nb Top level modules: 1. [NTE:EL0509] Max instance depth: 2. -[NTE:EL0510] Nb instances: 4. +[NTE:EL0510] Nb instances: 3. [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === @@ -961,7 +961,7 @@ assert_stmt 3 assignment 11 begin 9 bit_select 1 -constant 89 +constant 71 delay_control 6 design 1 event_control 2 @@ -969,48 +969,48 @@ if_else 1 if_stmt 1 immediate_assert 1 initial 3 -logic_net 32 -logic_typespec 44 -module_inst 11 -operation 29 +logic_net 27 +logic_typespec 34 +module_inst 9 +operation 28 part_select 1 -port 27 +port 22 property_decl 3 property_spec 6 -range 35 +range 26 ref_module 1 -ref_obj 76 -ref_typespec 45 +ref_obj 67 +ref_typespec 35 repeat 1 sys_func_call 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === always 5 -assert_stmt 9 +assert_stmt 6 assignment 30 -begin 23 +begin 21 bit_select 2 -constant 89 +constant 71 delay_control 18 design 1 -event_control 5 +event_control 4 if_else 2 -if_stmt 3 -immediate_assert 3 -initial 8 -logic_net 32 -logic_typespec 44 -module_inst 11 -operation 81 +if_stmt 2 +immediate_assert 2 +initial 7 +logic_net 27 +logic_typespec 34 +module_inst 9 +operation 58 part_select 2 -port 41 -property_decl 9 -property_spec 18 -range 35 +port 31 +property_decl 6 +property_spec 12 +range 26 ref_module 1 -ref_obj 170 -ref_typespec 59 +ref_obj 131 +ref_typespec 44 repeat 3 sys_func_call 12 === UHDM Object Stats End === @@ -3483,601 +3483,6 @@ design: (work@tb_left_rotation) \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25 |vpiOperand: \_constant: , line:13:25, endln:13:26 - |vpiModule: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiParent: - \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7 - |vpiName:u_left_rotate_assertions - |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions - |vpiPropertyDecl: - \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation), line:18:12, endln:18:28 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiName:p_valid_rotation - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation - |vpiPropertySpec: - \_property_spec: , line:19:5, endln:19:98 - |vpiParent: - \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation), line:18:12, endln:18:28 - |vpiClockingEvent: - \_operation: , line:19:7, endln:19:18 - |vpiParent: - \_property_spec: , line:19:5, endln:19:98 - |vpiOpType:39 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.clk), line:19:15, endln:19:18 - |vpiParent: - \_operation: , line:19:7, endln:19:18 - |vpiName:clk - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.clk - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14 - |vpiPropertyExpr: - \_operation: , line:19:20, endln:19:98 - |vpiParent: - \_property_spec: , line:19:5, endln:19:98 - |vpiOpType:52 - |vpiOperand: - \_operation: , line:19:21, endln:19:27 - |vpiParent: - \_operation: , line:19:20, endln:19:98 - |vpiOpType:3 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rst_n), line:19:22, endln:19:27 - |vpiParent: - \_operation: , line:19:21, endln:19:27 - |vpiName:rst_n - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rst_n - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16 - |vpiOperand: - \_operation: , line:19:34, endln:19:97 - |vpiParent: - \_operation: , line:19:20, endln:19:98 - |vpiOpType:29 - |vpiOperand: - \_operation: , line:19:34, endln:19:67 - |vpiParent: - \_operation: , line:19:34, endln:19:97 - |vpiOpType:14 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotated), line:19:34, endln:19:41 - |vpiParent: - \_operation: , line:19:34, endln:19:67 - |vpiName:rotated - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotated - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25 - |vpiOperand: - \_operation: , line:19:46, endln:19:66 - |vpiParent: - \_operation: , line:19:34, endln:19:67 - |vpiOpType:22 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in), line:19:46, endln:19:53 - |vpiParent: - \_operation: , line:19:46, endln:19:66 - |vpiName:word_in - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by), line:19:57, endln:19:66 - |vpiParent: - \_operation: , line:19:46, endln:19:66 - |vpiName:rotate_by - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26 - |vpiOperand: - \_operation: , line:19:71, endln:19:96 - |vpiParent: - \_operation: , line:19:34, endln:19:97 - |vpiOpType:23 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in), line:19:71, endln:19:78 - |vpiParent: - \_operation: , line:19:71, endln:19:96 - |vpiName:word_in - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25 - |vpiOperand: - \_operation: , line:19:83, endln:19:95 - |vpiParent: - \_operation: , line:19:71, endln:19:96 - |vpiOpType:11 - |vpiOperand: - \_constant: , line:19:83, endln:19:85 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by), line:19:86, endln:19:95 - |vpiParent: - \_operation: , line:19:83, endln:19:95 - |vpiName:rotate_by - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26 - |vpiPropertyDecl: - \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range), line:24:12, endln:24:28 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiName:p_rotation_range - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range - |vpiPropertySpec: - \_property_spec: , line:25:5, endln:25:53 - |vpiParent: - \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range), line:24:12, endln:24:28 - |vpiClockingEvent: - \_operation: , line:25:7, endln:25:18 - |vpiParent: - \_property_spec: , line:25:5, endln:25:53 - |vpiOpType:39 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.clk), line:25:15, endln:25:18 - |vpiParent: - \_operation: , line:25:7, endln:25:18 - |vpiName:clk - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.clk - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14 - |vpiPropertyExpr: - \_operation: , line:25:20, endln:25:53 - |vpiParent: - \_property_spec: , line:25:5, endln:25:53 - |vpiOpType:52 - |vpiOperand: - \_operation: , line:25:21, endln:25:27 - |vpiParent: - \_operation: , line:25:20, endln:25:53 - |vpiOpType:3 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rst_n), line:25:22, endln:25:27 - |vpiParent: - \_operation: , line:25:21, endln:25:27 - |vpiName:rst_n - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rst_n - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16 - |vpiOperand: - \_operation: , line:25:34, endln:25:52 - |vpiParent: - \_operation: , line:25:20, endln:25:53 - |vpiOpType:21 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rotate_by), line:25:34, endln:25:43 - |vpiParent: - \_operation: , line:25:34, endln:25:52 - |vpiName:rotate_by - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rotate_by - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26 - |vpiOperand: - \_constant: , line:25:47, endln:25:52 - |vpiPropertyDecl: - \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation), line:30:12, endln:30:25 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiName:p_no_rotation - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation - |vpiPropertySpec: - \_property_spec: , line:31:5, endln:31:71 - |vpiParent: - \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation), line:30:12, endln:30:25 - |vpiClockingEvent: - \_operation: , line:31:7, endln:31:18 - |vpiParent: - \_property_spec: , line:31:5, endln:31:71 - |vpiOpType:39 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.clk), line:31:15, endln:31:18 - |vpiParent: - \_operation: , line:31:7, endln:31:18 - |vpiName:clk - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.clk - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14 - |vpiPropertyExpr: - \_operation: , line:31:20, endln:31:71 - |vpiParent: - \_property_spec: , line:31:5, endln:31:71 - |vpiOpType:52 - |vpiOperand: - \_operation: , line:31:21, endln:31:45 - |vpiParent: - \_operation: , line:31:20, endln:31:71 - |vpiOpType:26 - |vpiOperand: - \_operation: , line:31:21, endln:31:27 - |vpiParent: - \_operation: , line:31:21, endln:31:45 - |vpiOpType:3 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rst_n), line:31:22, endln:31:27 - |vpiParent: - \_operation: , line:31:21, endln:31:27 - |vpiName:rst_n - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rst_n - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16 - |vpiOperand: - \_operation: , line:31:31, endln:31:45 - |vpiParent: - \_operation: , line:31:21, endln:31:45 - |vpiOpType:14 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotate_by), line:31:31, endln:31:40 - |vpiParent: - \_operation: , line:31:31, endln:31:45 - |vpiName:rotate_by - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotate_by - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26 - |vpiOperand: - \_constant: , line:31:44, endln:31:45 - |vpiOperand: - \_operation: , line:31:52, endln:31:70 - |vpiParent: - \_operation: , line:31:20, endln:31:71 - |vpiOpType:14 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotated), line:31:52, endln:31:59 - |vpiParent: - \_operation: , line:31:52, endln:31:70 - |vpiName:rotated - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotated - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.word_in), line:31:63, endln:31:70 - |vpiParent: - \_operation: , line:31:52, endln:31:70 - |vpiName:word_in - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.word_in - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25 - |vpiDefName:work@left_rotate_assertions - |vpiDefFile:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv - |vpiDefLineNo:1 - |vpiNet: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiTypespec: - \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk) - |vpiParent: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk - |vpiActual: - \_logic_typespec: , line:2:11, endln:2:11 - |vpiName:clk - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk - |vpiNet: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiTypespec: - \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n) - |vpiParent: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n - |vpiActual: - \_logic_typespec: , line:3:11, endln:3:11 - |vpiName:rst_n - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n - |vpiNet: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiTypespec: - \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in) - |vpiParent: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in - |vpiActual: - \_logic_typespec: , line:4:11, endln:4:17 - |vpiName:word_in - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in - |vpiNet: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiTypespec: - \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by) - |vpiParent: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by - |vpiActual: - \_logic_typespec: , line:5:11, endln:5:16 - |vpiName:rotate_by - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by - |vpiNet: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiTypespec: - \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated) - |vpiParent: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated - |vpiActual: - \_logic_typespec: , line:6:11, endln:6:17 - |vpiName:rotated - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated - |vpiAssertion: - \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation), line:21:3, endln:21:55 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiName:a_valid_rotation - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation - |vpiProperty: - \_property_spec: , line:21:37, endln:21:53 - |vpiParent: - \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation), line:21:3, endln:21:55 - |vpiPropertyExpr: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation.p_valid_rotation), line:21:37, endln:21:53 - |vpiParent: - \_property_spec: , line:21:37, endln:21:53 - |vpiName:p_valid_rotation - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation.p_valid_rotation - |vpiActual: - \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation), line:18:12, endln:18:28 - |vpiAssertion: - \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range), line:27:3, endln:27:55 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiName:a_rotation_range - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range - |vpiProperty: - \_property_spec: , line:27:37, endln:27:53 - |vpiParent: - \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range), line:27:3, endln:27:55 - |vpiPropertyExpr: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range.p_rotation_range), line:27:37, endln:27:53 - |vpiParent: - \_property_spec: , line:27:37, endln:27:53 - |vpiName:p_rotation_range - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range.p_rotation_range - |vpiActual: - \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range), line:24:12, endln:24:28 - |vpiAssertion: - \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation), line:33:3, endln:33:49 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiName:a_no_rotation - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation - |vpiProperty: - \_property_spec: , line:33:34, endln:33:47 - |vpiParent: - \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation), line:33:3, endln:33:49 - |vpiPropertyExpr: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation.p_no_rotation), line:33:34, endln:33:47 - |vpiParent: - \_property_spec: , line:33:34, endln:33:47 - |vpiName:p_no_rotation - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation.p_no_rotation - |vpiActual: - \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation), line:30:12, endln:30:25 - |vpiInstance: - \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7 - |vpiPort: - \_port: (clk), line:2:11, endln:2:14 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiName:clk - |vpiDirection:1 - |vpiHighConn: - \_ref_obj: (work@tb_left_rotation.clk), line:38:10, endln:38:13 - |vpiParent: - \_port: (clk), line:2:11, endln:2:14 - |vpiName:clk - |vpiFullName:work@tb_left_rotation.clk - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14 - |vpiLowConn: - \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.clk), line:38:6, endln:38:9 - |vpiParent: - \_port: (clk), line:2:11, endln:2:14 - |vpiName:clk - |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.clk - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14 - |vpiTypedef: - \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk) - |vpiParent: - \_port: (clk), line:2:11, endln:2:14 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk - |vpiActual: - \_logic_typespec: , line:2:11, endln:2:11 - |vpiInstance: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiPort: - \_port: (rst_n), line:3:11, endln:3:16 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiName:rst_n - |vpiDirection:1 - |vpiHighConn: - \_ref_obj: (work@tb_left_rotation.reset), line:39:10, endln:39:15 - |vpiParent: - \_port: (rst_n), line:3:11, endln:3:16 - |vpiName:reset - |vpiFullName:work@tb_left_rotation.reset - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.reset), line:3:16, endln:3:21 - |vpiLowConn: - \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.rst_n), line:39:4, endln:39:9 - |vpiParent: - \_port: (rst_n), line:3:11, endln:3:16 - |vpiName:rst_n - |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.rst_n - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16 - |vpiTypedef: - \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n) - |vpiParent: - \_port: (rst_n), line:3:11, endln:3:16 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n - |vpiActual: - \_logic_typespec: , line:3:11, endln:3:11 - |vpiInstance: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiPort: - \_port: (word_in), line:4:18, endln:4:25 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiName:word_in - |vpiDirection:1 - |vpiHighConn: - \_ref_obj: (work@tb_left_rotation.in_data), line:40:12, endln:40:19 - |vpiParent: - \_port: (word_in), line:4:18, endln:4:25 - |vpiName:in_data - |vpiFullName:work@tb_left_rotation.in_data - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.in_data), line:4:22, endln:4:29 - |vpiLowConn: - \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.word_in), line:40:4, endln:40:11 - |vpiParent: - \_port: (word_in), line:4:18, endln:4:25 - |vpiName:word_in - |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.word_in - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25 - |vpiTypedef: - \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in) - |vpiParent: - \_port: (word_in), line:4:18, endln:4:25 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in - |vpiActual: - \_logic_typespec: , line:4:11, endln:4:17 - |vpiInstance: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiPort: - \_port: (rotate_by), line:5:17, endln:5:26 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiName:rotate_by - |vpiDirection:1 - |vpiHighConn: - \_operation: , line:41:16, endln:41:17 - |vpiParent: - \_port: (rotate_by), line:5:17, endln:5:26 - |vpiOpType:36 - |vpiLowConn: - \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26 - |vpiParent: - \_port: (rotate_by), line:5:17, endln:5:26 - |vpiName:rotate_by - |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.rotate_by - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26 - |vpiTypedef: - \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by) - |vpiParent: - \_port: (rotate_by), line:5:17, endln:5:26 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by - |vpiActual: - \_logic_typespec: , line:5:11, endln:5:16 - |vpiInstance: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiPort: - \_port: (rotated), line:6:18, endln:6:25 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiName:rotated - |vpiDirection:1 - |vpiHighConn: - \_ref_obj: (work@tb_left_rotation.out_data), line:42:12, endln:42:20 - |vpiParent: - \_port: (rotated), line:6:18, endln:6:25 - |vpiName:out_data - |vpiFullName:work@tb_left_rotation.out_data - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30 - |vpiLowConn: - \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.rotated), line:42:4, endln:42:11 - |vpiParent: - \_port: (rotated), line:6:18, endln:6:25 - |vpiName:rotated - |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.rotated - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25 - |vpiTypedef: - \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated) - |vpiParent: - \_port: (rotated), line:6:18, endln:6:25 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated - |vpiActual: - \_logic_typespec: , line:6:11, endln:6:17 - |vpiInstance: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiProcess: - \_initial: , line:10:3, endln:15:6 - |vpiParent: - \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3 - |vpiStmt: - \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:10:11, endln:15:6 - |vpiParent: - \_initial: , line:10:3, endln:15:6 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions - |vpiStmt: - \_event_control: , line:11:5, endln:11:19 - |vpiParent: - \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:10:11, endln:15:6 - |vpiCondition: - \_operation: , line:11:7, endln:11:18 - |vpiParent: - \_event_control: , line:11:5, endln:11:19 - |vpiOpType:39 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:11:15, endln:11:18 - |vpiParent: - \_operation: , line:11:7, endln:11:18 - |vpiName:clk - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14 - |vpiStmt: - \_if_stmt: , line:12:5, endln:14:8 - |vpiParent: - \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:10:11, endln:15:6 - |vpiCondition: - \_operation: , line:12:9, endln:12:15 - |vpiParent: - \_if_stmt: , line:12:5, endln:14:8 - |vpiOpType:3 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:12:10, endln:12:15 - |vpiParent: - \_operation: , line:12:9, endln:12:15 - |vpiName:rst_n - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16 - |vpiStmt: - \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:12:17, endln:14:8 - |vpiParent: - \_if_stmt: , line:12:5, endln:14:8 - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions - |vpiStmt: - \_immediate_assert: , line:13:7, endln:13:28 - |vpiParent: - \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:12:17, endln:14:8 - |vpiExpr: - \_operation: , line:13:14, endln:13:26 - |vpiParent: - \_immediate_assert: , line:13:7, endln:13:28 - |vpiOpType:14 - |vpiOperand: - \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:13:14, endln:13:21 - |vpiParent: - \_operation: , line:13:14, endln:13:26 - |vpiName:rotated - |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated - |vpiActual: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25 - |vpiOperand: - \_constant: , line:13:25, endln:13:26 \_weaklyReferenced: \_logic_typespec: , line:3:5, endln:3:8 |vpiParent: @@ -4366,146 +3771,6 @@ design: (work@tb_left_rotation) |vpiConstType:9 \_logic_typespec: , line:2:11, endln:2:11 \_logic_typespec: , line:3:11, endln:3:11 -\_logic_typespec: , line:4:11, endln:4:17 - |vpiRange: - \_range: , line:4:11, endln:4:17 - |vpiParent: - \_logic_typespec: , line:4:11, endln:4:17 - |vpiLeftRange: - \_constant: , line:4:12, endln:4:14 - |vpiParent: - \_range: , line:4:11, endln:4:17 - |vpiDecompile:31 - |vpiSize:64 - |UINT:31 - |vpiConstType:9 - |vpiRightRange: - \_constant: , line:4:15, endln:4:16 - |vpiParent: - \_range: , line:4:11, endln:4:17 - |vpiDecompile:0 - |vpiSize:64 - |UINT:0 - |vpiConstType:9 -\_logic_typespec: , line:5:11, endln:5:16 - |vpiRange: - \_range: , line:5:11, endln:5:16 - |vpiParent: - \_logic_typespec: , line:5:11, endln:5:16 - |vpiLeftRange: - \_constant: , line:5:12, endln:5:13 - |vpiParent: - \_range: , line:5:11, endln:5:16 - |vpiDecompile:4 - |vpiSize:64 - |UINT:4 - |vpiConstType:9 - |vpiRightRange: - \_constant: , line:5:14, endln:5:15 - |vpiParent: - \_range: , line:5:11, endln:5:16 - |vpiDecompile:0 - |vpiSize:64 - |UINT:0 - |vpiConstType:9 -\_logic_typespec: , line:6:11, endln:6:17 - |vpiRange: - \_range: , line:6:11, endln:6:17 - |vpiParent: - \_logic_typespec: , line:6:11, endln:6:17 - |vpiLeftRange: - \_constant: , line:6:12, endln:6:14 - |vpiParent: - \_range: , line:6:11, endln:6:17 - |vpiDecompile:31 - |vpiSize:64 - |UINT:31 - |vpiConstType:9 - |vpiRightRange: - \_constant: , line:6:15, endln:6:16 - |vpiParent: - \_range: , line:6:11, endln:6:17 - |vpiDecompile:0 - |vpiSize:64 - |UINT:0 - |vpiConstType:9 -\_logic_typespec: , line:2:11, endln:2:11 - |vpiParent: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14 -\_logic_typespec: , line:3:11, endln:3:11 - |vpiParent: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16 -\_logic_typespec: , line:4:11, endln:4:17 - |vpiParent: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25 - |vpiRange: - \_range: , line:4:11, endln:4:17 - |vpiParent: - \_logic_typespec: , line:4:11, endln:4:17 - |vpiLeftRange: - \_constant: , line:4:12, endln:4:14 - |vpiParent: - \_range: , line:4:11, endln:4:17 - |vpiDecompile:31 - |vpiSize:64 - |UINT:31 - |vpiConstType:9 - |vpiRightRange: - \_constant: , line:4:15, endln:4:16 - |vpiParent: - \_range: , line:4:11, endln:4:17 - |vpiDecompile:0 - |vpiSize:64 - |UINT:0 - |vpiConstType:9 -\_logic_typespec: , line:5:11, endln:5:16 - |vpiParent: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26 - |vpiRange: - \_range: , line:5:11, endln:5:16 - |vpiParent: - \_logic_typespec: , line:5:11, endln:5:16 - |vpiLeftRange: - \_constant: , line:5:12, endln:5:13 - |vpiParent: - \_range: , line:5:11, endln:5:16 - |vpiDecompile:4 - |vpiSize:64 - |UINT:4 - |vpiConstType:9 - |vpiRightRange: - \_constant: , line:5:14, endln:5:15 - |vpiParent: - \_range: , line:5:11, endln:5:16 - |vpiDecompile:0 - |vpiSize:64 - |UINT:0 - |vpiConstType:9 -\_logic_typespec: , line:6:11, endln:6:17 - |vpiParent: - \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25 - |vpiRange: - \_range: , line:6:11, endln:6:17 - |vpiParent: - \_logic_typespec: , line:6:11, endln:6:17 - |vpiLeftRange: - \_constant: , line:6:12, endln:6:14 - |vpiParent: - \_range: , line:6:11, endln:6:17 - |vpiDecompile:31 - |vpiSize:64 - |UINT:31 - |vpiConstType:9 - |vpiRightRange: - \_constant: , line:6:15, endln:6:16 - |vpiParent: - \_range: , line:6:11, endln:6:17 - |vpiDecompile:0 - |vpiSize:64 - |UINT:0 - |vpiConstType:9 -\_logic_typespec: , line:2:11, endln:2:11 -\_logic_typespec: , line:3:11, endln:3:11 \_logic_typespec: , line:4:11, endln:4:17 |vpiRange: \_range: , line:4:11, endln:4:17 @@ -4695,13 +3960,4 @@ design: (work@tb_left_rotation) [LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:21:37: Non synthesizable construct, [LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:27:37: Non synthesizable construct, [LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:33:34: Non synthesizable construct, -[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:19:5: Non synthesizable construct, -[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:18:12: Non synthesizable construct, p_valid_rotation -[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:25:5: Non synthesizable construct, -[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:24:12: Non synthesizable construct, p_rotation_range -[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:31:5: Non synthesizable construct, -[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:30:12: Non synthesizable construct, p_no_rotation -[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:21:37: Non synthesizable construct, -[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:27:37: Non synthesizable construct, -[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:33:34: Non synthesizable construct, ============================== End Linting Results ============================== diff --git a/tests/AssertTempError/AssertTempError.log b/tests/AssertTempError/AssertTempError.log index e0d0fae7cf..c104cccd93 100644 --- a/tests/AssertTempError/AssertTempError.log +++ b/tests/AssertTempError/AssertTempError.log @@ -1477,8 +1477,8 @@ AST_DEBUG_END [NTE:EL0503] ${SURELOG_DIR}/tests/AssertTempError/testbench.sv:3:1: Top level module "work@tb_UART". [NTE:EL0508] Nb Top level modules: 1. [NTE:EL0509] Max instance depth: 2. -[NTE:EL0510] Nb instances: 4. -[NTE:EL0511] Nb leaf instances: 2. +[NTE:EL0510] Nb instances: 3. +[NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 3 @@ -1488,27 +1488,27 @@ begin 15 bit_select 2 case_item 4 case_stmt 1 -constant 106 +constant 94 delay_control 6 design 1 event_control 2 if_else 2 if_stmt 2 initial 1 -int_typespec 20 -logic_net 54 -logic_typespec 64 -module_inst 12 +int_typespec 16 +logic_net 49 +logic_typespec 55 +module_inst 10 operation 24 -param_assign 20 -parameter 20 -port 33 +param_assign 16 +parameter 16 +port 29 property_decl 2 property_spec 4 -range 23 +range 21 ref_module 1 -ref_obj 124 -ref_typespec 120 +ref_obj 116 +ref_typespec 99 repeat 1 sys_func_call 6 while_stmt 1 @@ -1516,35 +1516,35 @@ while_stmt 1 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === always 7 -assert_stmt 6 +assert_stmt 4 assignment 74 begin 33 bit_select 4 case_item 8 case_stmt 2 -constant 106 +constant 94 delay_control 18 design 1 event_control 4 if_else 4 if_stmt 4 initial 3 -int_typespec 20 -logic_net 54 -logic_typespec 64 -module_inst 12 -operation 57 -param_assign 20 -parameter 20 -port 48 -property_decl 6 -property_spec 12 -range 23 +int_typespec 16 +logic_net 49 +logic_typespec 55 +module_inst 10 +operation 51 +param_assign 16 +parameter 16 +port 40 +property_decl 4 +property_spec 8 +range 21 ref_module 1 -ref_obj 253 -ref_typespec 135 +ref_obj 227 +ref_typespec 110 repeat 3 -sys_func_call 18 +sys_func_call 16 while_stmt 3 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/AssertTempError/slpp_all/surelog.uhdm ... @@ -5974,509 +5974,6 @@ design: (work@tb_UART) \_logic_typespec: , line:74:11, endln:74:11 |vpiInstance: \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiModule: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiParent: - \_module_inst: work@UART (work@tb_UART.uart_inst), file:${SURELOG_DIR}/tests/AssertTempError/testbench.sv, line:10:5, endln:18:7 - |vpiName:uut - |vpiFullName:work@tb_UART.uut - |vpiPropertyDecl: - \_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiName:p_send - |vpiFullName:work@tb_UART.uart_inst.uut.p_send - |vpiPropertySpec: - \_property_spec: , line:83:9, endln:84:33 - |vpiParent: - \_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20 - |vpiClockingEvent: - \_operation: , line:83:11, endln:83:22 - |vpiParent: - \_property_spec: , line:83:9, endln:84:33 - |vpiOpType:39 - |vpiOperand: - \_ref_obj: (work@tb_UART.uart_inst.uut.p_send.clk), line:83:19, endln:83:22 - |vpiParent: - \_operation: , line:83:11, endln:83:22 - |vpiName:clk - |vpiFullName:work@tb_UART.uart_inst.uut.p_send.clk - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.clk), line:71:11, endln:71:14 - |vpiPropertyExpr: - \_operation: , line:84:9, endln:84:33 - |vpiParent: - \_property_spec: , line:83:9, endln:84:33 - |vpiOpType:51 - |vpiOperand: - \_ref_obj: (work@tb_UART.uart_inst.uut.p_send.send), line:84:9, endln:84:13 - |vpiParent: - \_operation: , line:84:9, endln:84:33 - |vpiName:send - |vpiFullName:work@tb_UART.uart_inst.uut.p_send.send - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.send), line:73:11, endln:73:15 - |vpiOperand: - \_operation: , line:84:19, endln:84:32 - |vpiParent: - \_operation: , line:84:9, endln:84:33 - |vpiOpType:14 - |vpiOperand: - \_ref_obj: (work@tb_UART.uart_inst.uut.p_send.state), line:84:19, endln:84:24 - |vpiParent: - \_operation: , line:84:19, endln:84:32 - |vpiName:state - |vpiFullName:work@tb_UART.uart_inst.uut.p_send.state - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.state), line:78:13, endln:78:18 - |vpiOperand: - \_ref_obj: (work@tb_UART.uart_inst.uut.p_send.DATA), line:84:28, endln:84:32 - |vpiParent: - \_operation: , line:84:19, endln:84:32 - |vpiName:DATA - |vpiFullName:work@tb_UART.uart_inst.uut.p_send.DATA - |vpiActual: - \_parameter: (work@tb_UART.uart_inst.uut.DATA), line:79:36, endln:79:40 - |vpiPropertyDecl: - \_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiName:p_done - |vpiFullName:work@tb_UART.uart_inst.uut.p_done - |vpiPropertySpec: - \_property_spec: , line:91:9, endln:92:33 - |vpiParent: - \_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20 - |vpiClockingEvent: - \_operation: , line:91:11, endln:91:22 - |vpiParent: - \_property_spec: , line:91:9, endln:92:33 - |vpiOpType:39 - |vpiOperand: - \_ref_obj: (work@tb_UART.uart_inst.uut.p_done.clk), line:91:19, endln:91:22 - |vpiParent: - \_operation: , line:91:11, endln:91:22 - |vpiName:clk - |vpiFullName:work@tb_UART.uart_inst.uut.p_done.clk - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.clk), line:71:11, endln:71:14 - |vpiPropertyExpr: - \_operation: , line:92:9, endln:92:33 - |vpiParent: - \_property_spec: , line:91:9, endln:92:33 - |vpiOpType:51 - |vpiOperand: - \_ref_obj: (work@tb_UART.uart_inst.uut.p_done.done), line:92:9, endln:92:13 - |vpiParent: - \_operation: , line:92:9, endln:92:33 - |vpiName:done - |vpiFullName:work@tb_UART.uart_inst.uut.p_done.done - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.done), line:74:11, endln:74:15 - |vpiOperand: - \_operation: , line:92:19, endln:92:32 - |vpiParent: - \_operation: , line:92:9, endln:92:33 - |vpiOpType:14 - |vpiOperand: - \_ref_obj: (work@tb_UART.uart_inst.uut.p_done.state), line:92:19, endln:92:24 - |vpiParent: - \_operation: , line:92:19, endln:92:32 - |vpiName:state - |vpiFullName:work@tb_UART.uart_inst.uut.p_done.state - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.state), line:78:13, endln:78:18 - |vpiOperand: - \_ref_obj: (work@tb_UART.uart_inst.uut.p_done.STOP), line:92:28, endln:92:32 - |vpiParent: - \_operation: , line:92:19, endln:92:32 - |vpiName:STOP - |vpiFullName:work@tb_UART.uart_inst.uut.p_done.STOP - |vpiActual: - \_parameter: (work@tb_UART.uart_inst.uut.STOP), line:79:46, endln:79:50 - |vpiParameter: - \_parameter: (work@tb_UART.uart_inst.uut.IDLE), line:79:15, endln:79:19 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |UINT:0 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut.IDLE) - |vpiParent: - \_parameter: (work@tb_UART.uart_inst.uut.IDLE), line:79:15, endln:79:19 - |vpiFullName:work@tb_UART.uart_inst.uut.IDLE - |vpiActual: - \_int_typespec: , line:79:5, endln:79:54 - |vpiName:IDLE - |vpiFullName:work@tb_UART.uart_inst.uut.IDLE - |vpiParameter: - \_parameter: (work@tb_UART.uart_inst.uut.START), line:79:25, endln:79:30 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |UINT:1 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut.START) - |vpiParent: - \_parameter: (work@tb_UART.uart_inst.uut.START), line:79:25, endln:79:30 - |vpiFullName:work@tb_UART.uart_inst.uut.START - |vpiActual: - \_int_typespec: , line:79:5, endln:79:54 - |vpiName:START - |vpiFullName:work@tb_UART.uart_inst.uut.START - |vpiParameter: - \_parameter: (work@tb_UART.uart_inst.uut.DATA), line:79:36, endln:79:40 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |UINT:2 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut.DATA) - |vpiParent: - \_parameter: (work@tb_UART.uart_inst.uut.DATA), line:79:36, endln:79:40 - |vpiFullName:work@tb_UART.uart_inst.uut.DATA - |vpiActual: - \_int_typespec: , line:79:5, endln:79:54 - |vpiName:DATA - |vpiFullName:work@tb_UART.uart_inst.uut.DATA - |vpiParameter: - \_parameter: (work@tb_UART.uart_inst.uut.STOP), line:79:46, endln:79:50 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |UINT:3 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut.STOP) - |vpiParent: - \_parameter: (work@tb_UART.uart_inst.uut.STOP), line:79:46, endln:79:50 - |vpiFullName:work@tb_UART.uart_inst.uut.STOP - |vpiActual: - \_int_typespec: , line:79:5, endln:79:54 - |vpiName:STOP - |vpiFullName:work@tb_UART.uart_inst.uut.STOP - |vpiParamAssign: - \_param_assign: , line:79:15, endln:79:23 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiRhs: - \_constant: , line:79:22, endln:79:23 - |vpiParent: - \_param_assign: , line:79:15, endln:79:23 - |vpiDecompile:0 - |vpiSize:32 - |UINT:0 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut) - |vpiParent: - \_constant: , line:79:22, endln:79:23 - |vpiFullName:work@tb_UART.uart_inst.uut - |vpiActual: - \_int_typespec: , line:79:5, endln:79:54 - |vpiConstType:9 - |vpiLhs: - \_parameter: (work@tb_UART.uart_inst.uut.IDLE), line:79:15, endln:79:19 - |vpiParamAssign: - \_param_assign: , line:79:25, endln:79:34 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiRhs: - \_constant: , line:79:33, endln:79:34 - |vpiParent: - \_param_assign: , line:79:25, endln:79:34 - |vpiDecompile:1 - |vpiSize:32 - |UINT:1 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut) - |vpiParent: - \_constant: , line:79:33, endln:79:34 - |vpiFullName:work@tb_UART.uart_inst.uut - |vpiActual: - \_int_typespec: , line:79:5, endln:79:54 - |vpiConstType:9 - |vpiLhs: - \_parameter: (work@tb_UART.uart_inst.uut.START), line:79:25, endln:79:30 - |vpiParamAssign: - \_param_assign: , line:79:36, endln:79:44 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiRhs: - \_constant: , line:79:43, endln:79:44 - |vpiParent: - \_param_assign: , line:79:36, endln:79:44 - |vpiDecompile:2 - |vpiSize:32 - |UINT:2 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut) - |vpiParent: - \_constant: , line:79:43, endln:79:44 - |vpiFullName:work@tb_UART.uart_inst.uut - |vpiActual: - \_int_typespec: , line:79:5, endln:79:54 - |vpiConstType:9 - |vpiLhs: - \_parameter: (work@tb_UART.uart_inst.uut.DATA), line:79:36, endln:79:40 - |vpiParamAssign: - \_param_assign: , line:79:46, endln:79:54 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiRhs: - \_constant: , line:79:53, endln:79:54 - |vpiParent: - \_param_assign: , line:79:46, endln:79:54 - |vpiDecompile:3 - |vpiSize:32 - |UINT:3 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut) - |vpiParent: - \_constant: , line:79:53, endln:79:54 - |vpiFullName:work@tb_UART.uart_inst.uut - |vpiActual: - \_int_typespec: , line:79:5, endln:79:54 - |vpiConstType:9 - |vpiLhs: - \_parameter: (work@tb_UART.uart_inst.uut.STOP), line:79:46, endln:79:50 - |vpiDefName:work@UART_assertions - |vpiDefFile:${SURELOG_DIR}/tests/AssertTempError/design.sv - |vpiDefLineNo:70 - |vpiNet: - \_logic_net: (work@tb_UART.uart_inst.uut.clk), line:71:11, endln:71:14 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut.clk) - |vpiParent: - \_logic_net: (work@tb_UART.uart_inst.uut.clk), line:71:11, endln:71:14 - |vpiFullName:work@tb_UART.uart_inst.uut.clk - |vpiActual: - \_logic_typespec: , line:71:11, endln:71:11 - |vpiName:clk - |vpiFullName:work@tb_UART.uart_inst.uut.clk - |vpiNet: - \_logic_net: (work@tb_UART.uart_inst.uut.rst_n), line:72:11, endln:72:16 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut.rst_n) - |vpiParent: - \_logic_net: (work@tb_UART.uart_inst.uut.rst_n), line:72:11, endln:72:16 - |vpiFullName:work@tb_UART.uart_inst.uut.rst_n - |vpiActual: - \_logic_typespec: , line:72:11, endln:72:11 - |vpiName:rst_n - |vpiFullName:work@tb_UART.uart_inst.uut.rst_n - |vpiNet: - \_logic_net: (work@tb_UART.uart_inst.uut.send), line:73:11, endln:73:15 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut.send) - |vpiParent: - \_logic_net: (work@tb_UART.uart_inst.uut.send), line:73:11, endln:73:15 - |vpiFullName:work@tb_UART.uart_inst.uut.send - |vpiActual: - \_logic_typespec: , line:73:11, endln:73:11 - |vpiName:send - |vpiFullName:work@tb_UART.uart_inst.uut.send - |vpiNet: - \_logic_net: (work@tb_UART.uart_inst.uut.done), line:74:11, endln:74:15 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut.done) - |vpiParent: - \_logic_net: (work@tb_UART.uart_inst.uut.done), line:74:11, endln:74:15 - |vpiFullName:work@tb_UART.uart_inst.uut.done - |vpiActual: - \_logic_typespec: , line:74:11, endln:74:11 - |vpiName:done - |vpiFullName:work@tb_UART.uart_inst.uut.done - |vpiNet: - \_logic_net: (work@tb_UART.uart_inst.uut.state), line:78:13, endln:78:18 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiTypespec: - \_ref_typespec: (work@tb_UART.uart_inst.uut.state) - |vpiParent: - \_logic_net: (work@tb_UART.uart_inst.uut.state), line:78:13, endln:78:18 - |vpiFullName:work@tb_UART.uart_inst.uut.state - |vpiActual: - \_logic_typespec: , line:78:3, endln:78:12 - |vpiName:state - |vpiFullName:work@tb_UART.uart_inst.uut.state - |vpiNetType:48 - |vpiAssertion: - \_assert_stmt: (work@tb_UART.uart_inst.uut), line:87:4, endln:87:69 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiFullName:work@tb_UART.uart_inst.uut - |vpiStmt: - \_sys_func_call: ($display), line:87:34, endln:87:68 - |vpiParent: - \_assert_stmt: (work@tb_UART.uart_inst.uut), line:87:4, endln:87:69 - |vpiArgument: - \_constant: , line:87:43, endln:87:67 - |vpiName:$display - |vpiProperty: - \_property_spec: , line:87:21, endln:87:27 - |vpiParent: - \_assert_stmt: (work@tb_UART.uart_inst.uut), line:87:4, endln:87:69 - |vpiPropertyExpr: - \_ref_obj: (work@tb_UART.uart_inst.uut.p_send), line:87:21, endln:87:27 - |vpiParent: - \_property_spec: , line:87:21, endln:87:27 - |vpiName:p_send - |vpiFullName:work@tb_UART.uart_inst.uut.p_send - |vpiActual: - \_property_decl: (work@tb_UART.uart_inst.uut.p_send), line:82:14, endln:82:20 - |vpiAssertion: - \_assert_stmt: (work@tb_UART.uart_inst.uut), line:95:5, endln:95:70 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiFullName:work@tb_UART.uart_inst.uut - |vpiStmt: - \_sys_func_call: ($display), line:95:35, endln:95:69 - |vpiParent: - \_assert_stmt: (work@tb_UART.uart_inst.uut), line:95:5, endln:95:70 - |vpiArgument: - \_constant: , line:95:44, endln:95:68 - |vpiName:$display - |vpiProperty: - \_property_spec: , line:95:22, endln:95:28 - |vpiParent: - \_assert_stmt: (work@tb_UART.uart_inst.uut), line:95:5, endln:95:70 - |vpiPropertyExpr: - \_ref_obj: (work@tb_UART.uart_inst.uut.p_done), line:95:22, endln:95:28 - |vpiParent: - \_property_spec: , line:95:22, endln:95:28 - |vpiName:p_done - |vpiFullName:work@tb_UART.uart_inst.uut.p_done - |vpiActual: - \_property_decl: (work@tb_UART.uart_inst.uut.p_done), line:90:14, endln:90:20 - |vpiInstance: - \_module_inst: work@UART (work@tb_UART.uart_inst), file:${SURELOG_DIR}/tests/AssertTempError/testbench.sv, line:10:5, endln:18:7 - |vpiPort: - \_port: (clk), line:71:11, endln:71:14 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiName:clk - |vpiDirection:1 - |vpiHighConn: - \_ref_obj: (work@tb_UART.clk), line:100:36, endln:100:39 - |vpiParent: - \_port: (clk), line:71:11, endln:71:14 - |vpiName:clk - |vpiFullName:work@tb_UART.clk - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.clk), line:71:11, endln:71:14 - |vpiLowConn: - \_ref_obj: (work@tb_UART.uut.clk), line:100:32, endln:100:35 - |vpiParent: - \_port: (clk), line:71:11, endln:71:14 - |vpiName:clk - |vpiFullName:work@tb_UART.uut.clk - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.clk), line:71:11, endln:71:14 - |vpiTypedef: - \_ref_typespec: (work@tb_UART.uart_inst.uut.clk) - |vpiParent: - \_port: (clk), line:71:11, endln:71:14 - |vpiFullName:work@tb_UART.uart_inst.uut.clk - |vpiActual: - \_logic_typespec: , line:71:11, endln:71:11 - |vpiInstance: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiPort: - \_port: (rst_n), line:72:11, endln:72:16 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiName:rst_n - |vpiDirection:1 - |vpiHighConn: - \_ref_obj: (work@tb_UART.rst_n), line:100:48, endln:100:53 - |vpiParent: - \_port: (rst_n), line:72:11, endln:72:16 - |vpiName:rst_n - |vpiFullName:work@tb_UART.rst_n - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.rst_n), line:72:11, endln:72:16 - |vpiLowConn: - \_ref_obj: (work@tb_UART.uut.rst_n), line:100:42, endln:100:47 - |vpiParent: - \_port: (rst_n), line:72:11, endln:72:16 - |vpiName:rst_n - |vpiFullName:work@tb_UART.uut.rst_n - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.rst_n), line:72:11, endln:72:16 - |vpiTypedef: - \_ref_typespec: (work@tb_UART.uart_inst.uut.rst_n) - |vpiParent: - \_port: (rst_n), line:72:11, endln:72:16 - |vpiFullName:work@tb_UART.uart_inst.uut.rst_n - |vpiActual: - \_logic_typespec: , line:72:11, endln:72:11 - |vpiInstance: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiPort: - \_port: (send), line:73:11, endln:73:15 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiName:send - |vpiDirection:1 - |vpiHighConn: - \_ref_obj: (work@tb_UART.send), line:100:61, endln:100:65 - |vpiParent: - \_port: (send), line:73:11, endln:73:15 - |vpiName:send - |vpiFullName:work@tb_UART.send - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.send), line:73:11, endln:73:15 - |vpiLowConn: - \_ref_obj: (work@tb_UART.uut.send), line:100:56, endln:100:60 - |vpiParent: - \_port: (send), line:73:11, endln:73:15 - |vpiName:send - |vpiFullName:work@tb_UART.uut.send - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.send), line:73:11, endln:73:15 - |vpiTypedef: - \_ref_typespec: (work@tb_UART.uart_inst.uut.send) - |vpiParent: - \_port: (send), line:73:11, endln:73:15 - |vpiFullName:work@tb_UART.uart_inst.uut.send - |vpiActual: - \_logic_typespec: , line:73:11, endln:73:11 - |vpiInstance: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiPort: - \_port: (done), line:74:11, endln:74:15 - |vpiParent: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 - |vpiName:done - |vpiDirection:1 - |vpiHighConn: - \_ref_obj: (work@tb_UART.done), line:100:73, endln:100:77 - |vpiParent: - \_port: (done), line:74:11, endln:74:15 - |vpiName:done - |vpiFullName:work@tb_UART.done - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.done), line:74:11, endln:74:15 - |vpiLowConn: - \_ref_obj: (work@tb_UART.uut.done), line:100:68, endln:100:72 - |vpiParent: - \_port: (done), line:74:11, endln:74:15 - |vpiName:done - |vpiFullName:work@tb_UART.uut.done - |vpiActual: - \_logic_net: (work@tb_UART.uart_inst.uut.done), line:74:11, endln:74:15 - |vpiTypedef: - \_ref_typespec: (work@tb_UART.uart_inst.uut.done) - |vpiParent: - \_port: (done), line:74:11, endln:74:15 - |vpiFullName:work@tb_UART.uart_inst.uut.done - |vpiActual: - \_logic_typespec: , line:74:11, endln:74:11 - |vpiInstance: - \_module_inst: work@UART_assertions (work@tb_UART.uut), file:${SURELOG_DIR}/tests/AssertTempError/design.sv, line:100:11, endln:100:80 \_weaklyReferenced: \_int_typespec: , line:12:5, endln:12:54 \_int_typespec: , line:12:5, endln:12:54 @@ -6662,45 +6159,6 @@ design: (work@tb_UART) \_logic_typespec: , line:72:11, endln:72:11 \_logic_typespec: , line:73:11, endln:73:11 \_logic_typespec: , line:74:11, endln:74:11 -\_logic_typespec: , line:71:11, endln:71:11 - |vpiParent: - \_logic_net: (work@tb_UART.uart_inst.uut.clk), line:71:11, endln:71:14 -\_logic_typespec: , line:72:11, endln:72:11 - |vpiParent: - \_logic_net: (work@tb_UART.uart_inst.uut.rst_n), line:72:11, endln:72:16 -\_logic_typespec: , line:73:11, endln:73:11 - |vpiParent: - \_logic_net: (work@tb_UART.uart_inst.uut.send), line:73:11, endln:73:15 -\_logic_typespec: , line:74:11, endln:74:11 - |vpiParent: - \_logic_net: (work@tb_UART.uart_inst.uut.done), line:74:11, endln:74:15 -\_logic_typespec: , line:78:3, endln:78:12 - |vpiParent: - \_logic_net: (work@tb_UART.uart_inst.uut.state), line:78:13, endln:78:18 - |vpiRange: - \_range: , line:78:7, endln:78:12 - |vpiParent: - \_logic_typespec: , line:78:3, endln:78:12 - |vpiLeftRange: - \_constant: , line:78:8, endln:78:9 - |vpiParent: - \_range: , line:78:7, endln:78:12 - |vpiDecompile:2 - |vpiSize:64 - |UINT:2 - |vpiConstType:9 - |vpiRightRange: - \_constant: , line:78:10, endln:78:11 - |vpiParent: - \_range: , line:78:7, endln:78:12 - |vpiDecompile:0 - |vpiSize:64 - |UINT:0 - |vpiConstType:9 -\_logic_typespec: , line:71:11, endln:71:11 -\_logic_typespec: , line:72:11, endln:72:11 -\_logic_typespec: , line:73:11, endln:73:11 -\_logic_typespec: , line:74:11, endln:74:11 \_logic_typespec: , line:71:11, endln:71:11 |vpiParent: \_logic_net: (work@tb_UART.uart_inst.uut.clk), line:71:11, endln:71:14 @@ -6924,18 +6382,6 @@ design: (work@tb_UART) \_int_typespec: , line:79:5, endln:79:54 |vpiParent: \_ref_typespec: (work@tb_UART.uart_inst.uut.STOP) -\_int_typespec: , line:79:5, endln:79:54 - |vpiParent: - \_ref_typespec: (work@tb_UART.uart_inst.uut.IDLE) -\_int_typespec: , line:79:5, endln:79:54 - |vpiParent: - \_ref_typespec: (work@tb_UART.uart_inst.uut.START) -\_int_typespec: , line:79:5, endln:79:54 - |vpiParent: - \_ref_typespec: (work@tb_UART.uart_inst.uut.DATA) -\_int_typespec: , line:79:5, endln:79:54 - |vpiParent: - \_ref_typespec: (work@tb_UART.uart_inst.uut.STOP) =================== [ FATAL] : 0 [ SYNTAX] : 0 @@ -6968,10 +6414,4 @@ design: (work@tb_UART) [LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:90:14: Non synthesizable construct, p_done [LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:87:21: Non synthesizable construct, [LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:95:22: Non synthesizable construct, -[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:83:9: Non synthesizable construct, -[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:82:14: Non synthesizable construct, p_send -[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:91:9: Non synthesizable construct, -[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:90:14: Non synthesizable construct, p_done -[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:87:21: Non synthesizable construct, -[LINT]: ${SURELOG_DIR}/tests/AssertTempError/design.sv:95:22: Non synthesizable construct, ============================== End Linting Results ============================== diff --git a/tests/BindStmt2/BindStmt2.log b/tests/BindStmt2/BindStmt2.log index f87e11559e..8d6f1c1bbd 100644 --- a/tests/BindStmt2/BindStmt2.log +++ b/tests/BindStmt2/BindStmt2.log @@ -575,7 +575,7 @@ AST_DEBUG_END [NTE:EL0503] ${SURELOG_DIR}/tests/BindStmt2/dut.sv:56:1: Top level module "work@top". [NTE:EL0504] Multiple top level modules in design. [NTE:EL0508] Nb Top level modules: 2. -[NTE:EL0509] Max instance depth: 1. +[NTE:EL0509] Max instance depth: 2. [NTE:EL0510] Nb instances: 3. [NTE:EL0511] Nb leaf instances: 2. [INF:UH0706] Creating UHDM Model... @@ -617,7 +617,7 @@ param_assign 8 parameter 8 port 78 range 30 -ref_obj 108 +ref_obj 114 ref_typespec 135 string_typespec 2 unsupported_typespec 25 @@ -2231,14 +2231,15 @@ design: (work@rv_dm) |vpiInstance: \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiModule: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiParent: \_module_inst: work@rv_dm (work@rv_dm), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:1:1, endln:34:10 |vpiName:u_dmidpi + |vpiFullName:work@rv_dm.u_dmidpi |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.clk_i), line:40:21, endln:40:26 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.clk_i) |vpiParent: @@ -2252,7 +2253,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.rst_ni), line:41:21, endln:41:27 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.rst_ni) |vpiParent: @@ -2266,7 +2267,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_valid), line:43:21, endln:43:34 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.dmi_req_valid) |vpiParent: @@ -2280,7 +2281,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_ready), line:44:21, endln:44:34 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.dmi_req_ready) |vpiParent: @@ -2294,7 +2295,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_addr), line:45:21, endln:45:33 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.dmi_req_addr) |vpiParent: @@ -2308,7 +2309,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_op), line:46:21, endln:46:31 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.dmi_req_op) |vpiParent: @@ -2322,7 +2323,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_data), line:47:21, endln:47:33 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.dmi_req_data) |vpiParent: @@ -2336,7 +2337,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_valid), line:48:21, endln:48:34 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.dmi_rsp_valid) |vpiParent: @@ -2350,7 +2351,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_ready), line:49:21, endln:49:34 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.dmi_rsp_ready) |vpiParent: @@ -2364,7 +2365,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_data), line:50:21, endln:50:33 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.dmi_rsp_data) |vpiParent: @@ -2378,7 +2379,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_resp), line:51:21, endln:51:33 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.dmi_rsp_resp) |vpiParent: @@ -2392,7 +2393,7 @@ design: (work@rv_dm) |vpiVariables: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rst_n), line:52:21, endln:52:30 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.dmi_rst_n) |vpiParent: @@ -2406,7 +2407,7 @@ design: (work@rv_dm) |vpiParameter: \_parameter: (work@rv_dm.u_dmidpi.Name), line:37:20, endln:37:24 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |STRING:dmi0 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.Name) @@ -2420,7 +2421,7 @@ design: (work@rv_dm) |vpiParameter: \_parameter: (work@rv_dm.u_dmidpi.ListenPort), line:38:17, endln:38:27 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |UINT:44853 |vpiTypespec: \_ref_typespec: (work@rv_dm.u_dmidpi.ListenPort) @@ -2435,7 +2436,7 @@ design: (work@rv_dm) |vpiParamAssign: \_param_assign: , line:37:20, endln:37:33 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiRhs: \_constant: , line:37:27, endln:37:33 |vpiParent: @@ -2456,7 +2457,7 @@ design: (work@rv_dm) |vpiParamAssign: \_param_assign: , line:38:17, endln:38:35 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiRhs: \_constant: , line:38:30, endln:38:35 |vpiParent: @@ -2482,15 +2483,23 @@ design: (work@rv_dm) |vpiPort: \_port: (clk_i), line:40:21, endln:40:26 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:clk_i |vpiDirection:1 + |vpiHighConn: + \_ref_obj: (work@rv_dm.clk_i), line:58:6, endln:58:11 + |vpiParent: + \_port: (clk_i), line:40:21, endln:40:26 + |vpiName:clk_i + |vpiFullName:work@rv_dm.clk_i + |vpiActual: + \_bit_var: (work@rv_dm.u_dmidpi.clk_i), line:40:21, endln:40:26 |vpiLowConn: - \_ref_obj: (u_dmidpi.clk_i), line:58:6, endln:58:11 + \_ref_obj: (work@rv_dm.u_dmidpi.clk_i), line:58:6, endln:58:11 |vpiParent: \_port: (clk_i), line:40:21, endln:40:26 |vpiName:clk_i - |vpiFullName:u_dmidpi.clk_i + |vpiFullName:work@rv_dm.u_dmidpi.clk_i |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.clk_i), line:40:21, endln:40:26 |vpiTypedef: @@ -2501,19 +2510,27 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:40:10, endln:40:13 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (rst_ni), line:41:21, endln:41:27 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:rst_ni |vpiDirection:1 + |vpiHighConn: + \_ref_obj: (work@rv_dm.rst_ni), line:59:6, endln:59:12 + |vpiParent: + \_port: (rst_ni), line:41:21, endln:41:27 + |vpiName:rst_ni + |vpiFullName:work@rv_dm.rst_ni + |vpiActual: + \_bit_var: (work@rv_dm.u_dmidpi.rst_ni), line:41:21, endln:41:27 |vpiLowConn: - \_ref_obj: (u_dmidpi.rst_ni), line:59:6, endln:59:12 + \_ref_obj: (work@rv_dm.u_dmidpi.rst_ni), line:59:6, endln:59:12 |vpiParent: \_port: (rst_ni), line:41:21, endln:41:27 |vpiName:rst_ni - |vpiFullName:u_dmidpi.rst_ni + |vpiFullName:work@rv_dm.u_dmidpi.rst_ni |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.rst_ni), line:41:21, endln:41:27 |vpiTypedef: @@ -2524,19 +2541,27 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:41:10, endln:41:13 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_req_valid), line:43:21, endln:43:34 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_req_valid |vpiDirection:2 + |vpiHighConn: + \_ref_obj: (work@rv_dm.dmi_req_valid), line:60:6, endln:60:19 + |vpiParent: + \_port: (dmi_req_valid), line:43:21, endln:43:34 + |vpiName:dmi_req_valid + |vpiFullName:work@rv_dm.dmi_req_valid + |vpiActual: + \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_valid), line:43:21, endln:43:34 |vpiLowConn: - \_ref_obj: (u_dmidpi.dmi_req_valid), line:60:6, endln:60:19 + \_ref_obj: (work@rv_dm.u_dmidpi.dmi_req_valid), line:60:6, endln:60:19 |vpiParent: \_port: (dmi_req_valid), line:43:21, endln:43:34 |vpiName:dmi_req_valid - |vpiFullName:u_dmidpi.dmi_req_valid + |vpiFullName:work@rv_dm.u_dmidpi.dmi_req_valid |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_valid), line:43:21, endln:43:34 |vpiTypedef: @@ -2547,19 +2572,27 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:43:10, endln:43:13 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_req_ready), line:44:21, endln:44:34 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_req_ready |vpiDirection:1 + |vpiHighConn: + \_ref_obj: (work@rv_dm.dmi_req_ready), line:61:6, endln:61:19 + |vpiParent: + \_port: (dmi_req_ready), line:44:21, endln:44:34 + |vpiName:dmi_req_ready + |vpiFullName:work@rv_dm.dmi_req_ready + |vpiActual: + \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_ready), line:44:21, endln:44:34 |vpiLowConn: - \_ref_obj: (u_dmidpi.dmi_req_ready), line:61:6, endln:61:19 + \_ref_obj: (work@rv_dm.u_dmidpi.dmi_req_ready), line:61:6, endln:61:19 |vpiParent: \_port: (dmi_req_ready), line:44:21, endln:44:34 |vpiName:dmi_req_ready - |vpiFullName:u_dmidpi.dmi_req_ready + |vpiFullName:work@rv_dm.u_dmidpi.dmi_req_ready |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_ready), line:44:21, endln:44:34 |vpiTypedef: @@ -2570,11 +2603,11 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:44:10, endln:44:13 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_req_addr), line:45:21, endln:45:33 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_req_addr |vpiDirection:2 |vpiHighConn: @@ -2594,13 +2627,15 @@ design: (work@rv_dm) \_hier_path: (dmi_req.addr), line:62:22, endln:62:34 |vpiName:addr |vpiFullName:work@rv_dm.u_dmidpi.dmi_req_addr.addr + |vpiExpr: + \_logic_var: (work@rv_dm.dmi_req), line:28:18, endln:28:25 |vpiName:dmi_req.addr |vpiLowConn: - \_ref_obj: (u_dmidpi.dmi_req_addr), line:62:6, endln:62:18 + \_ref_obj: (work@rv_dm.u_dmidpi.dmi_req_addr), line:62:6, endln:62:18 |vpiParent: \_port: (dmi_req_addr), line:45:21, endln:45:33 |vpiName:dmi_req_addr - |vpiFullName:u_dmidpi.dmi_req_addr + |vpiFullName:work@rv_dm.u_dmidpi.dmi_req_addr |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_addr), line:45:21, endln:45:33 |vpiTypedef: @@ -2611,11 +2646,11 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:45:10, endln:45:19 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_req_op), line:46:21, endln:46:31 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_req_op |vpiDirection:2 |vpiHighConn: @@ -2635,13 +2670,15 @@ design: (work@rv_dm) \_hier_path: (dmi_req.op), line:63:22, endln:63:32 |vpiName:op |vpiFullName:work@rv_dm.u_dmidpi.dmi_req_op.op + |vpiExpr: + \_logic_var: (work@rv_dm.dmi_req), line:28:18, endln:28:25 |vpiName:dmi_req.op |vpiLowConn: - \_ref_obj: (u_dmidpi.dmi_req_op), line:63:6, endln:63:16 + \_ref_obj: (work@rv_dm.u_dmidpi.dmi_req_op), line:63:6, endln:63:16 |vpiParent: \_port: (dmi_req_op), line:46:21, endln:46:31 |vpiName:dmi_req_op - |vpiFullName:u_dmidpi.dmi_req_op + |vpiFullName:work@rv_dm.u_dmidpi.dmi_req_op |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_op), line:46:21, endln:46:31 |vpiTypedef: @@ -2652,11 +2689,11 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:46:10, endln:46:19 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_req_data), line:47:21, endln:47:33 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_req_data |vpiDirection:2 |vpiHighConn: @@ -2676,13 +2713,15 @@ design: (work@rv_dm) \_hier_path: (dmi_req.data), line:64:22, endln:64:34 |vpiName:data |vpiFullName:work@rv_dm.u_dmidpi.dmi_req_data.data + |vpiExpr: + \_logic_var: (work@rv_dm.dmi_req), line:28:18, endln:28:25 |vpiName:dmi_req.data |vpiLowConn: - \_ref_obj: (u_dmidpi.dmi_req_data), line:64:6, endln:64:18 + \_ref_obj: (work@rv_dm.u_dmidpi.dmi_req_data), line:64:6, endln:64:18 |vpiParent: \_port: (dmi_req_data), line:47:21, endln:47:33 |vpiName:dmi_req_data - |vpiFullName:u_dmidpi.dmi_req_data + |vpiFullName:work@rv_dm.u_dmidpi.dmi_req_data |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.dmi_req_data), line:47:21, endln:47:33 |vpiTypedef: @@ -2693,19 +2732,27 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:47:10, endln:47:20 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_rsp_valid), line:48:21, endln:48:34 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_rsp_valid |vpiDirection:1 + |vpiHighConn: + \_ref_obj: (work@rv_dm.dmi_rsp_valid), line:65:6, endln:65:19 + |vpiParent: + \_port: (dmi_rsp_valid), line:48:21, endln:48:34 + |vpiName:dmi_rsp_valid + |vpiFullName:work@rv_dm.dmi_rsp_valid + |vpiActual: + \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_valid), line:48:21, endln:48:34 |vpiLowConn: - \_ref_obj: (u_dmidpi.dmi_rsp_valid), line:65:6, endln:65:19 + \_ref_obj: (work@rv_dm.u_dmidpi.dmi_rsp_valid), line:65:6, endln:65:19 |vpiParent: \_port: (dmi_rsp_valid), line:48:21, endln:48:34 |vpiName:dmi_rsp_valid - |vpiFullName:u_dmidpi.dmi_rsp_valid + |vpiFullName:work@rv_dm.u_dmidpi.dmi_rsp_valid |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_valid), line:48:21, endln:48:34 |vpiTypedef: @@ -2716,19 +2763,27 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:48:10, endln:48:13 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_rsp_ready), line:49:21, endln:49:34 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_rsp_ready |vpiDirection:2 + |vpiHighConn: + \_ref_obj: (work@rv_dm.dmi_rsp_ready), line:66:6, endln:66:19 + |vpiParent: + \_port: (dmi_rsp_ready), line:49:21, endln:49:34 + |vpiName:dmi_rsp_ready + |vpiFullName:work@rv_dm.dmi_rsp_ready + |vpiActual: + \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_ready), line:49:21, endln:49:34 |vpiLowConn: - \_ref_obj: (u_dmidpi.dmi_rsp_ready), line:66:6, endln:66:19 + \_ref_obj: (work@rv_dm.u_dmidpi.dmi_rsp_ready), line:66:6, endln:66:19 |vpiParent: \_port: (dmi_rsp_ready), line:49:21, endln:49:34 |vpiName:dmi_rsp_ready - |vpiFullName:u_dmidpi.dmi_rsp_ready + |vpiFullName:work@rv_dm.u_dmidpi.dmi_rsp_ready |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_ready), line:49:21, endln:49:34 |vpiTypedef: @@ -2739,11 +2794,11 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:49:10, endln:49:13 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_rsp_data), line:50:21, endln:50:33 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_rsp_data |vpiDirection:1 |vpiHighConn: @@ -2763,13 +2818,15 @@ design: (work@rv_dm) \_hier_path: (dmi_rsp.data), line:67:22, endln:67:34 |vpiName:data |vpiFullName:work@rv_dm.u_dmidpi.dmi_rsp_data.data + |vpiExpr: + \_logic_var: (work@rv_dm.dmi_rsp), line:29:18, endln:29:25 |vpiName:dmi_rsp.data |vpiLowConn: - \_ref_obj: (u_dmidpi.dmi_rsp_data), line:67:6, endln:67:18 + \_ref_obj: (work@rv_dm.u_dmidpi.dmi_rsp_data), line:67:6, endln:67:18 |vpiParent: \_port: (dmi_rsp_data), line:50:21, endln:50:33 |vpiName:dmi_rsp_data - |vpiFullName:u_dmidpi.dmi_rsp_data + |vpiFullName:work@rv_dm.u_dmidpi.dmi_rsp_data |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_data), line:50:21, endln:50:33 |vpiTypedef: @@ -2780,11 +2837,11 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:50:10, endln:50:20 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_rsp_resp), line:51:21, endln:51:33 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_rsp_resp |vpiDirection:1 |vpiHighConn: @@ -2804,13 +2861,15 @@ design: (work@rv_dm) \_hier_path: (dmi_rsp.resp), line:68:22, endln:68:34 |vpiName:resp |vpiFullName:work@rv_dm.u_dmidpi.dmi_rsp_resp.resp + |vpiExpr: + \_logic_var: (work@rv_dm.dmi_rsp), line:29:18, endln:29:25 |vpiName:dmi_rsp.resp |vpiLowConn: - \_ref_obj: (u_dmidpi.dmi_rsp_resp), line:68:6, endln:68:18 + \_ref_obj: (work@rv_dm.u_dmidpi.dmi_rsp_resp), line:68:6, endln:68:18 |vpiParent: \_port: (dmi_rsp_resp), line:51:21, endln:51:33 |vpiName:dmi_rsp_resp - |vpiFullName:u_dmidpi.dmi_rsp_resp + |vpiFullName:work@rv_dm.u_dmidpi.dmi_rsp_resp |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_resp), line:51:21, endln:51:33 |vpiTypedef: @@ -2821,27 +2880,27 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:51:10, endln:51:19 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiPort: \_port: (dmi_rst_n), line:52:21, endln:52:30 |vpiParent: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |vpiName:dmi_rst_n |vpiDirection:2 |vpiHighConn: - \_ref_obj: (work@rv_dm.u_dmidpi.dmi_rst_n.dmi_rst_n), line:69:22, endln:69:31 + \_ref_obj: (work@rv_dm.dmi_rst_n), line:69:22, endln:69:31 |vpiParent: \_port: (dmi_rst_n), line:52:21, endln:52:30 |vpiName:dmi_rst_n - |vpiFullName:work@rv_dm.u_dmidpi.dmi_rst_n.dmi_rst_n + |vpiFullName:work@rv_dm.dmi_rst_n |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rst_n), line:52:21, endln:52:30 |vpiLowConn: - \_ref_obj: (u_dmidpi.dmi_rst_n), line:69:6, endln:69:15 + \_ref_obj: (work@rv_dm.u_dmidpi.dmi_rst_n), line:69:6, endln:69:15 |vpiParent: \_port: (dmi_rst_n), line:52:21, endln:52:30 |vpiName:dmi_rst_n - |vpiFullName:u_dmidpi.dmi_rst_n + |vpiFullName:work@rv_dm.u_dmidpi.dmi_rst_n |vpiActual: \_bit_var: (work@rv_dm.u_dmidpi.dmi_rst_n), line:52:21, endln:52:30 |vpiTypedef: @@ -2852,7 +2911,7 @@ design: (work@rv_dm) |vpiActual: \_bit_typespec: , line:52:10, endln:52:13 |vpiInstance: - \_module_inst: work@dmidpi (u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 + \_module_inst: work@dmidpi (work@rv_dm.u_dmidpi), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:57:14, endln:70:5 |uhdmtopModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BindStmt2/dut.sv, line:56:1, endln:71:10 |vpiName:work@top diff --git a/tests/BindingPort/BindingPort.log b/tests/BindingPort/BindingPort.log index 5c853fe7f4..80e898b616 100644 --- a/tests/BindingPort/BindingPort.log +++ b/tests/BindingPort/BindingPort.log @@ -60,28 +60,28 @@ AST_DEBUG_END [NTE:EL0503] ${SURELOG_DIR}/tests/BindingPort/dut.sv:4:1: Top level module "work@UART". [ERR:EL0550] ${SURELOG_DIR}/tests/BindingPort/dut.sv:22:38: Unknown port "state". [NTE:EL0508] Nb Top level modules: 1. -[NTE:EL0509] Max instance depth: 1. -[NTE:EL0510] Nb instances: 3. -[NTE:EL0511] Nb leaf instances: 2. +[NTE:EL0509] Max instance depth: 2. +[NTE:EL0510] Nb instances: 2. +[NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === design 1 -logic_net 5 -logic_typespec 8 -module_inst 7 -port 5 -ref_obj 7 -ref_typespec 8 +logic_net 4 +logic_typespec 6 +module_inst 5 +port 4 +ref_obj 5 +ref_typespec 6 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === design 1 -logic_net 5 -logic_typespec 8 -module_inst 7 -port 8 -ref_obj 12 -ref_typespec 11 +logic_net 4 +logic_typespec 6 +module_inst 5 +port 6 +ref_obj 8 +ref_typespec 8 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BindingPort/slpp_all/surelog.uhdm ... [INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/BindingPort/slpp_all/checker/surelog.chk.html ... @@ -200,17 +200,18 @@ design: (work@UART) |vpiInstance: \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 |vpiModule: - \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 + \_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 |vpiParent: \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 |vpiName:uut + |vpiFullName:work@UART.uut |vpiDefName:work@UART_assertions |vpiDefFile:${SURELOG_DIR}/tests/BindingPort/dut.sv |vpiDefLineNo:13 |vpiNet: \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 |vpiParent: - \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 + \_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 |vpiTypespec: \_ref_typespec: (work@UART.uut.clk) |vpiParent: @@ -225,78 +226,24 @@ design: (work@UART) |vpiPort: \_port: (state), line:14:11, endln:14:14 |vpiParent: - \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 + \_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 |vpiName:state |vpiDirection:1 |vpiHighConn: - \_ref_obj: (work@UART.uut.state.clk), line:22:44, endln:22:47 + \_ref_obj: (work@UART.clk), line:22:44, endln:22:47 |vpiParent: \_port: (state), line:14:11, endln:14:14 |vpiName:clk - |vpiFullName:work@UART.uut.state.clk + |vpiFullName:work@UART.clk |vpiActual: \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 |vpiLowConn: - \_ref_obj: (uut.clk), line:22:38, endln:22:43 + \_ref_obj: (work@UART.uut.clk), line:22:38, endln:22:43 |vpiParent: \_port: (state), line:14:11, endln:14:14 |vpiName:clk - |vpiFullName:uut.clk - |vpiActual: - \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 - |vpiTypedef: - \_ref_typespec: (work@UART.uut.state) - |vpiParent: - \_port: (state), line:14:11, endln:14:14 - |vpiFullName:work@UART.uut.state - |vpiActual: - \_logic_typespec: , line:14:11, endln:14:11 - |vpiInstance: - \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 - |vpiModule: - \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 - |vpiParent: - \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 - |vpiName:uut - |vpiDefName:work@UART_assertions - |vpiDefFile:${SURELOG_DIR}/tests/BindingPort/dut.sv - |vpiDefLineNo:13 - |vpiNet: - \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 - |vpiParent: - \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 - |vpiTypespec: - \_ref_typespec: (work@UART.uut.clk) - |vpiParent: - \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 |vpiFullName:work@UART.uut.clk |vpiActual: - \_logic_typespec: , line:14:11, endln:14:11 - |vpiName:clk - |vpiFullName:work@UART.uut.clk - |vpiInstance: - \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 - |vpiPort: - \_port: (state), line:14:11, endln:14:14 - |vpiParent: - \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 - |vpiName:state - |vpiDirection:1 - |vpiHighConn: - \_ref_obj: (work@UART.uut.state.clk), line:22:44, endln:22:47 - |vpiParent: - \_port: (state), line:14:11, endln:14:14 - |vpiName:clk - |vpiFullName:work@UART.uut.state.clk - |vpiActual: - \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 - |vpiLowConn: - \_ref_obj: (uut.clk), line:22:38, endln:22:43 - |vpiParent: - \_port: (state), line:14:11, endln:14:14 - |vpiName:clk - |vpiFullName:uut.clk - |vpiActual: \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 |vpiTypedef: \_ref_typespec: (work@UART.uut.state) @@ -306,17 +253,13 @@ design: (work@UART) |vpiActual: \_logic_typespec: , line:14:11, endln:14:11 |vpiInstance: - \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 + \_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 \_weaklyReferenced: \_logic_typespec: , line:5:11, endln:5:11 \_logic_typespec: , line:5:11, endln:5:11 |vpiParent: \_logic_net: (work@UART.clk), line:5:11, endln:5:14 \_logic_typespec: , line:14:11, endln:14:11 -\_logic_typespec: , line:14:11, endln:14:11 - |vpiParent: - \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 -\_logic_typespec: , line:14:11, endln:14:11 \_logic_typespec: , line:14:11, endln:14:11 |vpiParent: \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 diff --git a/tests/InterfaceBinding/InterfaceBinding.log b/tests/InterfaceBinding/InterfaceBinding.log new file mode 100644 index 0000000000..a77a950c98 --- /dev/null +++ b/tests/InterfaceBinding/InterfaceBinding.log @@ -0,0 +1,1705 @@ +[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/InterfaceBinding/slpp_all/surelog.log". +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<298> s<297> l<1:1> el<1:0> +n u<2> t p<67> s<3> l<1:1> el<1:7> +n u<3> t p<67> s<66> l<1:8> el<1:15> +n<> u<4> t p<7> s<6> l<2:3> el<2:8> +n<> u<5> t p<6> l<2:20> el<2:20> +n<> u<6> t p<7> c<5> l<2:20> el<2:20> +n<> u<7> t p<9> c<4> s<8> l<2:3> el<2:8> +n u<8> t p<9> l<2:20> el<2:23> +n<> u<9> t p<66> c<7> s<25> l<2:3> el<2:23> +n<> u<10> t p<23> s<22> l<3:3> el<3:8> +n<7> u<11> t p<12> l<3:10> el<3:11> +n<> u<12> t p<13> c<11> l<3:10> el<3:11> +n<> u<13> t p<14> c<12> l<3:10> el<3:11> +n<> u<14> t p<19> c<13> s<18> l<3:10> el<3:11> +n<0> u<15> t p<16> l<3:12> el<3:13> +n<> u<16> t p<17> c<15> l<3:12> el<3:13> +n<> u<17> t p<18> c<16> l<3:12> el<3:13> +n<> u<18> t p<19> c<17> l<3:12> el<3:13> +n<> u<19> t p<20> c<14> l<3:10> el<3:13> +n<> u<20> t p<21> c<19> l<3:9> el<3:14> +n<> u<21> t p<22> c<20> l<3:9> el<3:14> +n<> u<22> t p<23> c<21> l<3:9> el<3:14> +n<> u<23> t p<25> c<10> s<24> l<3:3> el<3:14> +n u<24> t p<25> l<3:20> el<3:22> +n<> u<25> t p<66> c<23> s<41> l<3:3> el<3:22> +n<> u<26> t p<39> s<38> l<4:3> el<4:8> +n<7> u<27> t p<28> l<4:10> el<4:11> +n<> u<28> t p<29> c<27> l<4:10> el<4:11> +n<> u<29> t p<30> c<28> l<4:10> el<4:11> +n<> u<30> t p<35> c<29> s<34> l<4:10> el<4:11> +n<0> u<31> t p<32> l<4:12> el<4:13> +n<> u<32> t p<33> c<31> l<4:12> el<4:13> +n<> u<33> t p<34> c<32> l<4:12> el<4:13> +n<> u<34> t p<35> c<33> l<4:12> el<4:13> +n<> u<35> t p<36> c<30> l<4:10> el<4:13> +n<> u<36> t p<37> c<35> l<4:9> el<4:14> +n<> u<37> t p<38> c<36> l<4:9> el<4:14> +n<> u<38> t p<39> c<37> l<4:9> el<4:14> +n<> u<39> t p<41> c<26> s<40> l<4:3> el<4:14> +n u<40> t p<41> l<4:20> el<4:22> +n<> u<41> t p<66> c<39> s<47> l<4:3> el<4:22> +n<> u<42> t p<45> s<44> l<5:3> el<5:8> +n<> u<43> t p<44> l<5:20> el<5:20> +n<> u<44> t p<45> c<43> l<5:20> el<5:20> +n<> u<45> t p<47> c<42> s<46> l<5:3> el<5:8> +n u<46> t p<47> l<5:20> el<5:26> +n<> u<47> t p<66> c<45> s<65> l<5:3> el<5:26> +n<> u<48> t p<63> s<62> l<6:3> el<6:9> +n<> u<49> t p<60> s<59> l<6:10> el<6:13> +n<8> u<50> t p<51> l<6:15> el<6:16> +n<> u<51> t p<52> c<50> l<6:15> el<6:16> +n<> u<52> t p<53> c<51> l<6:15> el<6:16> +n<> u<53> t p<58> c<52> s<57> l<6:15> el<6:16> +n<0> u<54> t p<55> l<6:17> el<6:18> +n<> u<55> t p<56> c<54> l<6:17> el<6:18> +n<> u<56> t p<57> c<55> l<6:17> el<6:18> +n<> u<57> t p<58> c<56> l<6:17> el<6:18> +n<> u<58> t p<59> c<53> l<6:15> el<6:18> +n<> u<59> t p<60> c<58> l<6:14> el<6:19> +n<> u<60> t p<61> c<49> l<6:10> el<6:19> +n<> u<61> t p<62> c<60> l<6:10> el<6:19> +n<> u<62> t p<63> c<61> l<6:10> el<6:19> +n<> u<63> t p<65> c<48> s<64> l<6:3> el<6:19> +n u<64> t p<65> l<6:20> el<6:27> +n<> u<65> t p<66> c<63> l<6:3> el<6:27> +n<> u<66> t p<67> c<9> l<1:15> el<7:2> +n<> u<67> t p<139> c<2> s<136> l<1:1> el<7:3> +n<> u<68> t p<133> s<132> l<9:3> el<9:9> +n<> u<69> t p<74> s<73> l<9:13> el<9:20> +n u<70> t p<71> l<9:21> el<9:24> +n<> u<71> t p<72> c<70> l<9:21> el<9:24> +n<> u<72> t p<73> c<71> l<9:21> el<9:24> +n<> u<73> t p<74> c<72> l<9:21> el<9:24> +n<> u<74> t p<75> c<69> l<9:13> el<9:24> +n<> u<75> t p<76> c<74> l<9:10> el<9:25> +n<> u<76> t p<130> c<75> s<129> l<9:10> el<9:25> +n u<77> t p<78> l<11:11> el<11:17> +n<> u<78> t p<79> c<77> l<11:11> el<11:17> +n<> u<79> t p<80> c<78> l<11:11> el<11:17> +n<> u<80> t p<81> c<79> l<11:11> el<11:17> +n<> u<81> t p<82> c<80> l<11:11> el<11:17> +n<> u<82> t p<121> c<81> s<101> l<11:11> el<11:17> +n u<83> t p<84> l<12:9> el<12:16> +n<> u<84> t p<87> c<83> s<86> l<12:9> el<12:16> +n<> u<85> t p<86> l<12:17> el<12:17> +n<> u<86> t p<106> c<104> l<14:17> el<14:17> +n<> u<106> t p<117> c<103> s<116> l<14:9> el<14:16> +n u<107> t p<108> l<14:20> el<14:22> +n<> u<108> t p<109> c<107> l<14:20> el<14:22> +n<> u<109> t p<110> c<108> l<14:20> el<14:22> +n<> u<110> t p<116> c<109> s<115> l<14:20> el<14:22> +n u<111> t p<112> l<14:25> el<14:27> +n<> u<112> t p<113> c<111> l<14:25> el<14:27> +n<> u<113> t p<114> c<112> l<14:25> el<14:27> +n<> u<114> t p<116> c<113> l<14:25> el<14:27> +n<> u<115> t p<116> s<114> l<14:23> el<14:24> +n<> u<116> t p<117> c<110> l<14:20> el<14:27> +n<> u<117> t p<118> c<106> l<14:9> el<14:27> +n<> u<118> t p<119> c<117> l<14:9> el<14:28> +n<> u<119> t p<120> c<118> l<14:9> el<14:28> +n<> u<120> t p<121> c<119> l<14:9> el<14:28> +n<> u<121> t p<122> c<82> l<11:7> el<14:28> +n<> u<122> t p<123> c<121> l<11:7> el<14:28> +n<> u<123> t p<124> c<122> l<11:7> el<14:28> +n<> u<124> t p<126> c<123> s<125> l<11:7> el<14:28> +n<> u<125> t p<126> l<15:5> el<15:8> +n<> u<126> t p<127> c<124> l<10:5> el<15:8> +n<> u<127> t p<128> c<126> l<10:5> el<15:8> +n<> u<128> t p<129> c<127> l<10:5> el<15:8> +n<> u<129> t p<130> c<128> l<10:5> el<15:8> +n<> u<130> t p<131> c<76> l<9:10> el<15:8> +n<> u<131> t p<132> c<130> l<9:10> el<15:8> +n<> u<132> t p<133> c<131> l<9:10> el<15:8> +n<> u<133> t p<134> c<68> l<9:3> el<15:8> +n<> u<134> t p<135> c<133> l<9:3> el<15:8> +n<> u<135> t p<136> c<134> l<9:3> el<15:8> +n<> u<136> t p<139> c<135> s<138> l<9:3> el<15:8> +n u<137> t p<139> l<17:12> el<17:19> +n<> u<138> t p<139> s<137> l<17:1> el<17:10> +n<> u<139> t p<140> c<67> l<1:1> el<17:19> +n<> u<140> t p<297> c<139> s<246> l<1:1> el<17:19> +n<> u<141> t p<207> s<143> l<19:1> el<19:10> +n u<142> t p<143> l<19:11> el<19:21> +n<> u<143> t p<207> c<142> s<206> l<19:11> el<19:21> +n<> u<144> t p<149> s<148> l<20:3> el<20:8> +n<> u<145> t p<146> l<20:9> el<20:12> +n<> u<146> t p<147> c<145> l<20:9> el<20:12> +n<> u<147> t p<148> c<146> l<20:9> el<20:12> +n<> u<148> t p<149> c<147> l<20:9> el<20:12> +n<> u<149> t p<151> c<144> s<150> l<20:3> el<20:12> +n u<150> t p<151> l<20:13> el<20:16> +n<> u<151> t p<206> c<149> s<167> l<20:3> el<20:16> +n<> u<152> t p<165> s<164> l<21:3> el<21:8> +n<7> u<153> t p<154> l<21:10> el<21:11> +n<> u<154> t p<155> c<153> l<21:10> el<21:11> +n<> u<155> t p<156> c<154> l<21:10> el<21:11> +n<> u<156> t p<161> c<155> s<160> l<21:10> el<21:11> +n<0> u<157> t p<158> l<21:12> el<21:13> +n<> u<158> t p<159> c<157> l<21:12> el<21:13> +n<> u<159> t p<160> c<158> l<21:12> el<21:13> +n<> u<160> t p<161> c<159> l<21:12> el<21:13> +n<> u<161> t p<162> c<156> l<21:10> el<21:13> +n<> u<162> t p<163> c<161> l<21:9> el<21:14> +n<> u<163> t p<164> c<162> l<21:9> el<21:14> +n<> u<164> t p<165> c<163> l<21:9> el<21:14> +n<> u<165> t p<167> c<152> s<166> l<21:3> el<21:14> +n u<166> t p<167> l<21:15> el<21:16> +n<> u<167> t p<206> c<165> s<183> l<21:3> el<21:16> +n<> u<168> t p<181> s<180> l<22:3> el<22:8> +n<7> u<169> t p<170> l<22:10> el<22:11> +n<> u<170> t p<171> c<169> l<22:10> el<22:11> +n<> u<171> t p<172> c<170> l<22:10> el<22:11> +n<> u<172> t p<177> c<171> s<176> l<22:10> el<22:11> +n<0> u<173> t p<174> l<22:12> el<22:13> +n<> u<174> t p<175> c<173> l<22:12> el<22:13> +n<> u<175> t p<176> c<174> l<22:12> el<22:13> +n<> u<176> t p<177> c<175> l<22:12> el<22:13> +n<> u<177> t p<178> c<172> l<22:10> el<22:13> +n<> u<178> t p<179> c<177> l<22:9> el<22:14> +n<> u<179> t p<180> c<178> l<22:9> el<22:14> +n<> u<180> t p<181> c<179> l<22:9> el<22:14> +n<> u<181> t p<183> c<168> s<182> l<22:3> el<22:14> +n u<182> t p<183> l<22:15> el<22:16> +n<> u<183> t p<206> c<181> s<189> l<22:3> el<22:16> +n<> u<184> t p<187> s<186> l<23:3> el<23:8> +n<> u<185> t p<186> l<23:15> el<23:15> +n<> u<186> t p<187> c<185> l<23:15> el<23:15> +n<> u<187> t p<189> c<184> s<188> l<23:3> el<23:8> +n u<188> t p<189> l<23:15> el<23:20> +n<> u<189> t p<206> c<187> s<205> l<23:3> el<23:20> +n<> u<190> t p<203> s<202> l<24:3> el<24:8> +n<8> u<191> t p<192> l<24:10> el<24:11> +n<> u<192> t p<193> c<191> l<24:10> el<24:11> +n<> u<193> t p<194> c<192> l<24:10> el<24:11> +n<> u<194> t p<199> c<193> s<198> l<24:10> el<24:11> +n<0> u<195> t p<196> l<24:12> el<24:13> +n<> u<196> t p<197> c<195> l<24:12> el<24:13> +n<> u<197> t p<198> c<196> l<24:12> el<24:13> +n<> u<198> t p<199> c<197> l<24:12> el<24:13> +n<> u<199> t p<200> c<194> l<24:10> el<24:13> +n<> u<200> t p<201> c<199> l<24:9> el<24:14> +n<> u<201> t p<202> c<200> l<24:9> el<24:14> +n<> u<202> t p<203> c<201> l<24:9> el<24:14> +n<> u<203> t p<205> c<190> s<204> l<24:3> el<24:14> +n u<204> t p<205> l<24:15> el<24:21> +n<> u<205> t p<206> c<203> l<24:3> el<24:21> +n<> u<206> t p<207> c<151> l<19:21> el<25:2> +n<> u<207> t p<245> c<141> s<241> l<19:1> el<25:3> +n u<208> t p<237> s<215> l<27:12> el<27:14> +n<> u<209> t p<214> s<213> l<27:17> el<27:24> +n u<210> t p<211> l<27:25> el<27:28> +n<> u<211> t p<212> c<210> l<27:25> el<27:28> +n<> u<212> t p<213> c<211> l<27:25> el<27:28> +n<> u<213> t p<214> c<212> l<27:25> el<27:28> +n<> u<214> t p<215> c<209> l<27:17> el<27:28> +n<> u<215> t p<237> c<214> s<220> l<27:15> el<27:29> +n<> u<216> t p<220> s<219> l<28:5> el<28:11> +n u<217> t p<218> l<28:15> el<28:16> +n<> u<218> t p<219> c<217> l<28:15> el<28:16> +n<> u<219> t p<220> c<218> l<28:15> el<28:16> +n<> u<220> t p<237> c<216> s<225> l<28:5> el<28:17> +n<> u<221> t p<225> s<224> l<29:5> el<29:11> +n u<222> t p<223> l<29:15> el<29:16> +n<> u<223> t p<224> c<222> l<29:15> el<29:16> +n<> u<224> t p<225> c<223> l<29:15> el<29:16> +n<> u<225> t p<237> c<221> s<230> l<29:5> el<29:17> +n<> u<226> t p<230> s<229> l<30:5> el<30:11> +n u<227> t p<228> l<30:15> el<30:20> +n<> u<228> t p<229> c<227> l<30:15> el<30:20> +n<> u<229> t p<230> c<228> l<30:15> el<30:20> +n<> u<230> t p<237> c<226> s<235> l<30:5> el<30:21> +n<> u<231> t p<235> s<234> l<31:5> el<31:10> +n u<232> t p<233> l<31:15> el<31:21> +n<> u<233> t p<234> c<232> l<31:15> el<31:21> +n<> u<234> t p<235> c<233> l<31:15> el<31:21> +n<> u<235> t p<237> c<231> s<236> l<31:5> el<31:22> +n<> u<236> t p<237> l<32:3> el<32:14> +n<> u<237> t p<238> c<208> l<27:3> el<32:14> +n<> u<238> t p<239> c<237> l<27:3> el<32:14> +n<> u<239> t p<240> c<238> l<27:3> el<32:14> +n<> u<240> t p<241> c<239> l<27:3> el<32:14> +n<> u<241> t p<245> c<240> s<244> l<27:3> el<32:14> +n u<242> t p<243> l<34:15> el<34:25> +n<> u<243> t p<245> c<242> l<34:15> el<34:25> +n<> u<244> t p<245> s<243> l<34:1> el<34:13> +n<> u<245> t p<246> c<207> l<19:1> el<34:25> +n<> u<246> t p<297> c<245> s<296> l<19:1> el<34:25> +n u<247> t p<295> s<294> l<36:6> el<36:13> +n u<248> t p<293> s<292> l<36:14> el<36:24> +n u<249> t p<250> l<36:25> el<36:36> +n<> u<250> t p<292> c<249> s<291> l<36:25> el<36:36> +n u<251> t p<258> s<256> l<37:4> el<37:7> +n u<252> t p<253> l<37:8> el<37:11> +n<> u<253> t p<254> c<252> l<37:8> el<37:11> +n<> u<254> t p<255> c<253> l<37:8> el<37:11> +n<> u<255> t p<258> c<254> s<257> l<37:8> el<37:11> +n<> u<256> t p<258> s<255> l<37:7> el<37:8> +n<> u<257> t p<258> l<37:11> el<37:12> +n<> u<258> t p<291> c<251> s<266> l<37:3> el<37:12> +n u<259> t p<266> s<264> l<38:4> el<38:5> +n u<260> t p<261> l<38:6> el<38:8> +n<> u<261> t p<262> c<260> l<38:6> el<38:8> +n<> u<262> t p<263> c<261> l<38:6> el<38:8> +n<> u<263> t p<266> c<262> s<265> l<38:6> el<38:8> +n<> u<264> t p<266> s<263> l<38:5> el<38:6> +n<> u<265> t p<266> l<38:8> el<38:9> +n<> u<266> t p<291> c<259> s<274> l<38:3> el<38:9> +n u<267> t p<274> s<272> l<39:4> el<39:5> +n u<268> t p<269> l<39:6> el<39:8> +n<> u<269> t p<270> c<268> l<39:6> el<39:8> +n<> u<270> t p<271> c<269> l<39:6> el<39:8> +n<> u<271> t p<274> c<270> s<273> l<39:6> el<39:8> +n<> u<272> t p<274> s<271> l<39:5> el<39:6> +n<> u<273> t p<274> l<39:8> el<39:9> +n<> u<274> t p<291> c<267> s<282> l<39:3> el<39:9> +n u<275> t p<282> s<280> l<40:4> el<40:9> +n u<276> t p<277> l<40:10> el<40:16> +n<> u<277> t p<278> c<276> l<40:10> el<40:16> +n<> u<278> t p<279> c<277> l<40:10> el<40:16> +n<> u<279> t p<282> c<278> s<281> l<40:10> el<40:16> +n<> u<280> t p<282> s<279> l<40:9> el<40:10> +n<> u<281> t p<282> l<40:16> el<40:17> +n<> u<282> t p<291> c<275> s<290> l<40:3> el<40:17> +n u<283> t p<290> s<288> l<41:4> el<41:10> +n u<284> t p<285> l<41:11> el<41:18> +n<> u<285> t p<286> c<284> l<41:11> el<41:18> +n<> u<286> t p<287> c<285> l<41:11> el<41:18> +n<> u<287> t p<290> c<286> s<289> l<41:11> el<41:18> +n<> u<288> t p<290> s<287> l<41:10> el<41:11> +n<> u<289> t p<290> l<41:18> el<41:19> +n<> u<290> t p<291> c<283> l<41:3> el<41:19> +n<> u<291> t p<292> c<258> l<37:3> el<41:19> +n<> u<292> t p<293> c<250> l<36:25> el<42:2> +n<> u<293> t p<294> c<248> l<36:14> el<42:3> +n<> u<294> t p<295> c<293> l<36:14> el<42:3> +n<> u<295> t p<296> c<247> l<36:1> el<42:3> +n<> u<296> t p<297> c<295> l<36:1> el<42:3> +n<> u<297> t p<298> c<140> l<1:1> el<42:3> +n<> u<298> t c<1> l<1:1> el<42:3> +AST_DEBUG_END +[WRN:PA0205] ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:1:1: No timescale set for "ADD_SUB". +[WRN:PA0205] ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:19:1: No timescale set for "add_sub_if". +[INF:CP0300] Compilation... +[INF:CP0303] ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:1:1: Compile module "work@ADD_SUB". +[INF:CP0304] ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:19:1: Compile interface "work@add_sub_if". +[INF:EL0526] Design Elaboration... +[NTE:EL0503] ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:1:1: Top level module "work@ADD_SUB". +[NTE:EL0508] Nb Top level modules: 1. +[NTE:EL0509] Max instance depth: 1. +[NTE:EL0510] Nb instances: 1. +[NTE:EL0511] Nb leaf instances: 0. +[INF:UH0706] Creating UHDM Model... +=== UHDM Object Stats Begin (Non-Elaborated Model) === +always 1 +assignment 2 +begin 1 +bit_typespec 2 +bit_var 1 +clocking_block 2 +clocking_io_decl 8 +constant 42 +design 1 +event_control 3 +if_else 1 +interface_inst 3 +logic_net 19 +logic_typespec 23 +module_inst 4 +operation 5 +port 20 +range 21 +ref_obj 35 +ref_typespec 25 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... +=== UHDM Object Stats Begin (Elaborated Model) === +always 2 +assignment 4 +begin 2 +bit_typespec 2 +bit_var 1 +clocking_block 2 +clocking_io_decl 8 +constant 42 +design 1 +event_control 4 +if_else 2 +interface_inst 3 +logic_net 19 +logic_typespec 23 +module_inst 4 +operation 8 +port 25 +range 21 +ref_obj 48 +ref_typespec 30 +=== UHDM Object Stats End === +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/InterfaceBinding/slpp_all/surelog.uhdm ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/InterfaceBinding/slpp_all/checker/surelog.chk.html ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/InterfaceBinding/slpp_all/surelog.uhdm ... +[INF:UH0711] Decompiling UHDM... +====== UHDM ======= +design: (work@ADD_SUB) +|vpiElaborated:1 +|vpiName:work@ADD_SUB +|uhdmallInterfaces: +\_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiParent: + \_design: (work@ADD_SUB) + |vpiFullName:work@add_sub_if + |vpiDefName:work@add_sub_if + |vpiNet: + \_logic_net: (work@add_sub_if.clk), line:20:13, endln:20:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiName:clk + |vpiFullName:work@add_sub_if.clk + |vpiNet: + \_logic_net: (work@add_sub_if.a), line:21:15, endln:21:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiName:a + |vpiFullName:work@add_sub_if.a + |vpiNet: + \_logic_net: (work@add_sub_if.b), line:22:15, endln:22:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiName:b + |vpiFullName:work@add_sub_if.b + |vpiNet: + \_logic_net: (work@add_sub_if.doAdd), line:23:15, endln:23:20 + |vpiParent: + \_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiName:doAdd + |vpiFullName:work@add_sub_if.doAdd + |vpiNet: + \_logic_net: (work@add_sub_if.result), line:24:15, endln:24:21 + |vpiParent: + \_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiName:result + |vpiFullName:work@add_sub_if.result + |vpiClockingBlock: + \_clocking_block: (work@add_sub_if.cb), line:27:3, endln:32:14 + |vpiParent: + \_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiName:cb + |vpiFullName:work@add_sub_if.cb + |vpiClockingEvent: + \_event_control: , line:27:15, endln:27:29 + |vpiParent: + \_clocking_block: (work@add_sub_if.cb), line:27:3, endln:32:14 + |vpiCondition: + \_operation: , line:27:17, endln:27:28 + |vpiParent: + \_event_control: , line:27:15, endln:27:29 + |vpiOpType:39 + |vpiOperand: + \_ref_obj: (work@add_sub_if.cb.clk), line:27:25, endln:27:28 + |vpiParent: + \_operation: , line:27:17, endln:27:28 + |vpiName:clk + |vpiFullName:work@add_sub_if.cb.clk + |vpiActual: + \_bit_var: (work@ADD_SUB.add_sub_if0.clk), line:20:13, endln:20:16 + |vpiClockingIODecl: + \_clocking_io_decl: (a), line:28:15, endln:28:16 + |vpiParent: + \_clocking_block: (work@add_sub_if.cb), line:27:3, endln:32:14 + |vpiDirection:2 + |vpiName:a + |vpiClockingIODecl: + \_clocking_io_decl: (b), line:29:15, endln:29:16 + |vpiParent: + \_clocking_block: (work@add_sub_if.cb), line:27:3, endln:32:14 + |vpiDirection:2 + |vpiName:b + |vpiClockingIODecl: + \_clocking_io_decl: (doAdd), line:30:15, endln:30:20 + |vpiParent: + \_clocking_block: (work@add_sub_if.cb), line:27:3, endln:32:14 + |vpiDirection:2 + |vpiName:doAdd + |vpiClockingIODecl: + \_clocking_io_decl: (result), line:31:15, endln:31:21 + |vpiParent: + \_clocking_block: (work@add_sub_if.cb), line:27:3, endln:32:14 + |vpiDirection:1 + |vpiName:result + |vpiPort: + \_port: (clk), line:20:13, endln:20:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiName:clk + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@add_sub_if.clk.clk), line:20:13, endln:20:16 + |vpiParent: + \_port: (clk), line:20:13, endln:20:16 + |vpiName:clk + |vpiFullName:work@add_sub_if.clk.clk + |vpiActual: + \_logic_net: (work@add_sub_if.clk), line:20:13, endln:20:16 + |vpiPort: + \_port: (a), line:21:15, endln:21:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiName:a + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@add_sub_if.a.a), line:21:15, endln:21:16 + |vpiParent: + \_port: (a), line:21:15, endln:21:16 + |vpiName:a + |vpiFullName:work@add_sub_if.a.a + |vpiActual: + \_logic_net: (work@add_sub_if.a), line:21:15, endln:21:16 + |vpiPort: + \_port: (b), line:22:15, endln:22:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiName:b + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@add_sub_if.b.b), line:22:15, endln:22:16 + |vpiParent: + \_port: (b), line:22:15, endln:22:16 + |vpiName:b + |vpiFullName:work@add_sub_if.b.b + |vpiActual: + \_logic_net: (work@add_sub_if.b), line:22:15, endln:22:16 + |vpiPort: + \_port: (doAdd), line:23:15, endln:23:20 + |vpiParent: + \_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiName:doAdd + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@add_sub_if.doAdd.doAdd), line:23:15, endln:23:20 + |vpiParent: + \_port: (doAdd), line:23:15, endln:23:20 + |vpiName:doAdd + |vpiFullName:work@add_sub_if.doAdd.doAdd + |vpiActual: + \_logic_net: (work@add_sub_if.doAdd), line:23:15, endln:23:20 + |vpiPort: + \_port: (result), line:24:15, endln:24:21 + |vpiParent: + \_interface_inst: work@add_sub_if (work@add_sub_if), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:19:1, endln:34:25 + |vpiName:result + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@add_sub_if.result.result), line:24:15, endln:24:21 + |vpiParent: + \_port: (result), line:24:15, endln:24:21 + |vpiName:result + |vpiFullName:work@add_sub_if.result.result + |vpiActual: + \_logic_net: (work@add_sub_if.result), line:24:15, endln:24:21 + |vpiEndLabel:add_sub_if +|uhdmallModules: +\_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiParent: + \_design: (work@ADD_SUB) + |vpiFullName:work@ADD_SUB + |vpiDefName:work@ADD_SUB + |vpiNet: + \_logic_net: (work@ADD_SUB.clk), line:2:20, endln:2:23 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:clk + |vpiFullName:work@ADD_SUB.clk + |vpiNet: + \_logic_net: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:a0 + |vpiFullName:work@ADD_SUB.a0 + |vpiNet: + \_logic_net: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:b0 + |vpiFullName:work@ADD_SUB.b0 + |vpiNet: + \_logic_net: (work@ADD_SUB.doAdd0), line:5:20, endln:5:26 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:doAdd0 + |vpiFullName:work@ADD_SUB.doAdd0 + |vpiNet: + \_logic_net: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:result0 + |vpiFullName:work@ADD_SUB.result0 + |vpiNetType:48 + |vpiPort: + \_port: (clk), line:2:20, endln:2:23 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:clk + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.clk.clk), line:2:20, endln:2:23 + |vpiParent: + \_port: (clk), line:2:20, endln:2:23 + |vpiName:clk + |vpiFullName:work@ADD_SUB.clk.clk + |vpiActual: + \_logic_net: (work@ADD_SUB.clk), line:2:20, endln:2:23 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.clk) + |vpiParent: + \_port: (clk), line:2:20, endln:2:23 + |vpiFullName:work@ADD_SUB.clk + |vpiActual: + \_logic_typespec: , line:2:20, endln:2:20 + |vpiPort: + \_port: (a0), line:3:20, endln:3:22 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:a0 + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.a0.a0), line:3:20, endln:3:22 + |vpiParent: + \_port: (a0), line:3:20, endln:3:22 + |vpiName:a0 + |vpiFullName:work@ADD_SUB.a0.a0 + |vpiActual: + \_logic_net: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.a0) + |vpiParent: + \_port: (a0), line:3:20, endln:3:22 + |vpiFullName:work@ADD_SUB.a0 + |vpiActual: + \_logic_typespec: , line:3:9, endln:3:14 + |vpiPort: + \_port: (b0), line:4:20, endln:4:22 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:b0 + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.b0.b0), line:4:20, endln:4:22 + |vpiParent: + \_port: (b0), line:4:20, endln:4:22 + |vpiName:b0 + |vpiFullName:work@ADD_SUB.b0.b0 + |vpiActual: + \_logic_net: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.b0) + |vpiParent: + \_port: (b0), line:4:20, endln:4:22 + |vpiFullName:work@ADD_SUB.b0 + |vpiActual: + \_logic_typespec: , line:4:9, endln:4:14 + |vpiPort: + \_port: (doAdd0), line:5:20, endln:5:26 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:doAdd0 + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.doAdd0.doAdd0), line:5:20, endln:5:26 + |vpiParent: + \_port: (doAdd0), line:5:20, endln:5:26 + |vpiName:doAdd0 + |vpiFullName:work@ADD_SUB.doAdd0.doAdd0 + |vpiActual: + \_logic_net: (work@ADD_SUB.doAdd0), line:5:20, endln:5:26 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.doAdd0) + |vpiParent: + \_port: (doAdd0), line:5:20, endln:5:26 + |vpiFullName:work@ADD_SUB.doAdd0 + |vpiActual: + \_logic_typespec: , line:5:20, endln:5:20 + |vpiPort: + \_port: (result0), line:6:20, endln:6:27 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:result0 + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.result0.result0), line:6:20, endln:6:27 + |vpiParent: + \_port: (result0), line:6:20, endln:6:27 + |vpiName:result0 + |vpiFullName:work@ADD_SUB.result0.result0 + |vpiActual: + \_logic_net: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.result0) + |vpiParent: + \_port: (result0), line:6:20, endln:6:27 + |vpiFullName:work@ADD_SUB.result0 + |vpiActual: + \_logic_typespec: , line:6:10, endln:6:19 + |vpiProcess: + \_always: , line:9:3, endln:15:8 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiStmt: + \_event_control: , line:9:10, endln:9:25 + |vpiParent: + \_always: , line:9:3, endln:15:8 + |vpiCondition: + \_operation: , line:9:13, endln:9:24 + |vpiParent: + \_event_control: , line:9:10, endln:9:25 + |vpiOpType:39 + |vpiOperand: + \_ref_obj: (work@ADD_SUB.clk), line:9:21, endln:9:24 + |vpiParent: + \_operation: , line:9:13, endln:9:24 + |vpiName:clk + |vpiFullName:work@ADD_SUB.clk + |vpiActual: + \_logic_net: (work@ADD_SUB.clk), line:2:20, endln:2:23 + |vpiStmt: + \_begin: (work@ADD_SUB), line:10:5, endln:15:8 + |vpiParent: + \_event_control: , line:9:10, endln:9:25 + |vpiFullName:work@ADD_SUB + |vpiStmt: + \_if_else: , line:11:7, endln:14:28 + |vpiParent: + \_begin: (work@ADD_SUB), line:10:5, endln:15:8 + |vpiCondition: + \_ref_obj: (work@ADD_SUB.doAdd0), line:11:11, endln:11:17 + |vpiParent: + \_begin: (work@ADD_SUB), line:10:5, endln:15:8 + |vpiName:doAdd0 + |vpiFullName:work@ADD_SUB.doAdd0 + |vpiActual: + \_logic_net: (work@ADD_SUB.doAdd0), line:5:20, endln:5:26 + |vpiStmt: + \_assignment: , line:12:9, endln:12:27 + |vpiParent: + \_if_else: , line:11:7, endln:14:28 + |vpiOpType:82 + |vpiRhs: + \_operation: , line:12:20, endln:12:27 + |vpiParent: + \_assignment: , line:12:9, endln:12:27 + |vpiOpType:24 + |vpiOperand: + \_ref_obj: (work@ADD_SUB.a0), line:12:20, endln:12:22 + |vpiParent: + \_operation: , line:12:20, endln:12:27 + |vpiName:a0 + |vpiFullName:work@ADD_SUB.a0 + |vpiActual: + \_logic_net: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiOperand: + \_ref_obj: (work@ADD_SUB.b0), line:12:25, endln:12:27 + |vpiParent: + \_operation: , line:12:20, endln:12:27 + |vpiName:b0 + |vpiFullName:work@ADD_SUB.b0 + |vpiActual: + \_logic_net: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiLhs: + \_ref_obj: (work@ADD_SUB.result0), line:12:9, endln:12:16 + |vpiParent: + \_assignment: , line:12:9, endln:12:27 + |vpiName:result0 + |vpiFullName:work@ADD_SUB.result0 + |vpiActual: + \_logic_net: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiElseStmt: + \_assignment: , line:14:9, endln:14:27 + |vpiParent: + \_if_else: , line:11:7, endln:14:28 + |vpiOpType:82 + |vpiRhs: + \_operation: , line:14:20, endln:14:27 + |vpiParent: + \_assignment: , line:14:9, endln:14:27 + |vpiOpType:11 + |vpiOperand: + \_ref_obj: (work@ADD_SUB.a0), line:14:20, endln:14:22 + |vpiParent: + \_operation: , line:14:20, endln:14:27 + |vpiName:a0 + |vpiFullName:work@ADD_SUB.a0 + |vpiActual: + \_logic_net: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiOperand: + \_ref_obj: (work@ADD_SUB.b0), line:14:25, endln:14:27 + |vpiParent: + \_operation: , line:14:20, endln:14:27 + |vpiName:b0 + |vpiFullName:work@ADD_SUB.b0 + |vpiActual: + \_logic_net: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiLhs: + \_ref_obj: (work@ADD_SUB.result0), line:14:9, endln:14:16 + |vpiParent: + \_assignment: , line:14:9, endln:14:27 + |vpiName:result0 + |vpiFullName:work@ADD_SUB.result0 + |vpiActual: + \_logic_net: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiAlwaysType:1 + |vpiEndLabel:ADD_SUB +|uhdmtopModules: +\_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:work@ADD_SUB + |vpiDefName:work@ADD_SUB + |vpiTop:1 + |vpiNet: + \_logic_net: (work@ADD_SUB.clk), line:2:20, endln:2:23 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiTypespec: + \_ref_typespec: (work@ADD_SUB.clk) + |vpiParent: + \_logic_net: (work@ADD_SUB.clk), line:2:20, endln:2:23 + |vpiFullName:work@ADD_SUB.clk + |vpiActual: + \_logic_typespec: , line:2:20, endln:2:20 + |vpiName:clk + |vpiFullName:work@ADD_SUB.clk + |vpiNet: + \_logic_net: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiTypespec: + \_ref_typespec: (work@ADD_SUB.a0) + |vpiParent: + \_logic_net: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiFullName:work@ADD_SUB.a0 + |vpiActual: + \_logic_typespec: , line:3:9, endln:3:14 + |vpiName:a0 + |vpiFullName:work@ADD_SUB.a0 + |vpiNet: + \_logic_net: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiTypespec: + \_ref_typespec: (work@ADD_SUB.b0) + |vpiParent: + \_logic_net: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiFullName:work@ADD_SUB.b0 + |vpiActual: + \_logic_typespec: , line:4:9, endln:4:14 + |vpiName:b0 + |vpiFullName:work@ADD_SUB.b0 + |vpiNet: + \_logic_net: (work@ADD_SUB.doAdd0), line:5:20, endln:5:26 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiTypespec: + \_ref_typespec: (work@ADD_SUB.doAdd0) + |vpiParent: + \_logic_net: (work@ADD_SUB.doAdd0), line:5:20, endln:5:26 + |vpiFullName:work@ADD_SUB.doAdd0 + |vpiActual: + \_logic_typespec: , line:5:20, endln:5:20 + |vpiName:doAdd0 + |vpiFullName:work@ADD_SUB.doAdd0 + |vpiNet: + \_logic_net: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiTypespec: + \_ref_typespec: (work@ADD_SUB.result0) + |vpiParent: + \_logic_net: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiFullName:work@ADD_SUB.result0 + |vpiActual: + \_logic_typespec: , line:6:10, endln:6:19 + |vpiName:result0 + |vpiFullName:work@ADD_SUB.result0 + |vpiNetType:48 + |vpiTopModule:1 + |vpiPort: + \_port: (clk), line:2:20, endln:2:23 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:clk + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.clk), line:2:20, endln:2:23 + |vpiParent: + \_port: (clk), line:2:20, endln:2:23 + |vpiName:clk + |vpiFullName:work@ADD_SUB.clk + |vpiActual: + \_logic_net: (work@ADD_SUB.clk), line:2:20, endln:2:23 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.clk) + |vpiParent: + \_port: (clk), line:2:20, endln:2:23 + |vpiFullName:work@ADD_SUB.clk + |vpiActual: + \_logic_typespec: , line:2:20, endln:2:20 + |vpiInstance: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiPort: + \_port: (a0), line:3:20, endln:3:22 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:a0 + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiParent: + \_port: (a0), line:3:20, endln:3:22 + |vpiName:a0 + |vpiFullName:work@ADD_SUB.a0 + |vpiActual: + \_logic_net: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.a0) + |vpiParent: + \_port: (a0), line:3:20, endln:3:22 + |vpiFullName:work@ADD_SUB.a0 + |vpiActual: + \_logic_typespec: , line:3:9, endln:3:14 + |vpiInstance: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiPort: + \_port: (b0), line:4:20, endln:4:22 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:b0 + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiParent: + \_port: (b0), line:4:20, endln:4:22 + |vpiName:b0 + |vpiFullName:work@ADD_SUB.b0 + |vpiActual: + \_logic_net: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.b0) + |vpiParent: + \_port: (b0), line:4:20, endln:4:22 + |vpiFullName:work@ADD_SUB.b0 + |vpiActual: + \_logic_typespec: , line:4:9, endln:4:14 + |vpiInstance: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiPort: + \_port: (doAdd0), line:5:20, endln:5:26 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:doAdd0 + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.doAdd0), line:5:20, endln:5:26 + |vpiParent: + \_port: (doAdd0), line:5:20, endln:5:26 + |vpiName:doAdd0 + |vpiFullName:work@ADD_SUB.doAdd0 + |vpiActual: + \_logic_net: (work@ADD_SUB.doAdd0), line:5:20, endln:5:26 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.doAdd0) + |vpiParent: + \_port: (doAdd0), line:5:20, endln:5:26 + |vpiFullName:work@ADD_SUB.doAdd0 + |vpiActual: + \_logic_typespec: , line:5:20, endln:5:20 + |vpiInstance: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiPort: + \_port: (result0), line:6:20, endln:6:27 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:result0 + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiParent: + \_port: (result0), line:6:20, endln:6:27 + |vpiName:result0 + |vpiFullName:work@ADD_SUB.result0 + |vpiActual: + \_logic_net: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.result0) + |vpiParent: + \_port: (result0), line:6:20, endln:6:27 + |vpiFullName:work@ADD_SUB.result0 + |vpiActual: + \_logic_typespec: , line:6:10, endln:6:19 + |vpiInstance: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiInterface: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiName:add_sub_if0 + |vpiFullName:work@ADD_SUB.add_sub_if0 + |vpiVariables: + \_bit_var: (work@ADD_SUB.add_sub_if0.clk), line:20:13, endln:20:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiTypespec: + \_ref_typespec: (work@ADD_SUB.add_sub_if0.clk) + |vpiParent: + \_bit_var: (work@ADD_SUB.add_sub_if0.clk), line:20:13, endln:20:16 + |vpiFullName:work@ADD_SUB.add_sub_if0.clk + |vpiActual: + \_bit_typespec: , line:20:9, endln:20:12 + |vpiName:clk + |vpiFullName:work@ADD_SUB.add_sub_if0.clk + |vpiVisibility:1 + |vpiDefName:work@add_sub_if + |vpiDefFile:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv + |vpiDefLineNo:19 + |vpiNet: + \_logic_net: (work@ADD_SUB.add_sub_if0.a), line:21:15, endln:21:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiTypespec: + \_ref_typespec: (work@ADD_SUB.add_sub_if0.a) + |vpiParent: + \_logic_net: (work@ADD_SUB.add_sub_if0.a), line:21:15, endln:21:16 + |vpiFullName:work@ADD_SUB.add_sub_if0.a + |vpiActual: + \_logic_typespec: , line:21:9, endln:21:14 + |vpiName:a + |vpiFullName:work@ADD_SUB.add_sub_if0.a + |vpiNet: + \_logic_net: (work@ADD_SUB.add_sub_if0.b), line:22:15, endln:22:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiTypespec: + \_ref_typespec: (work@ADD_SUB.add_sub_if0.b) + |vpiParent: + \_logic_net: (work@ADD_SUB.add_sub_if0.b), line:22:15, endln:22:16 + |vpiFullName:work@ADD_SUB.add_sub_if0.b + |vpiActual: + \_logic_typespec: , line:22:9, endln:22:14 + |vpiName:b + |vpiFullName:work@ADD_SUB.add_sub_if0.b + |vpiNet: + \_logic_net: (work@ADD_SUB.add_sub_if0.doAdd), line:23:15, endln:23:20 + |vpiParent: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiTypespec: + \_ref_typespec: (work@ADD_SUB.add_sub_if0.doAdd) + |vpiParent: + \_logic_net: (work@ADD_SUB.add_sub_if0.doAdd), line:23:15, endln:23:20 + |vpiFullName:work@ADD_SUB.add_sub_if0.doAdd + |vpiActual: + \_logic_typespec: , line:23:15, endln:23:15 + |vpiName:doAdd + |vpiFullName:work@ADD_SUB.add_sub_if0.doAdd + |vpiNet: + \_logic_net: (work@ADD_SUB.add_sub_if0.result), line:24:15, endln:24:21 + |vpiParent: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiTypespec: + \_ref_typespec: (work@ADD_SUB.add_sub_if0.result) + |vpiParent: + \_logic_net: (work@ADD_SUB.add_sub_if0.result), line:24:15, endln:24:21 + |vpiFullName:work@ADD_SUB.add_sub_if0.result + |vpiActual: + \_logic_typespec: , line:24:9, endln:24:14 + |vpiName:result + |vpiFullName:work@ADD_SUB.add_sub_if0.result + |vpiInstance: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiClockingBlock: + \_clocking_block: (work@ADD_SUB.add_sub_if0.cb), line:27:3, endln:32:14 + |vpiParent: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiName:cb + |vpiFullName:work@ADD_SUB.add_sub_if0.cb + |vpiClockingEvent: + \_event_control: , line:27:15, endln:27:29 + |vpiParent: + \_clocking_block: (work@ADD_SUB.add_sub_if0.cb), line:27:3, endln:32:14 + |vpiCondition: + \_operation: , line:27:17, endln:27:28 + |vpiParent: + \_event_control: , line:27:15, endln:27:29 + |vpiOpType:39 + |vpiOperand: + \_ref_obj: (work@ADD_SUB.add_sub_if0.cb.clk), line:27:25, endln:27:28 + |vpiParent: + \_operation: , line:27:17, endln:27:28 + |vpiName:clk + |vpiFullName:work@ADD_SUB.add_sub_if0.cb.clk + |vpiActual: + \_bit_var: (work@ADD_SUB.add_sub_if0.clk), line:20:13, endln:20:16 + |vpiClockingIODecl: + \_clocking_io_decl: (a), line:28:15, endln:28:16 + |vpiParent: + \_clocking_block: (work@ADD_SUB.add_sub_if0.cb), line:27:3, endln:32:14 + |vpiDirection:2 + |vpiName:a + |vpiClockingIODecl: + \_clocking_io_decl: (b), line:29:15, endln:29:16 + |vpiParent: + \_clocking_block: (work@ADD_SUB.add_sub_if0.cb), line:27:3, endln:32:14 + |vpiDirection:2 + |vpiName:b + |vpiClockingIODecl: + \_clocking_io_decl: (doAdd), line:30:15, endln:30:20 + |vpiParent: + \_clocking_block: (work@ADD_SUB.add_sub_if0.cb), line:27:3, endln:32:14 + |vpiDirection:2 + |vpiName:doAdd + |vpiClockingIODecl: + \_clocking_io_decl: (result), line:31:15, endln:31:21 + |vpiParent: + \_clocking_block: (work@ADD_SUB.add_sub_if0.cb), line:27:3, endln:32:14 + |vpiDirection:1 + |vpiName:result + |vpiPort: + \_port: (clk), line:20:13, endln:20:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiName:clk + |vpiDirection:1 + |vpiHighConn: + \_ref_obj: (work@ADD_SUB.clk), line:37:8, endln:37:11 + |vpiParent: + \_port: (clk), line:20:13, endln:20:16 + |vpiName:clk + |vpiFullName:work@ADD_SUB.clk + |vpiActual: + \_bit_var: (work@ADD_SUB.add_sub_if0.clk), line:20:13, endln:20:16 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.add_sub_if0.clk), line:37:4, endln:37:7 + |vpiParent: + \_port: (clk), line:20:13, endln:20:16 + |vpiName:clk + |vpiFullName:work@ADD_SUB.add_sub_if0.clk + |vpiActual: + \_bit_var: (work@ADD_SUB.add_sub_if0.clk), line:20:13, endln:20:16 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.add_sub_if0.clk) + |vpiParent: + \_port: (clk), line:20:13, endln:20:16 + |vpiFullName:work@ADD_SUB.add_sub_if0.clk + |vpiActual: + \_bit_typespec: , line:20:9, endln:20:12 + |vpiPort: + \_port: (a), line:21:15, endln:21:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiName:a + |vpiDirection:1 + |vpiHighConn: + \_ref_obj: (work@ADD_SUB.a0), line:38:6, endln:38:8 + |vpiParent: + \_port: (a), line:21:15, endln:21:16 + |vpiName:a0 + |vpiFullName:work@ADD_SUB.a0 + |vpiActual: + \_logic_net: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.add_sub_if0.a), line:38:4, endln:38:5 + |vpiParent: + \_port: (a), line:21:15, endln:21:16 + |vpiName:a + |vpiFullName:work@ADD_SUB.add_sub_if0.a + |vpiActual: + \_logic_net: (work@ADD_SUB.add_sub_if0.a), line:21:15, endln:21:16 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.add_sub_if0.a) + |vpiParent: + \_port: (a), line:21:15, endln:21:16 + |vpiFullName:work@ADD_SUB.add_sub_if0.a + |vpiActual: + \_logic_typespec: , line:21:9, endln:21:14 + |vpiPort: + \_port: (b), line:22:15, endln:22:16 + |vpiParent: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiName:b + |vpiDirection:1 + |vpiHighConn: + \_ref_obj: (work@ADD_SUB.b0), line:39:6, endln:39:8 + |vpiParent: + \_port: (b), line:22:15, endln:22:16 + |vpiName:b0 + |vpiFullName:work@ADD_SUB.b0 + |vpiActual: + \_logic_net: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.add_sub_if0.b), line:39:4, endln:39:5 + |vpiParent: + \_port: (b), line:22:15, endln:22:16 + |vpiName:b + |vpiFullName:work@ADD_SUB.add_sub_if0.b + |vpiActual: + \_logic_net: (work@ADD_SUB.add_sub_if0.b), line:22:15, endln:22:16 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.add_sub_if0.b) + |vpiParent: + \_port: (b), line:22:15, endln:22:16 + |vpiFullName:work@ADD_SUB.add_sub_if0.b + |vpiActual: + \_logic_typespec: , line:22:9, endln:22:14 + |vpiPort: + \_port: (doAdd), line:23:15, endln:23:20 + |vpiParent: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiName:doAdd + |vpiDirection:1 + |vpiHighConn: + \_ref_obj: (work@ADD_SUB.doAdd0), line:40:10, endln:40:16 + |vpiParent: + \_port: (doAdd), line:23:15, endln:23:20 + |vpiName:doAdd0 + |vpiFullName:work@ADD_SUB.doAdd0 + |vpiActual: + \_logic_net: (work@ADD_SUB.doAdd0), line:5:20, endln:5:26 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.add_sub_if0.doAdd), line:40:4, endln:40:9 + |vpiParent: + \_port: (doAdd), line:23:15, endln:23:20 + |vpiName:doAdd + |vpiFullName:work@ADD_SUB.add_sub_if0.doAdd + |vpiActual: + \_logic_net: (work@ADD_SUB.add_sub_if0.doAdd), line:23:15, endln:23:20 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.add_sub_if0.doAdd) + |vpiParent: + \_port: (doAdd), line:23:15, endln:23:20 + |vpiFullName:work@ADD_SUB.add_sub_if0.doAdd + |vpiActual: + \_logic_typespec: , line:23:15, endln:23:15 + |vpiPort: + \_port: (result), line:24:15, endln:24:21 + |vpiParent: + \_interface_inst: work@add_sub_if (work@ADD_SUB.add_sub_if0), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:36:14, endln:42:3 + |vpiName:result + |vpiDirection:1 + |vpiHighConn: + \_ref_obj: (work@ADD_SUB.result0), line:41:11, endln:41:18 + |vpiParent: + \_port: (result), line:24:15, endln:24:21 + |vpiName:result0 + |vpiFullName:work@ADD_SUB.result0 + |vpiActual: + \_logic_net: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiLowConn: + \_ref_obj: (work@ADD_SUB.add_sub_if0.result), line:41:4, endln:41:10 + |vpiParent: + \_port: (result), line:24:15, endln:24:21 + |vpiName:result + |vpiFullName:work@ADD_SUB.add_sub_if0.result + |vpiActual: + \_logic_net: (work@ADD_SUB.add_sub_if0.result), line:24:15, endln:24:21 + |vpiTypedef: + \_ref_typespec: (work@ADD_SUB.add_sub_if0.result) + |vpiParent: + \_port: (result), line:24:15, endln:24:21 + |vpiFullName:work@ADD_SUB.add_sub_if0.result + |vpiActual: + \_logic_typespec: , line:24:9, endln:24:14 + |vpiProcess: + \_always: , line:9:3, endln:15:8 + |vpiParent: + \_module_inst: work@ADD_SUB (work@ADD_SUB), file:${SURELOG_DIR}/tests/InterfaceBinding/dut.sv, line:1:1, endln:17:19 + |vpiStmt: + \_event_control: , line:9:10, endln:9:25 + |vpiParent: + \_always: , line:9:3, endln:15:8 + |vpiCondition: + \_operation: , line:9:13, endln:9:24 + |vpiParent: + \_event_control: , line:9:10, endln:9:25 + |vpiOpType:39 + |vpiOperand: + \_ref_obj: (work@ADD_SUB.clk), line:9:21, endln:9:24 + |vpiParent: + \_operation: , line:9:13, endln:9:24 + |vpiName:clk + |vpiFullName:work@ADD_SUB.clk + |vpiActual: + \_logic_net: (work@ADD_SUB.clk), line:2:20, endln:2:23 + |vpiStmt: + \_begin: (work@ADD_SUB), line:10:5, endln:15:8 + |vpiParent: + \_event_control: , line:9:10, endln:9:25 + |vpiFullName:work@ADD_SUB + |vpiStmt: + \_if_else: , line:11:7, endln:14:28 + |vpiParent: + \_begin: (work@ADD_SUB), line:10:5, endln:15:8 + |vpiCondition: + \_ref_obj: (work@ADD_SUB.doAdd0), line:11:11, endln:11:17 + |vpiParent: + \_if_else: , line:11:7, endln:14:28 + |vpiName:doAdd0 + |vpiFullName:work@ADD_SUB.doAdd0 + |vpiActual: + \_logic_net: (work@ADD_SUB.doAdd0), line:5:20, endln:5:26 + |vpiStmt: + \_assignment: , line:12:9, endln:12:27 + |vpiParent: + \_if_else: , line:11:7, endln:14:28 + |vpiOpType:82 + |vpiRhs: + \_operation: , line:12:20, endln:12:27 + |vpiParent: + \_assignment: , line:12:9, endln:12:27 + |vpiOpType:24 + |vpiOperand: + \_ref_obj: (work@ADD_SUB.a0), line:12:20, endln:12:22 + |vpiParent: + \_operation: , line:12:20, endln:12:27 + |vpiName:a0 + |vpiFullName:work@ADD_SUB.a0 + |vpiActual: + \_logic_net: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiOperand: + \_ref_obj: (work@ADD_SUB.b0), line:12:25, endln:12:27 + |vpiParent: + \_operation: , line:12:20, endln:12:27 + |vpiName:b0 + |vpiFullName:work@ADD_SUB.b0 + |vpiActual: + \_logic_net: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiLhs: + \_ref_obj: (work@ADD_SUB.result0), line:12:9, endln:12:16 + |vpiParent: + \_assignment: , line:12:9, endln:12:27 + |vpiName:result0 + |vpiFullName:work@ADD_SUB.result0 + |vpiActual: + \_logic_net: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiElseStmt: + \_assignment: , line:14:9, endln:14:27 + |vpiParent: + \_if_else: , line:11:7, endln:14:28 + |vpiOpType:82 + |vpiRhs: + \_operation: , line:14:20, endln:14:27 + |vpiParent: + \_assignment: , line:14:9, endln:14:27 + |vpiOpType:11 + |vpiOperand: + \_ref_obj: (work@ADD_SUB.a0), line:14:20, endln:14:22 + |vpiParent: + \_operation: , line:14:20, endln:14:27 + |vpiName:a0 + |vpiFullName:work@ADD_SUB.a0 + |vpiActual: + \_logic_net: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiOperand: + \_ref_obj: (work@ADD_SUB.b0), line:14:25, endln:14:27 + |vpiParent: + \_operation: , line:14:20, endln:14:27 + |vpiName:b0 + |vpiFullName:work@ADD_SUB.b0 + |vpiActual: + \_logic_net: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiLhs: + \_ref_obj: (work@ADD_SUB.result0), line:14:9, endln:14:16 + |vpiParent: + \_assignment: , line:14:9, endln:14:27 + |vpiName:result0 + |vpiFullName:work@ADD_SUB.result0 + |vpiActual: + \_logic_net: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiAlwaysType:1 +\_weaklyReferenced: +\_logic_typespec: , line:2:20, endln:2:20 +\_logic_typespec: , line:3:9, endln:3:14 + |vpiRange: + \_range: , line:3:9, endln:3:14 + |vpiParent: + \_logic_typespec: , line:3:9, endln:3:14 + |vpiLeftRange: + \_constant: , line:3:10, endln:3:11 + |vpiParent: + \_range: , line:3:9, endln:3:14 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:3:12, endln:3:13 + |vpiParent: + \_range: , line:3:9, endln:3:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:4:9, endln:4:14 + |vpiRange: + \_range: , line:4:9, endln:4:14 + |vpiParent: + \_logic_typespec: , line:4:9, endln:4:14 + |vpiLeftRange: + \_constant: , line:4:10, endln:4:11 + |vpiParent: + \_range: , line:4:9, endln:4:14 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:4:12, endln:4:13 + |vpiParent: + \_range: , line:4:9, endln:4:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:5:20, endln:5:20 +\_logic_typespec: , line:6:10, endln:6:19 + |vpiRange: + \_range: , line:6:14, endln:6:19 + |vpiParent: + \_logic_typespec: , line:6:10, endln:6:19 + |vpiLeftRange: + \_constant: , line:6:15, endln:6:16 + |vpiParent: + \_range: , line:6:14, endln:6:19 + |vpiDecompile:8 + |vpiSize:64 + |UINT:8 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:6:17, endln:6:18 + |vpiParent: + \_range: , line:6:14, endln:6:19 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:2:20, endln:2:20 + |vpiParent: + \_logic_net: (work@ADD_SUB.clk), line:2:20, endln:2:23 +\_logic_typespec: , line:3:9, endln:3:14 + |vpiParent: + \_logic_net: (work@ADD_SUB.a0), line:3:20, endln:3:22 + |vpiRange: + \_range: , line:3:9, endln:3:14 + |vpiParent: + \_logic_typespec: , line:3:9, endln:3:14 + |vpiLeftRange: + \_constant: , line:3:10, endln:3:11 + |vpiParent: + \_range: , line:3:9, endln:3:14 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:3:12, endln:3:13 + |vpiParent: + \_range: , line:3:9, endln:3:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:4:9, endln:4:14 + |vpiParent: + \_logic_net: (work@ADD_SUB.b0), line:4:20, endln:4:22 + |vpiRange: + \_range: , line:4:9, endln:4:14 + |vpiParent: + \_logic_typespec: , line:4:9, endln:4:14 + |vpiLeftRange: + \_constant: , line:4:10, endln:4:11 + |vpiParent: + \_range: , line:4:9, endln:4:14 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:4:12, endln:4:13 + |vpiParent: + \_range: , line:4:9, endln:4:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:5:20, endln:5:20 + |vpiParent: + \_logic_net: (work@ADD_SUB.doAdd0), line:5:20, endln:5:26 +\_logic_typespec: , line:6:10, endln:6:19 + |vpiParent: + \_logic_net: (work@ADD_SUB.result0), line:6:20, endln:6:27 + |vpiRange: + \_range: , line:6:14, endln:6:19 + |vpiParent: + \_logic_typespec: , line:6:10, endln:6:19 + |vpiLeftRange: + \_constant: , line:6:15, endln:6:16 + |vpiParent: + \_range: , line:6:14, endln:6:19 + |vpiDecompile:8 + |vpiSize:64 + |UINT:8 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:6:17, endln:6:18 + |vpiParent: + \_range: , line:6:14, endln:6:19 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_bit_typespec: , line:20:9, endln:20:12 +\_logic_typespec: , line:21:9, endln:21:14 + |vpiRange: + \_range: , line:21:9, endln:21:14 + |vpiParent: + \_logic_typespec: , line:21:9, endln:21:14 + |vpiLeftRange: + \_constant: , line:21:10, endln:21:11 + |vpiParent: + \_range: , line:21:9, endln:21:14 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:21:12, endln:21:13 + |vpiParent: + \_range: , line:21:9, endln:21:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:22:9, endln:22:14 + |vpiRange: + \_range: , line:22:9, endln:22:14 + |vpiParent: + \_logic_typespec: , line:22:9, endln:22:14 + |vpiLeftRange: + \_constant: , line:22:10, endln:22:11 + |vpiParent: + \_range: , line:22:9, endln:22:14 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:22:12, endln:22:13 + |vpiParent: + \_range: , line:22:9, endln:22:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:23:15, endln:23:15 +\_logic_typespec: , line:24:9, endln:24:14 + |vpiRange: + \_range: , line:24:9, endln:24:14 + |vpiParent: + \_logic_typespec: , line:24:9, endln:24:14 + |vpiLeftRange: + \_constant: , line:24:10, endln:24:11 + |vpiParent: + \_range: , line:24:9, endln:24:14 + |vpiDecompile:8 + |vpiSize:64 + |UINT:8 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:24:12, endln:24:13 + |vpiParent: + \_range: , line:24:9, endln:24:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_bit_typespec: , line:20:9, endln:20:12 + |vpiParent: + \_bit_var: (work@ADD_SUB.add_sub_if0.clk), line:20:13, endln:20:16 +\_logic_typespec: , line:21:9, endln:21:14 + |vpiParent: + \_logic_net: (work@ADD_SUB.add_sub_if0.a), line:21:15, endln:21:16 + |vpiRange: + \_range: , line:21:9, endln:21:14 + |vpiParent: + \_logic_typespec: , line:21:9, endln:21:14 + |vpiLeftRange: + \_constant: , line:21:10, endln:21:11 + |vpiParent: + \_range: , line:21:9, endln:21:14 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:21:12, endln:21:13 + |vpiParent: + \_range: , line:21:9, endln:21:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:22:9, endln:22:14 + |vpiParent: + \_logic_net: (work@ADD_SUB.add_sub_if0.b), line:22:15, endln:22:16 + |vpiRange: + \_range: , line:22:9, endln:22:14 + |vpiParent: + \_logic_typespec: , line:22:9, endln:22:14 + |vpiLeftRange: + \_constant: , line:22:10, endln:22:11 + |vpiParent: + \_range: , line:22:9, endln:22:14 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:22:12, endln:22:13 + |vpiParent: + \_range: , line:22:9, endln:22:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:23:15, endln:23:15 + |vpiParent: + \_logic_net: (work@ADD_SUB.add_sub_if0.doAdd), line:23:15, endln:23:20 +\_logic_typespec: , line:24:9, endln:24:14 + |vpiParent: + \_logic_net: (work@ADD_SUB.add_sub_if0.result), line:24:15, endln:24:21 + |vpiRange: + \_range: , line:24:9, endln:24:14 + |vpiParent: + \_logic_typespec: , line:24:9, endln:24:14 + |vpiLeftRange: + \_constant: , line:24:10, endln:24:11 + |vpiParent: + \_range: , line:24:9, endln:24:14 + |vpiDecompile:8 + |vpiSize:64 + |UINT:8 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:24:12, endln:24:13 + |vpiParent: + \_range: , line:24:9, endln:24:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:2:20, endln:2:20 +\_logic_typespec: , line:3:9, endln:3:14 + |vpiRange: + \_range: , line:3:9, endln:3:14 + |vpiParent: + \_logic_typespec: , line:3:9, endln:3:14 + |vpiLeftRange: + \_constant: , line:3:10, endln:3:11 + |vpiParent: + \_range: , line:3:9, endln:3:14 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:3:12, endln:3:13 + |vpiParent: + \_range: , line:3:9, endln:3:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:4:9, endln:4:14 + |vpiRange: + \_range: , line:4:9, endln:4:14 + |vpiParent: + \_logic_typespec: , line:4:9, endln:4:14 + |vpiLeftRange: + \_constant: , line:4:10, endln:4:11 + |vpiParent: + \_range: , line:4:9, endln:4:14 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:4:12, endln:4:13 + |vpiParent: + \_range: , line:4:9, endln:4:14 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:5:20, endln:5:20 +\_logic_typespec: , line:6:10, endln:6:19 + |vpiRange: + \_range: , line:6:14, endln:6:19 + |vpiParent: + \_logic_typespec: , line:6:10, endln:6:19 + |vpiLeftRange: + \_constant: , line:6:15, endln:6:16 + |vpiParent: + \_range: , line:6:14, endln:6:19 + |vpiDecompile:8 + |vpiSize:64 + |UINT:8 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:6:17, endln:6:18 + |vpiParent: + \_range: , line:6:14, endln:6:19 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +=================== +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 2 +[ NOTE] : 5 + +============================== Begin Linting Results ============================== +[LINT]: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:28:15: Non synthesizable construct, a +[LINT]: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:29:15: Non synthesizable construct, b +[LINT]: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:30:15: Non synthesizable construct, doAdd +[LINT]: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:31:15: Non synthesizable construct, result +[LINT]: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:27:3: Non synthesizable construct, cb +[LINT]: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:28:15: Non synthesizable construct, a +[LINT]: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:29:15: Non synthesizable construct, b +[LINT]: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:30:15: Non synthesizable construct, doAdd +[LINT]: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:31:15: Non synthesizable construct, result +[LINT]: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv:27:3: Non synthesizable construct, cb +============================== End Linting Results ============================== + +============================== Begin RoundTrip Results ============================== +[roundtrip]: ${SURELOG_DIR}/tests/InterfaceBinding/dut.sv | ${SURELOG_DIR}/build/regression/InterfaceBinding/roundtrip/dut_000.sv | 17 | 34 | +============================== End RoundTrip Results ============================== diff --git a/tests/InterfaceBinding/InterfaceBinding.sl b/tests/InterfaceBinding/InterfaceBinding.sl new file mode 100644 index 0000000000..b461620aca --- /dev/null +++ b/tests/InterfaceBinding/InterfaceBinding.sl @@ -0,0 +1 @@ +-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin diff --git a/tests/InterfaceBinding/dut.sv b/tests/InterfaceBinding/dut.sv new file mode 100644 index 0000000000..a2598fd205 --- /dev/null +++ b/tests/InterfaceBinding/dut.sv @@ -0,0 +1,42 @@ +module ADD_SUB( + input clk, + input [7:0] a0, + input [7:0] b0, + input doAdd0, + output reg [8:0] result0 +); + + always @ (posedge clk) + begin + if (doAdd0) + result0 <= a0 + b0; + else + result0 <= a0 - b0; + end + +endmodule: ADD_SUB + +interface add_sub_if( + input bit clk, + input [7:0] a, + input [7:0] b, + input doAdd, + input [8:0] result +); + + clocking cb @(posedge clk); + output a; + output b; + output doAdd; + input result; + endclocking + +endinterface: add_sub_if + +bind ADD_SUB add_sub_if add_sub_if0( + .clk(clk), + .a(a0), + .b(b0), + .doAdd(doAdd0), + .result(result0) +); \ No newline at end of file diff --git a/third_party/UHDM b/third_party/UHDM index 857f68de3c..7d90dd0e68 160000 --- a/third_party/UHDM +++ b/third_party/UHDM @@ -1 +1 @@ -Subproject commit 857f68de3ce5b6f919f3a0f489c93072751b1578 +Subproject commit 7d90dd0e68759775d0c86885d991925096b5b496 diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index c0b0527dd6..b3dabfd78d 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -74,11 +74,11 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; [ 50%] Generating 1_lsu_stbuf.sv [ 56%] Generating 2_ahb_to_axi4.sv [ 62%] Generating 3_rvjtag_tap.sv -[ 68%] Generating 4_dec_tlu_ctl.sv -[ 75%] Generating 5_lsu_bus_buffer.sv +[ 68%] Generating 5_lsu_bus_buffer.sv +[ 75%] Generating 4_dec_tlu_ctl.sv [ 81%] Generating 6_dbg.sv [ 87%] Generating 7_axi4_to_ahb.sv -[ 93%] Generating 8_ifu_aln_ctl.sv +[100%] Generating 8_ifu_aln_ctl.sv [100%] Generating 9_tb_top.sv [100%] Built target Parse Surelog parsing status: 0 diff --git a/third_party/tests/SimpleUVM/SimpleUVM.log b/third_party/tests/SimpleUVM/SimpleUVM.log index 32650fb1ce..67ca23a1b9 100644 --- a/third_party/tests/SimpleUVM/SimpleUVM.log +++ b/third_party/tests/SimpleUVM/SimpleUVM.log @@ -385,8 +385,8 @@ array_var 576 assignment 9840 begin 6779 bit_select 2126 -bit_typespec 3078 -bit_var 1196 +bit_typespec 3076 +bit_var 1195 break_stmt 53 byte_typespec 120 byte_var 38 @@ -397,9 +397,9 @@ chandle_var 2 class_defn 615 class_typespec 8549 class_var 3294 -clocking_block 3 -clocking_io_decl 12 -constant 28594 +clocking_block 2 +clocking_io_decl 8 +constant 28576 constraint 4 continue_stmt 52 delay_control 54 @@ -409,7 +409,7 @@ do_while 51 enum_const 551 enum_typespec 93 enum_var 186 -event_control 19 +event_control 18 event_stmt 10 event_typespec 10 extends 279 @@ -429,32 +429,32 @@ indexed_part_select 41 initial 3 int_typespec 2767 int_var 1363 -interface_inst 5 +interface_inst 3 interface_typespec 1 io_decl 6908 -logic_net 246 -logic_typespec 109 +logic_net 242 +logic_typespec 101 logic_var 49 long_int_typespec 99 long_int_var 20 method_func_call 8000 -module_inst 34 +module_inst 33 named_begin 6 named_event 8 named_fork 3 -operation 10004 +operation 10003 package 4 packed_array_typespec 8 param_assign 468 parameter 673 part_select 43 -port 26 -range 2915 +port 21 +range 2906 real_typespec 33 real_var 8 ref_module 1 -ref_obj 41230 -ref_typespec 20779 +ref_obj 41219 +ref_typespec 20769 ref_var 1788 repeat 27 return_stmt 3272 @@ -3911,11 +3911,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:35:15: Non synthesizable construct, doAdd [LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:36:15: Non synthesizable construct, result [LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:32:3: Non synthesizable construct, cb -[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:33:15: Non synthesizable construct, a -[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:34:15: Non synthesizable construct, b -[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:35:15: Non synthesizable construct, doAdd -[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:36:15: Non synthesizable construct, result -[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:32:3: Non synthesizable construct, cb [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_agent.svh:67:6: Unsupported typespec, uvm_resource_types::rsrc_q_t [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/macros/uvm_resource_defines.svh:123:6: Unsupported typespec, __tmp_int_t__ [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_traversal.svh:168:13: Unsupported typespec, c