diff --git a/src/SourceCompile/Compiler.cpp b/src/SourceCompile/Compiler.cpp index 8f51142e8a..d49a734c0e 100644 --- a/src/SourceCompile/Compiler.cpp +++ b/src/SourceCompile/Compiler.cpp @@ -46,6 +46,7 @@ #include #include +#include #include #include @@ -210,11 +211,39 @@ bool Compiler::ppinit_() { fileSystem->collect(libFileId, m_commandLineParser->getSymbolTable()->getSymbol(ext), m_commandLineParser->getSymbolTable(), fileIds); - std::copy_if(fileIds.begin(), fileIds.end(), - std::inserter(libFileIdSet, libFileIdSet.end()), - [&sourceFiles](const PathId& libFileId) { - return sourceFiles.find(libFileId) == sourceFiles.end(); - }); + std::copy_if( + fileIds.begin(), fileIds.end(), + std::inserter(libFileIdSet, libFileIdSet.end()), + [&](const PathId& libFileId) { + if (sourceFiles.find(libFileId) == sourceFiles.end()) { + bool fileContainsModuleOfSameName = false; + std::filesystem::path dir_entry = fileSystem->toPath(libFileId); + std::ifstream ifs(dir_entry.string()); + if (ifs.good()) { + std::stringstream buffer; + buffer << ifs.rdbuf(); + std::string moduleName = dir_entry.stem().string(); + const std::regex regexpMod{"(module)[ ]+(" + moduleName + ")"}; + if (std::regex_search(buffer.str(), regexpMod)) { + fileContainsModuleOfSameName = true; + } + const std::regex regexpPrim{"(primitive)[ ]+(" + moduleName + + ")"}; + if (std::regex_search(buffer.str(), regexpPrim)) { + fileContainsModuleOfSameName = true; + } + const std::regex regexpPack{"(package)[ ]"}; + if (std::regex_search(buffer.str(), regexpPack)) { + // Files containing packages cannot be imported with -y + fileContainsModuleOfSameName = false; + } + } + ifs.close(); + return fileContainsModuleOfSameName; + } else { + return false; + } + }); } } for (const auto& libFileId : libFileIdSet) { diff --git a/tests/DashYTest/lib/BAD.v b/tests/DashYTest/lib/BAD.v new file mode 100644 index 0000000000..06c94d813b --- /dev/null +++ b/tests/DashYTest/lib/BAD.v @@ -0,0 +1,2 @@ +module MODULE_NAME_DOES_NOT_MATCH_FILE_NAME(); +endmodule diff --git a/third_party/tests/oh/BasicOh.log b/third_party/tests/oh/BasicOh.log index 27b3ecd606..c2febeb660 100644 --- a/third_party/tests/oh/BasicOh.log +++ b/third_party/tests/oh/BasicOh.log @@ -63,7 +63,6 @@ [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". @@ -203,7 +202,6 @@ [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". @@ -420,7 +418,6 @@ [INF:CP0303] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v:7:1: Compile module "work@oh_xor2". [INF:CP0303] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v:7:1: Compile module "work@oh_xor3". [INF:CP0303] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v:7:1: Compile module "work@oh_xor4". -[INF:CP0303] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v:8:1: Compile module "work@ohr_reg0". [INF:CP0302] Compile class "work@mailbox". [INF:CP0302] Compile class "work@process". [INF:CP0302] Compile class "work@semaphore". @@ -560,7 +557,6 @@ there are 1 more instances of this message. [NTE:CP0309] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v:11:21: Implicit port type (wire) for "z". [NTE:CP0309] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v:12:21: Implicit port type (wire) for "z". [NTE:CP0309] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v:13:21: Implicit port type (wire) for "z". -[NTE:CP0309] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v:13:21: Implicit port type (wire) for "out". [INF:EL0526] Design Elaboration... [INF:CP0335] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v:22:5: Compile generate block "work@oh_fifo_async.wr_rsync.genblk1". [INF:CP0335] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v:22:5: Compile generate block "work@oh_fifo_async.rd_rsync.genblk1". @@ -656,24 +652,24 @@ Instance tree: [NTE:EL0522] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v:48:3: Scope "work@oh_fifo_async.oh_memory_dp.genblk1". [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -always 77 +always 76 array_net 1 array_typespec 2 array_var 2 assign_stmt 30 -assignment 159 +assignment 157 begin 97 bit_select 114 class_defn 8 class_typespec 4 class_var 3 -constant 2477 -cont_assign 206 +constant 2465 +cont_assign 205 design 1 enum_const 5 enum_typespec 1 enum_var 1 -event_control 75 +event_control 74 for_stmt 7 function 9 gen_for 5 @@ -682,10 +678,10 @@ gen_if_else 29 gen_region 32 gen_scope 30 gen_scope_array 30 -if_else 58 +if_else 57 if_stmt 28 indexed_part_select 3 -int_typespec 353 +int_typespec 352 int_var 4 integer_typespec 8 integer_var 6 @@ -694,19 +690,19 @@ logic_net 201 logic_typespec 318 logic_var 16 module_array 4 -module_inst 193 +module_inst 192 module_typespec 4 named_begin 9 -operation 1736 +operation 1727 package 2 -param_assign 323 -parameter 323 -part_select 551 +param_assign 322 +parameter 322 +part_select 546 port 419 range 206 ref_module 47 -ref_obj 1858 -ref_typespec 1150 +ref_obj 1850 +ref_typespec 1148 ref_var 12 string_typespec 114 sys_func_call 14 @@ -716,24 +712,24 @@ var_select 6 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -always 109 +always 108 array_net 1 array_typespec 2 array_var 2 assign_stmt 33 -assignment 224 +assignment 222 begin 99 bit_select 179 class_defn 8 class_typespec 4 class_var 3 -constant 2510 -cont_assign 241 +constant 2498 +cont_assign 240 design 1 enum_const 10 enum_typespec 2 enum_var 1 -event_control 107 +event_control 106 for_stmt 10 function 18 gen_for 5 @@ -742,10 +738,10 @@ gen_if_else 29 gen_region 32 gen_scope 57 gen_scope_array 57 -if_else 86 +if_else 85 if_stmt 32 indexed_part_select 3 -int_typespec 353 +int_typespec 352 int_var 4 integer_typespec 8 integer_var 7 @@ -754,19 +750,19 @@ logic_net 201 logic_typespec 318 logic_var 16 module_array 4 -module_inst 193 +module_inst 192 module_typespec 4 named_begin 9 -operation 2080 +operation 2071 package 2 -param_assign 323 -parameter 323 -part_select 716 +param_assign 322 +parameter 322 +part_select 711 port 570 range 206 ref_module 47 -ref_obj 2264 -ref_typespec 1307 +ref_obj 2256 +ref_typespec 1305 ref_var 15 string_typespec 114 sys_func_call 14 @@ -27950,4 +27946,4 @@ design: (work@oh_fifo_async) [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 -[ NOTE] : 162 +[ NOTE] : 161