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Test Surelog against XilinxUnisimLibrary #568
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Are they in sv-test? |
It does parse all of them except 2 syntax errors of the same type in a specify block. https://github.com/alainmarcel/Surelog/blob/master/third_party/tests/XilinxUnisimLibrary/Unisim.log [ FATAL] : 0 |
See https://github.com/SymbiFlow/sv-tests/issues/903 for the sv-test issue |
@alaindargelas - The upstream sim models has been updated with the missing |
I would like to know if Surelog is able to parse the files found in the library at https://github.com/SymbiFlow/XilinxUnisimLibrary
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