From 7d49b6356f8044332f4acf6cb07467ba67fd201c Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 9 Jan 2024 11:30:37 -0800 Subject: [PATCH] enum val binding --- src/DesignCompile/UhdmWriter.cpp | 15 +++++++++++++++ tests/DefaultNetType/DefaultNetType.log | 3 +-- tests/InterfArrayBind/InterfArrayBind.log | 15 ++++----------- third_party/tests/CoresSweRVMP/CoresSweRVMP.log | 6 +++--- .../tests/NyuziProcessor/NyuziProcessor.log | 4 ++-- third_party/tests/Scr1/Scr1.log | 2 +- third_party/tests/Scr1SvTests/Scr1SvTests.log | 2 +- third_party/tests/Zachjs/Zachjs.log | 16 ++-------------- 8 files changed, 29 insertions(+), 34 deletions(-) diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp index 4079893312..5e2a333a38 100644 --- a/src/DesignCompile/UhdmWriter.cpp +++ b/src/DesignCompile/UhdmWriter.cpp @@ -3557,6 +3557,21 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) { ref->Actual_group(n); break; } + if (const ref_typespec* reftps = n->Typespec()) { + const typespec* tps = reftps->Actual_typespec(); + if (tps->UhdmType() == uhdmenum_typespec) { + const enum_typespec* etps = any_cast(tps); + if (etps && etps->Enum_consts()) { + for (auto c : *etps->Enum_consts()) { + if (c->VpiName() == name) { + ref->Actual_group(c); + break; + } + } + if (ref->Actual_group()) break; + } + } + } } if (ref->Actual_group()) continue; } diff --git a/tests/DefaultNetType/DefaultNetType.log b/tests/DefaultNetType/DefaultNetType.log index d0960a7ea7..801e8efb77 100644 --- a/tests/DefaultNetType/DefaultNetType.log +++ b/tests/DefaultNetType/DefaultNetType.log @@ -391,7 +391,6 @@ AST_DEBUG_END [ERR:EL0535] ${SURELOG_DIR}/tests/DefaultNetType/dut.sv:16:8: Illegal implicit net "b". [ERR:EL0535] ${SURELOG_DIR}/tests/DefaultNetType/dut.sv:32:21: Illegal implicit net "clock". [ERR:EL0535] ${SURELOG_DIR}/tests/DefaultNetType/dut.sv:33:4: Illegal implicit net "clear". -[ERR:EL0535] ${SURELOG_DIR}/tests/DefaultNetType/dut.sv:34:21: Illegal implicit net "S_A". [ERR:EL0535] ${SURELOG_DIR}/tests/DefaultNetType/dut.sv:40:14: Illegal implicit net "mode". [ERR:EL0535] ${SURELOG_DIR}/tests/DefaultNetType/dut.sv:41:21: Illegal implicit net "operation". [ERR:EL0535] ${SURELOG_DIR}/tests/DefaultNetType/dut.sv:42:21: Illegal implicit net "operation". @@ -1517,7 +1516,7 @@ design: (work@ok) =================== [ FATAL] : 0 [ SYNTAX] : 0 -[ ERROR] : 9 +[ ERROR] : 8 [WARNING] : 4 [ NOTE] : 8 diff --git a/tests/InterfArrayBind/InterfArrayBind.log b/tests/InterfArrayBind/InterfArrayBind.log index fabc24f2d1..ab4a010045 100644 --- a/tests/InterfArrayBind/InterfArrayBind.log +++ b/tests/InterfArrayBind/InterfArrayBind.log @@ -226,7 +226,7 @@ gen_scope_array 4 hier_path 6 int_typespec 5 interface_inst 5 -logic_net 3 +logic_net 2 logic_typespec 5 logic_var 2 module_array 1 @@ -256,7 +256,7 @@ gen_scope_array 6 hier_path 9 int_typespec 5 interface_inst 5 -logic_net 3 +logic_net 2 logic_typespec 5 logic_var 2 module_array 1 @@ -353,13 +353,6 @@ design: (work@soc_tb) \_enum_typespec: |vpiName:io_bus_source |vpiFullName:work@soc_tb.io_bus_source - |vpiNet: - \_logic_net: (work@soc_tb.IO_ONES), line:16:30, endln:16:37 - |vpiParent: - \_module_inst: work@soc_tb (work@soc_tb), file:${SURELOG_DIR}/tests/InterfArrayBind/dut.sv, line:6:1, endln:26:10 - |vpiName:IO_ONES - |vpiFullName:work@soc_tb.IO_ONES - |vpiNetType:1 |vpiModuleArray: \_module_array: (work@io_bus_interface), line:14:22, endln:14:39 |vpiParent: @@ -433,7 +426,7 @@ design: (work@soc_tb) |vpiName:IO_ONES |vpiFullName:work@soc_tb.IO_ONES |vpiActual: - \_logic_net: (work@soc_tb.IO_ONES), line:16:30, endln:16:37 + \_enum_const: (IO_ONES), line:11:7, endln:11:14 |vpiActual: \_ref_obj: (peripheral_io_bus[IO_ONES].write_en), line:16:39, endln:16:47 |vpiParent: @@ -853,7 +846,7 @@ design: (work@soc_tb) |vpiName:IO_ONES |vpiFullName:work@soc_tb.peripheral_io_bus[IO_ONES].write_en.IO_ONES |vpiActual: - \_logic_net: (work@soc_tb.IO_ONES), line:16:30, endln:16:37 + \_enum_const: (IO_ONES), line:11:7, endln:11:14 |vpiActual: \_ref_obj: (peripheral_io_bus[IO_ONES].write_en), line:16:39, endln:16:47 |vpiParent: diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 6433f14643..0011cd25c2 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -74,11 +74,11 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; [ 50%] Generating 1_lsu_stbuf.sv [ 56%] Generating 2_ahb_to_axi4.sv [ 62%] Generating 3_rvjtag_tap.sv -[ 68%] Generating 5_lsu_bus_buffer.sv -[ 75%] Generating 4_dec_tlu_ctl.sv +[ 68%] Generating 4_dec_tlu_ctl.sv +[ 75%] Generating 5_lsu_bus_buffer.sv [ 81%] Generating 6_dbg.sv [ 87%] Generating 7_axi4_to_ahb.sv -[ 93%] Generating 8_ifu_aln_ctl.sv +[100%] Generating 8_ifu_aln_ctl.sv [100%] Generating 9_tb_top.sv [100%] Built target Parse Surelog parsing status: 0 diff --git a/third_party/tests/NyuziProcessor/NyuziProcessor.log b/third_party/tests/NyuziProcessor/NyuziProcessor.log index 10d34afa22..fc8b50bddb 100644 --- a/third_party/tests/NyuziProcessor/NyuziProcessor.log +++ b/third_party/tests/NyuziProcessor/NyuziProcessor.log @@ -925,7 +925,7 @@ interface_array 4 interface_inst 48 interface_typespec 104 io_decl 831 -logic_net 3752 +logic_net 3747 logic_typespec 20996 logic_var 2684 modport 77 @@ -1005,7 +1005,7 @@ interface_array 4 interface_inst 48 interface_typespec 104 io_decl 845 -logic_net 3752 +logic_net 3747 logic_typespec 20996 logic_var 6026 modport 77 diff --git a/third_party/tests/Scr1/Scr1.log b/third_party/tests/Scr1/Scr1.log index 827e1abc6c..8c66054244 100644 --- a/third_party/tests/Scr1/Scr1.log +++ b/third_party/tests/Scr1/Scr1.log @@ -259,7 +259,7 @@ int_var 40 integer_typespec 59 integer_var 3 io_decl 27 -logic_net 2757 +logic_net 2690 logic_typespec 4195 logic_var 828 method_func_call 5 diff --git a/third_party/tests/Scr1SvTests/Scr1SvTests.log b/third_party/tests/Scr1SvTests/Scr1SvTests.log index 40dd7fcf08..d1feb424dc 100644 --- a/third_party/tests/Scr1SvTests/Scr1SvTests.log +++ b/third_party/tests/Scr1SvTests/Scr1SvTests.log @@ -191,7 +191,7 @@ int_var 32 integer_typespec 74 integer_var 3 io_decl 27 -logic_net 3006 +logic_net 2961 logic_typespec 4682 logic_var 1058 method_func_call 4 diff --git a/third_party/tests/Zachjs/Zachjs.log b/third_party/tests/Zachjs/Zachjs.log index 2d10448c37..29abea454a 100644 --- a/third_party/tests/Zachjs/Zachjs.log +++ b/third_party/tests/Zachjs/Zachjs.log @@ -903,21 +903,9 @@ Processing: -cd relong +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve [WARNING] : 0 [ NOTE] : 0 Processing: -cd relong +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ -parse -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns fsm.sv -l fsm.sv.log -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:13:29: Illegal implicit net "S_A". -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:21:13: Illegal implicit net "S_A". -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:21:34: Illegal implicit net "S_B". -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:21:40: Illegal implicit net "S_C". -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:22:13: Illegal implicit net "S_B". -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:22:34: Illegal implicit net "S_A". -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:22:40: Illegal implicit net "S_B". -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:23:13: Illegal implicit net "S_C". -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:23:30: Illegal implicit net "S_A". -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:30:13: Illegal implicit net "S_A". -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:31:13: Illegal implicit net "S_B". -[ERR:EL0535] ${SURELOG_DIR}/third_party/tests/Zachjs/relong/fsm.sv:32:13: Illegal implicit net "S_C". [ FATAL] : 0 [ SYNTAX] : 0 -[ ERROR] : 12 +[ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 Processing: -cd relong +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ -parse -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns functions.sv -l functions.sv.log @@ -1016,6 +1004,6 @@ Processing: -cd relong +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve Processed 122 tests. [ FATAL] : 0 [ SYNTAX] : 39 -[ ERROR] : 28 +[ ERROR] : 16 [WARNING] : 128 [ NOTE] : 0