diff --git a/src/DesignCompile/CompileHelper.cpp b/src/DesignCompile/CompileHelper.cpp index c8ab96f107..82ee974631 100644 --- a/src/DesignCompile/CompileHelper.cpp +++ b/src/DesignCompile/CompileHelper.cpp @@ -5101,6 +5101,33 @@ UHDM::expr* CompileHelper::expandPatternAssignment(const typespec* tps, for (uint64_t i = 0; i < size; i++) { values[i] = defaultval; } + // Apply any other indexed value + for (any* op : *operands) { + if (op->UhdmType() == uhdmtagged_pattern) { + taggedPattern = true; + tagged_pattern* tp = (tagged_pattern*)op; + if (const UHDM::ref_typespec* rt = tp->Typespec()) { + if (const typespec* tpsi = rt->Actual_typespec()) { + if (tpsi->UhdmType() == uhdminteger_typespec) { + integer_typespec* itps = (integer_typespec*)tpsi; + std::string_view v = itps->VpiValue(); + v.remove_prefix(std::string_view("INT:").length()); + int64_t index; + if (NumUtils::parseInt64(v, &index)) { + any* pattern = tp->Pattern(); + if (pattern->UhdmType() == uhdmconstant) { + constant* c = (constant*)pattern; + UHDM::ExprEval eval; + int32_t val = eval.get_value(invalidValue, c); + if (index >= 0 && index < ((int64_t)size)) + values[size - index - 1] = val; + } + } + } + } + } + } + } } } else { int32_t valIndex = 0; diff --git a/tests/PatternAssignInteger/PatternAssignInteger.log b/tests/PatternAssignInteger/PatternAssignInteger.log new file mode 100644 index 0000000000..22ab6328b7 --- /dev/null +++ b/tests/PatternAssignInteger/PatternAssignInteger.log @@ -0,0 +1,396 @@ +[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/PatternAssignInteger/slpp_all/surelog.log". +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<76> s<75> l<1:1> el<1:0> +n u<2> t p<23> s<3> l<1:1> el<1:7> +n u<3> t p<23> s<22> l<1:8> el<1:11> +n<> u<4> t p<19> s<18> l<1:12> el<1:18> +n<> u<5> t p<16> s<15> l<1:19> el<1:24> +n<7> u<6> t p<7> l<1:25> el<1:26> +n<> u<7> t p<8> c<6> l<1:25> el<1:26> +n<> u<8> t p<9> c<7> l<1:25> el<1:26> +n<> u<9> t p<14> c<8> s<13> l<1:25> el<1:26> +n<0> u<10> t p<11> l<1:27> el<1:28> +n<> u<11> t p<12> c<10> l<1:27> el<1:28> +n<> u<12> t p<13> c<11> l<1:27> el<1:28> +n<> u<13> t p<14> c<12> l<1:27> el<1:28> +n<> u<14> t p<15> c<9> l<1:25> el<1:28> +n<> u<15> t p<16> c<14> l<1:24> el<1:29> +n<> u<16> t p<17> c<5> l<1:19> el<1:29> +n<> u<17> t p<18> c<16> l<1:19> el<1:29> +n<> u<18> t p<19> c<17> l<1:19> el<1:29> +n<> u<19> t p<21> c<4> s<20> l<1:12> el<1:29> +n u<20> t p<21> l<1:30> el<1:31> +n<> u<21> t p<22> c<19> l<1:12> el<1:31> +n<> u<22> t p<23> c<21> l<1:11> el<1:32> +n<> u<23> t p<73> c<2> s<71> l<1:1> el<1:33> +n u<24> t p<25> l<2:11> el<2:12> +n<> u<25> t p<28> c<24> s<27> l<2:11> el<2:12> +n<> u<26> t p<27> l<2:13> el<2:13> +n<> u<27> t p<28> c<26> l<2:13> el<2:13> +n<> u<28> t p<66> c<25> s<65> l<2:11> el<2:12> +n<0> u<29> t p<30> l<2:17> el<2:18> +n<> u<30> t p<31> c<29> l<2:17> el<2:18> +n<> u<31> t p<32> c<30> l<2:17> el<2:18> +n<> u<32> t p<33> c<31> l<2:17> el<2:18> +n<> u<33> t p<62> c<32> s<37> l<2:17> el<2:18> +n<1> u<34> t p<35> l<2:19> el<2:20> +n<> u<35> t p<36> c<34> l<2:19> el<2:20> +n<> u<36> t p<37> c<35> l<2:19> el<2:20> +n<> u<37> t p<62> c<36> s<42> l<2:19> el<2:20> +n<3> u<38> t p<39> l<2:22> el<2:23> +n<> u<39> t p<40> c<38> l<2:22> el<2:23> +n<> u<40> t p<41> c<39> l<2:22> el<2:23> +n<> u<41> t p<42> c<40> l<2:22> el<2:23> +n<> u<42> t p<62> c<41> s<46> l<2:22> el<2:23> +n<1> u<43> t p<44> l<2:24> el<2:25> +n<> u<44> t p<45> c<43> l<2:24> el<2:25> +n<> u<45> t p<46> c<44> l<2:24> el<2:25> +n<> u<46> t p<62> c<45> s<51> l<2:24> el<2:25> +n<7> u<47> t p<48> l<2:27> el<2:28> +n<> u<48> t p<49> c<47> l<2:27> el<2:28> +n<> u<49> t p<50> c<48> l<2:27> el<2:28> +n<> u<50> t p<51> c<49> l<2:27> el<2:28> +n<> u<51> t p<62> c<50> s<55> l<2:27> el<2:28> +n<1> u<52> t p<53> l<2:29> el<2:30> +n<> u<53> t p<54> c<52> l<2:29> el<2:30> +n<> u<54> t p<55> c<53> l<2:29> el<2:30> +n<> u<55> t p<62> c<54> s<57> l<2:29> el<2:30> +n<> u<56> t p<57> l<2:32> el<2:39> +n<> u<57> t p<62> c<56> s<61> l<2:32> el<2:39> +n<0> u<58> t p<59> l<2:40> el<2:41> +n<> u<59> t p<60> c<58> l<2:40> el<2:41> +n<> u<60> t p<61> c<59> l<2:40> el<2:41> +n<> u<61> t p<62> c<60> l<2:40> el<2:41> +n<> u<62> t p<63> c<33> l<2:15> el<2:42> +n<> u<63> t p<64> c<62> l<2:15> el<2:42> +n<> u<64> t p<65> c<63> l<2:15> el<2:42> +n<> u<65> t p<66> c<64> l<2:15> el<2:42> +n<> u<66> t p<67> c<28> l<2:11> el<2:42> +n<> u<67> t p<68> c<66> l<2:11> el<2:42> +n<> u<68> t p<69> c<67> l<2:4> el<2:43> +n<> u<69> t p<70> c<68> l<2:4> el<2:43> +n<> u<70> t p<71> c<69> l<2:4> el<2:43> +n<> u<71> t p<73> c<70> s<72> l<2:4> el<2:43> +n<> u<72> t p<73> l<3:1> el<3:10> +n<> u<73> t p<74> c<23> l<1:1> el<3:10> +n<> u<74> t p<75> c<73> l<1:1> el<3:10> +n<> u<75> t p<76> c<74> l<1:1> el<3:10> +n<> u<76> t c<1> l<1:1> el<3:10> +AST_DEBUG_END +[WRN:PA0205] ${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv:1:1: No timescale set for "top". +[INF:CP0300] Compilation... +[INF:CP0303] ${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv:1:1: Compile module "work@top". +[INF:EL0526] Design Elaboration... +[NTE:EL0503] ${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv:1:1: Top level module "work@top". +[NTE:EL0508] Nb Top level modules: 1. +[NTE:EL0509] Max instance depth: 1. +[NTE:EL0510] Nb instances: 1. +[NTE:EL0511] Nb leaf instances: 1. +[INF:UH0706] Creating UHDM Model... +=== UHDM Object Stats Begin (Non-Elaborated Model) === +constant 17 +cont_assign 2 +design 1 +integer_typespec 6 +logic_net 2 +logic_typespec 3 +module_inst 4 +operation 2 +port 2 +range 4 +ref_obj 4 +ref_typespec 11 +string_typespec 2 +tagged_pattern 8 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... +=== UHDM Object Stats Begin (Elaborated Model) === +constant 17 +cont_assign 3 +design 1 +integer_typespec 6 +logic_net 2 +logic_typespec 3 +module_inst 4 +operation 2 +port 3 +range 4 +ref_obj 6 +ref_typespec 12 +string_typespec 2 +tagged_pattern 8 +=== UHDM Object Stats End === +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/PatternAssignInteger/slpp_all/surelog.uhdm ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/PatternAssignInteger/slpp_all/checker/surelog.chk.html ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/PatternAssignInteger/slpp_all/surelog.uhdm ... +[INF:UH0711] Decompiling UHDM... +====== UHDM ======= +design: (work@top) +|vpiElaborated:1 +|vpiName:work@top +|uhdmallModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv, line:1:1, endln:3:10 + |vpiParent: + \_design: (work@top) + |vpiFullName:work@top + |vpiDefName:work@top + |vpiNet: + \_logic_net: (work@top.o), line:1:30, endln:1:31 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv, line:1:1, endln:3:10 + |vpiName:o + |vpiFullName:work@top.o + |vpiNetType:36 + |vpiPort: + \_port: (o), line:1:30, endln:1:31 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv, line:1:1, endln:3:10 + |vpiName:o + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@top.o.o), line:1:30, endln:1:31 + |vpiParent: + \_port: (o), line:1:30, endln:1:31 + |vpiName:o + |vpiFullName:work@top.o.o + |vpiActual: + \_logic_net: (work@top.o), line:1:30, endln:1:31 + |vpiTypedef: + \_ref_typespec: (work@top.o) + |vpiParent: + \_port: (o), line:1:30, endln:1:31 + |vpiFullName:work@top.o + |vpiActual: + \_logic_typespec: , line:1:19, endln:1:29 + |vpiContAssign: + \_cont_assign: , line:2:11, endln:2:42 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv, line:1:1, endln:3:10 + |vpiRhs: + \_operation: , line:2:15, endln:2:42 + |vpiParent: + \_cont_assign: , line:2:11, endln:2:42 + |vpiOpType:75 + |vpiOperand: + \_tagged_pattern: , line:2:19, endln:2:20 + |vpiParent: + \_operation: , line:2:15, endln:2:42 + |vpiPattern: + \_constant: , line:2:19, endln:2:20 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiTypespec: + \_ref_typespec: (work@top) + |vpiParent: + \_tagged_pattern: , line:2:19, endln:2:20 + |vpiFullName:work@top + |vpiActual: + \_integer_typespec: , line:2:17, endln:2:18 + |vpiOperand: + \_tagged_pattern: , line:2:24, endln:2:25 + |vpiParent: + \_operation: , line:2:15, endln:2:42 + |vpiPattern: + \_constant: , line:2:24, endln:2:25 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiTypespec: + \_ref_typespec: (work@top) + |vpiParent: + \_tagged_pattern: , line:2:24, endln:2:25 + |vpiFullName:work@top + |vpiActual: + \_integer_typespec: , line:2:22, endln:2:23 + |vpiOperand: + \_tagged_pattern: , line:2:29, endln:2:30 + |vpiParent: + \_operation: , line:2:15, endln:2:42 + |vpiPattern: + \_constant: , line:2:29, endln:2:30 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiTypespec: + \_ref_typespec: (work@top) + |vpiParent: + \_tagged_pattern: , line:2:29, endln:2:30 + |vpiFullName:work@top + |vpiActual: + \_integer_typespec: , line:2:27, endln:2:28 + |vpiOperand: + \_tagged_pattern: , line:2:40, endln:2:41 + |vpiParent: + \_operation: , line:2:15, endln:2:42 + |vpiPattern: + \_constant: , line:2:40, endln:2:41 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiTypespec: + \_ref_typespec: (work@top) + |vpiParent: + \_tagged_pattern: , line:2:40, endln:2:41 + |vpiFullName:work@top + |vpiActual: + \_string_typespec: (default), line:2:32, endln:2:39 + |vpiLhs: + \_ref_obj: (work@top.o), line:2:11, endln:2:12 + |vpiParent: + \_cont_assign: , line:2:11, endln:2:42 + |vpiName:o + |vpiFullName:work@top.o + |vpiActual: + \_logic_net: (work@top.o), line:1:30, endln:1:31 +|uhdmtopModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv, line:1:1, endln:3:10 + |vpiName:work@top + |vpiDefName:work@top + |vpiTop:1 + |vpiNet: + \_logic_net: (work@top.o), line:1:30, endln:1:31 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv, line:1:1, endln:3:10 + |vpiTypespec: + \_ref_typespec: (work@top.o) + |vpiParent: + \_logic_net: (work@top.o), line:1:30, endln:1:31 + |vpiFullName:work@top.o + |vpiActual: + \_logic_typespec: , line:1:19, endln:1:29 + |vpiName:o + |vpiFullName:work@top.o + |vpiNetType:36 + |vpiTopModule:1 + |vpiPort: + \_port: (o), line:1:30, endln:1:31 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv, line:1:1, endln:3:10 + |vpiName:o + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@top.o), line:1:30, endln:1:31 + |vpiParent: + \_port: (o), line:1:30, endln:1:31 + |vpiName:o + |vpiFullName:work@top.o + |vpiActual: + \_logic_net: (work@top.o), line:1:30, endln:1:31 + |vpiTypedef: + \_ref_typespec: (work@top.o) + |vpiParent: + \_port: (o), line:1:30, endln:1:31 + |vpiFullName:work@top.o + |vpiActual: + \_logic_typespec: , line:1:19, endln:1:29 + |vpiInstance: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv, line:1:1, endln:3:10 + |vpiContAssign: + \_cont_assign: , line:2:11, endln:2:42 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv, line:1:1, endln:3:10 + |vpiRhs: + \_constant: , line:2:15, endln:2:42 + |vpiDecompile:8'd137 + |vpiSize:8 + |UINT:137 + |vpiLhs: + \_ref_obj: (work@top.o), line:2:11, endln:2:12 + |vpiParent: + \_cont_assign: , line:2:11, endln:2:42 + |vpiName:o + |vpiFullName:work@top.o + |vpiActual: + \_logic_net: (work@top.o), line:1:30, endln:1:31 +\_weaklyReferenced: +\_integer_typespec: , line:2:17, endln:2:18 + |INT:0 +\_integer_typespec: , line:2:22, endln:2:23 + |INT:3 +\_integer_typespec: , line:2:27, endln:2:28 + |INT:7 +\_string_typespec: (default), line:2:32, endln:2:39 + |vpiParent: + \_tagged_pattern: , line:2:40, endln:2:41 + |vpiName:default +\_logic_typespec: , line:1:19, endln:1:29 + |vpiRange: + \_range: , line:1:24, endln:1:29 + |vpiParent: + \_logic_typespec: , line:1:19, endln:1:29 + |vpiLeftRange: + \_constant: , line:1:25, endln:1:26 + |vpiParent: + \_range: , line:1:24, endln:1:29 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:1:27, endln:1:28 + |vpiParent: + \_range: , line:1:24, endln:1:29 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:1:19, endln:1:29 + |vpiRange: + \_range: , line:1:24, endln:1:29 + |vpiParent: + \_logic_typespec: , line:1:19, endln:1:29 + |vpiLeftRange: + \_constant: , line:1:25, endln:1:26 + |vpiParent: + \_range: , line:1:24, endln:1:29 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:1:27, endln:1:28 + |vpiParent: + \_range: , line:1:24, endln:1:29 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:1:19, endln:1:29 + |vpiRange: + \_range: , line:1:24, endln:1:29 + |vpiParent: + \_logic_typespec: , line:1:19, endln:1:29 + |vpiLeftRange: + \_constant: , line:1:25, endln:1:26 + |vpiParent: + \_range: , line:1:24, endln:1:29 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:1:27, endln:1:28 + |vpiParent: + \_range: , line:1:24, endln:1:29 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +=================== +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 1 +[ NOTE] : 5 + +============================== Begin RoundTrip Results ============================== +[roundtrip]: ${SURELOG_DIR}/tests/PatternAssignInteger/dut.sv | ${SURELOG_DIR}/build/regression/PatternAssignInteger/roundtrip/dut_000.sv | 1 | 3 | +============================== End RoundTrip Results ============================== diff --git a/tests/PatternAssignInteger/PatternAssignInteger.sl b/tests/PatternAssignInteger/PatternAssignInteger.sl new file mode 100644 index 0000000000..b461620aca --- /dev/null +++ b/tests/PatternAssignInteger/PatternAssignInteger.sl @@ -0,0 +1 @@ +-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin diff --git a/tests/PatternAssignInteger/dut.sv b/tests/PatternAssignInteger/dut.sv new file mode 100644 index 0000000000..5f65b4542b --- /dev/null +++ b/tests/PatternAssignInteger/dut.sv @@ -0,0 +1,3 @@ +module top(output logic[7:0] o); + assign o = '{0:1, 3:1, 7:1, default:0}; +endmodule \ No newline at end of file