diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp index c0f6b6312b..301e28f0ef 100644 --- a/src/DesignCompile/UhdmWriter.cpp +++ b/src/DesignCompile/UhdmWriter.cpp @@ -4527,6 +4527,125 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, } } + +class AlwaysWithForLoop : public VpiListener { + public: + explicit AlwaysWithForLoop() {} + ~AlwaysWithForLoop() override = default; + void leaveFor_stmt(const for_stmt* object, vpiHandle handle) { + containtsForStmt = true; + } + bool containtsForStmt = false; +}; + +bool alwaysContainsForLoop(Serializer& serializer, any* root) { + AlwaysWithForLoop* listener = new AlwaysWithForLoop(); + vpiHandle handle = serializer.MakeUhdmHandle(root->UhdmType(), root); + listener->listenAny(handle); + vpi_release_handle(handle); + bool result = listener->containtsForStmt; + delete listener; + return result; +} + +// synlig has a major problem processing always blocks. +// They are processed mainly in the allModules section which is incorrect in some case. +// They should be processed from the topModules section. +// Here we try to fix temporarily this by filtering out the always blocks containing for-loops +// from the allModules, and those without from the topModules +void filterAlwaysBlocks(Serializer& s, design* d) { + if (d->AllModules()) { + for (auto module : *d->AllModules()) { + if (module->Process()) { + bool more = true; + while (more) { + more = false; + for (std::vector::iterator itr = + module->Process()->begin(); + itr != module->Process()->end(); itr++) { + if ((*itr)->UhdmType() == uhdmalways) { + if (alwaysContainsForLoop(s, (*itr))) { + more = true; + module->Process()->erase(itr); + break; + } + } + } + } + } + } + } + std::queue instances; + if (d->TopModules()) { + for (auto mod : *d->TopModules()) { + instances.push(mod) ; + } + } + while (!instances.empty()) { + scope* current = instances.front(); + instances.pop(); + if (current->UhdmType() == uhdmmodule_inst) { + module_inst* mod = (module_inst*) current; + if (mod->Process()) { + bool more = true; + while (more) { + more = false; + for (std::vector::iterator itr = + mod->Process()->begin(); + itr != mod->Process()->end(); itr++) { + if ((*itr)->UhdmType() == uhdmalways) { + if (!alwaysContainsForLoop(s, (*itr))) { + more = true; + mod->Process()->erase(itr); + break; + } + } + } + } + } + if (mod->Modules()) { + for (auto m : *mod->Modules()) { + instances.push(m); + } + } + if (mod->Gen_scope_arrays()) { + for (auto m : *mod->Gen_scope_arrays()) { + instances.push(m->Gen_scopes()->at(0)); + } + } + } else if (current->UhdmType() == uhdmgen_scope) { + gen_scope* sc = (gen_scope*) current; + if (sc->Process()) { + bool more = true; + while (more) { + more = false; + for (std::vector::iterator itr = + sc->Process()->begin(); + itr != sc->Process()->end(); itr++) { + if ((*itr)->UhdmType() == uhdmalways) { + if (!alwaysContainsForLoop(s, (*itr))) { + more = true; + sc->Process()->erase(itr); + break; + } + } + } + } + } + if (sc->Modules()) { + for (auto m : *sc->Modules()) { + instances.push(m); + } + } + if (sc->Gen_scope_arrays()) { + for (auto m : *sc->Gen_scope_arrays()) { + instances.push(m->Gen_scopes()->at(0)); + } + } + } + } +} + vpiHandle UhdmWriter::write(PathId uhdmFileId) { FileSystem* const fileSystem = FileSystem::getInstance(); ModPortMap modPortMap; @@ -4966,6 +5085,7 @@ vpiHandle UhdmWriter::write(PathId uhdmFileId) { annotate->listenDesigns(designs); annotate->filterNonSynthesizable(); delete annotate; + filterAlwaysBlocks(s, d); } } diff --git a/tests/3SigsSensList/3SigsSensList.log b/tests/3SigsSensList/3SigsSensList.log index 1198bbc5f7..b0339da9dd 100644 --- a/tests/3SigsSensList/3SigsSensList.log +++ b/tests/3SigsSensList/3SigsSensList.log @@ -517,94 +517,6 @@ design: (work@dut) \_logic_typespec: , line:5:7, endln:5:11 |vpiInstance: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/3SigsSensList/dut.sv, line:1:1, endln:36:10 - |vpiProcess: - \_always: , line:24:1, endln:34:4 - |vpiParent: - \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/3SigsSensList/dut.sv, line:1:1, endln:36:10 - |vpiStmt: - \_event_control: , line:24:8, endln:24:55 - |vpiParent: - \_always: , line:24:1, endln:34:4 - |vpiCondition: - \_operation: , line:24:11, endln:24:54 - |vpiParent: - \_event_control: , line:24:8, endln:24:55 - |vpiOpType:35 - |vpiOperand: - \_operation: , line:24:11, endln:24:22 - |vpiParent: - \_operation: , line:24:11, endln:24:37 - |vpiOpType:39 - |vpiOperand: - \_ref_obj: (work@dut.clk), line:24:19, endln:24:22 - |vpiParent: - \_operation: , line:24:11, endln:24:22 - |vpiName:clk - |vpiFullName:work@dut.clk - |vpiActual: - \_logic_net: (work@dut.clk), line:3:18, endln:3:21 - |vpiOperand: - \_operation: , line:24:41, endln:24:54 - |vpiParent: - \_operation: , line:24:11, endln:24:54 - |vpiOpType:39 - |vpiOperand: - \_ref_obj: (synlig_tmp_rst_or_start) - |vpiName:synlig_tmp_rst_or_start - |vpiActual: - \_logic_net: (synlig_tmp_rst_or_start) - |vpiStmt: - \_begin: (work@dut), line:25:1, endln:34:4 - |vpiParent: - \_event_control: , line:24:8, endln:24:55 - |vpiFullName:work@dut - |vpiStmt: - \_if_else: , line:26:2, endln:33:5 - |vpiParent: - \_begin: (work@dut), line:25:1, endln:34:4 - |vpiCondition: - \_ref_obj: (synlig_tmp_rst_or_start) - |vpiStmt: - \_begin: (work@dut), line:27:2, endln:29:5 - |vpiParent: - \_if_else: , line:26:2, endln:33:5 - |vpiFullName:work@dut - |vpiStmt: - \_assignment: , line:28:4, endln:28:19 - |vpiParent: - \_begin: (work@dut), line:27:2, endln:29:5 - |vpiOpType:82 - |vpiRhs: - \_constant: , line:28:18, endln:28:19 - |vpiLhs: - \_ref_obj: (work@dut.outputLine), line:28:4, endln:28:14 - |vpiParent: - \_assignment: , line:28:4, endln:28:19 - |vpiName:outputLine - |vpiFullName:work@dut.outputLine - |vpiActual: - \_logic_net: (work@dut.outputLine), line:28:4, endln:28:14 - |vpiElseStmt: - \_begin: (work@dut), line:31:2, endln:33:5 - |vpiParent: - \_if_else: , line:26:2, endln:33:5 - |vpiFullName:work@dut - |vpiStmt: - \_assignment: , line:32:3, endln:32:24 - |vpiParent: - \_begin: (work@dut), line:31:2, endln:33:5 - |vpiOpType:82 - |vpiRhs: - \_constant: , line:32:23, endln:32:24 - |vpiLhs: - \_ref_obj: (work@dut.yScaleAmountNext), line:32:3, endln:32:19 - |vpiParent: - \_assignment: , line:32:3, endln:32:24 - |vpiName:yScaleAmountNext - |vpiFullName:work@dut.yScaleAmountNext - |vpiActual: - \_logic_net: (work@dut.yScaleAmountNext), line:32:3, endln:32:19 - |vpiAlwaysType:1 |vpiContAssign: \_cont_assign: |vpiRhs: @@ -657,18 +569,107 @@ design: (work@dut) \_logic_typespec: , line:3:7, endln:3:11 \_logic_typespec: , line:4:7, endln:4:11 \_logic_typespec: , line:5:7, endln:5:11 +\_operation: , line:24:26, endln:24:37 + |vpiParent: + \_operation: , line:24:11, endln:24:37 + |vpiOpType:39 + |vpiOperand: + \_ref_obj: (work@dut.rst), line:24:34, endln:24:37 \_operation: , line:24:11, endln:24:37 |vpiParent: \_operation: , line:24:11, endln:24:54 |vpiOpType:35 |vpiOperand: \_operation: , line:24:11, endln:24:22 -\_operation: , line:24:26, endln:24:37 + |vpiParent: + \_operation: , line:24:11, endln:24:37 + |vpiOpType:39 + |vpiOperand: + \_ref_obj: (work@dut.clk), line:24:19, endln:24:22 + |vpiParent: + \_operation: , line:24:11, endln:24:22 + |vpiName:clk + |vpiFullName:work@dut.clk + |vpiActual: + \_logic_net: (work@dut.clk), line:3:18, endln:3:21 +\_operation: , line:24:11, endln:24:54 |vpiParent: - \_operation: , line:24:11, endln:24:37 - |vpiOpType:39 + \_event_control: , line:24:8, endln:24:55 + |vpiOpType:35 |vpiOperand: - \_ref_obj: (work@dut.rst), line:24:34, endln:24:37 + \_operation: , line:24:11, endln:24:22 + |vpiOperand: + \_operation: , line:24:41, endln:24:54 + |vpiParent: + \_operation: , line:24:11, endln:24:54 + |vpiOpType:39 + |vpiOperand: + \_ref_obj: (synlig_tmp_rst_or_start) + |vpiName:synlig_tmp_rst_or_start + |vpiActual: + \_logic_net: (synlig_tmp_rst_or_start) +\_event_control: , line:24:8, endln:24:55 + |vpiParent: + \_always: , line:24:1, endln:34:4 + |vpiCondition: + \_operation: , line:24:11, endln:24:54 + |vpiStmt: + \_begin: (work@dut), line:25:1, endln:34:4 + |vpiParent: + \_event_control: , line:24:8, endln:24:55 + |vpiFullName:work@dut + |vpiStmt: + \_if_else: , line:26:2, endln:33:5 + |vpiParent: + \_begin: (work@dut), line:25:1, endln:34:4 + |vpiCondition: + \_ref_obj: (synlig_tmp_rst_or_start) + |vpiStmt: + \_begin: (work@dut), line:27:2, endln:29:5 + |vpiParent: + \_if_else: , line:26:2, endln:33:5 + |vpiFullName:work@dut + |vpiStmt: + \_assignment: , line:28:4, endln:28:19 + |vpiParent: + \_begin: (work@dut), line:27:2, endln:29:5 + |vpiOpType:82 + |vpiRhs: + \_constant: , line:28:18, endln:28:19 + |vpiLhs: + \_ref_obj: (work@dut.outputLine), line:28:4, endln:28:14 + |vpiParent: + \_assignment: , line:28:4, endln:28:19 + |vpiName:outputLine + |vpiFullName:work@dut.outputLine + |vpiActual: + \_logic_net: (work@dut.outputLine), line:28:4, endln:28:14 + |vpiElseStmt: + \_begin: (work@dut), line:31:2, endln:33:5 + |vpiParent: + \_if_else: , line:26:2, endln:33:5 + |vpiFullName:work@dut + |vpiStmt: + \_assignment: , line:32:3, endln:32:24 + |vpiParent: + \_begin: (work@dut), line:31:2, endln:33:5 + |vpiOpType:82 + |vpiRhs: + \_constant: , line:32:23, endln:32:24 + |vpiLhs: + \_ref_obj: (work@dut.yScaleAmountNext), line:32:3, endln:32:19 + |vpiParent: + \_assignment: , line:32:3, endln:32:24 + |vpiName:yScaleAmountNext + |vpiFullName:work@dut.yScaleAmountNext + |vpiActual: + \_logic_net: (work@dut.yScaleAmountNext), line:32:3, endln:32:19 +\_always: , line:24:1, endln:34:4 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/3SigsSensList/dut.sv, line:1:1, endln:36:10 + |vpiStmt: + \_event_control: , line:24:8, endln:24:55 + |vpiAlwaysType:1 =================== [ FATAL] : 0 [ SYNTAX] : 0 @@ -676,11 +677,6 @@ design: (work@dut) [WARNING] : 0 [ NOTE] : 5 -============================== Begin Linting Results ============================== -[LINT]: ${SURELOG_DIR}/tests/3SigsSensList/dut.sv:28:4: Illegal wire LHS, outputLine -[LINT]: ${SURELOG_DIR}/tests/3SigsSensList/dut.sv:32:3: Illegal wire LHS, yScaleAmountNext -============================== End Linting Results ============================== - ============================== Begin RoundTrip Results ============================== [roundtrip]: ${SURELOG_DIR}/tests/3SigsSensList/dut.sv | ${SURELOG_DIR}/build/regression/3SigsSensList/roundtrip/dut_000.sv | 20 | 36 | ============================== End RoundTrip Results ============================== diff --git a/tests/UnboundForLoop/UnboundForLoop.log b/tests/UnboundForLoop/UnboundForLoop.log index 55efe0e672..9ecab8ee25 100644 --- a/tests/UnboundForLoop/UnboundForLoop.log +++ b/tests/UnboundForLoop/UnboundForLoop.log @@ -271,119 +271,6 @@ design: (work@signed_shifter) |vpiFullName:work@signed_shifter.Q |vpiActual: \_logic_typespec: , line:3:10, endln:3:26 - |vpiProcess: - \_always: , line:5:3, endln:7:6 - |vpiParent: - \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10 - |vpiStmt: - \_event_control: , line:5:10, endln:5:13 - |vpiParent: - \_always: , line:5:3, endln:7:6 - |vpiStmt: - \_begin: (work@signed_shifter), line:5:14, endln:7:6 - |vpiParent: - \_event_control: , line:5:10, endln:5:13 - |vpiFullName:work@signed_shifter - |vpiStmt: - \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8 - |vpiParent: - \_begin: (work@signed_shifter), line:5:14, endln:7:6 - |vpiFullName:work@signed_shifter - |vpiForInitStmt: - \_assignment: , line:6:9, endln:6:12 - |vpiParent: - \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8 - |vpiRhs: - \_constant: , line:6:11, endln:6:12 - |vpiParent: - \_assignment: , line:6:9, endln:6:12 - |vpiDecompile:0 - |vpiSize:64 - |UINT:0 - |vpiConstType:9 - |vpiLhs: - \_ref_var: (work@signed_shifter.j), line:6:9, endln:6:10 - |vpiParent: - \_assignment: , line:6:9, endln:6:12 - |vpiName:j - |vpiFullName:work@signed_shifter.j - |vpiForIncStmt: - \_assignment: , line:6:17, endln:6:22 - |vpiParent: - \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8 - |vpiOpType:82 - |vpiBlocking:1 - |vpiRhs: - \_operation: , line:6:19, endln:6:22 - |vpiParent: - \_assignment: , line:6:17, endln:6:22 - |vpiOpType:24 - |vpiOperand: - \_ref_obj: (work@signed_shifter.j), line:6:19, endln:6:20 - |vpiParent: - \_operation: , line:6:19, endln:6:22 - |vpiName:j - |vpiFullName:work@signed_shifter.j - |vpiActual: - \_logic_net: (work@signed_shifter.j), line:4:11, endln:4:12 - |vpiOperand: - \_constant: , line:6:21, endln:6:22 - |vpiParent: - \_operation: , line:6:19, endln:6:22 - |vpiDecompile:1 - |vpiSize:64 - |UINT:1 - |vpiConstType:9 - |vpiLhs: - \_ref_obj: (work@signed_shifter.j), line:6:17, endln:6:18 - |vpiParent: - \_assignment: , line:6:17, endln:6:22 - |vpiName:j - |vpiFullName:work@signed_shifter.j - |vpiActual: - \_logic_net: (work@signed_shifter.j), line:4:11, endln:4:12 - |vpiCondition: - \_operation: , line:6:13, endln:6:16 - |vpiParent: - \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8 - |vpiOpType:20 - |vpiOperand: - \_ref_obj: (work@signed_shifter.j), line:6:13, endln:6:14 - |vpiParent: - \_operation: , line:6:13, endln:6:16 - |vpiName:j - |vpiFullName:work@signed_shifter.j - |vpiActual: - \_logic_net: (work@signed_shifter.j), line:4:11, endln:4:12 - |vpiOperand: - \_ref_obj: (work@signed_shifter.i), line:6:15, endln:6:16 - |vpiParent: - \_operation: , line:6:13, endln:6:16 - |vpiName:i - |vpiFullName:work@signed_shifter.i - |vpiActual: - \_logic_net: (work@signed_shifter.i), line:2:20, endln:2:21 - |vpiStmt: - \_assignment: , line:6:24, endln:6:32 - |vpiParent: - \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8 - |vpiOpType:82 - |vpiBlocking:1 - |vpiRhs: - \_constant: , line:6:28, endln:6:32 - |vpiDecompile:1'b1 - |vpiSize:1 - |BIN:1 - |vpiConstType:3 - |vpiLhs: - \_ref_obj: (work@signed_shifter.Q), line:6:24, endln:6:25 - |vpiParent: - \_assignment: , line:6:24, endln:6:32 - |vpiName:Q - |vpiFullName:work@signed_shifter.Q - |vpiActual: - \_logic_net: (work@signed_shifter.Q), line:3:27, endln:3:28 - |vpiAlwaysType:1 |uhdmtopModules: \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10 |vpiName:work@signed_shifter @@ -870,5 +757,5 @@ design: (work@signed_shifter) [ NOTE] : 5 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/UnboundForLoop/dut.sv | ${SURELOG_DIR}/build/regression/UnboundForLoop/roundtrip/dut_000.sv | 4 | 8 | +[roundtrip]: ${SURELOG_DIR}/tests/UnboundForLoop/dut.sv | ${SURELOG_DIR}/build/regression/UnboundForLoop/roundtrip/dut_000.sv | 5 | 8 | ============================== End RoundTrip Results ============================== diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index f32457ebbe..b18feb2511 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -64,12 +64,12 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; -- Configuring done -- Generating done -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -[ 6%] Generating 15_exu.sv +[ 6%] Generating 11_ifu_bp_ctl.sv [ 12%] Generating 10_lsu_bus_intf.sv -[ 18%] Generating 13_ifu_mem_ctl.sv -[ 25%] Generating 14_mem_lib.sv -[ 31%] Generating 11_ifu_bp_ctl.sv -[ 37%] Generating 12_beh_lib.sv +[ 18%] Generating 12_beh_lib.sv +[ 25%] Generating 13_ifu_mem_ctl.sv +[ 31%] Generating 14_mem_lib.sv +[ 37%] Generating 15_exu.sv [ 43%] Generating 16_dec_decode_ctl.sv [ 50%] Generating 1_lsu_stbuf.sv [ 56%] Generating 2_ahb_to_axi4.sv @@ -77,8 +77,8 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; [ 68%] Generating 4_dec_tlu_ctl.sv [ 75%] Generating 5_lsu_bus_buffer.sv [ 81%] Generating 6_dbg.sv -[ 87%] Generating 8_ifu_aln_ctl.sv [ 93%] Generating 7_axi4_to_ahb.sv +[ 93%] Generating 8_ifu_aln_ctl.sv [100%] Generating 9_tb_top.sv [100%] Built target Parse Surelog parsing status: 0