diff --git a/tests/UnboundForLoop/UnboundForLoop.log b/tests/UnboundForLoop/UnboundForLoop.log
index 86ad711f0c..55efe0e672 100644
--- a/tests/UnboundForLoop/UnboundForLoop.log
+++ b/tests/UnboundForLoop/UnboundForLoop.log
@@ -496,6 +496,7 @@ design: (work@signed_shifter)
         \_case_stmt: 
           |vpiParent:
           \_begin: (work@signed_shifter), line:5:14, endln:7:6
+          |vpiCaseType:1
           |vpiCondition:
           \_ref_obj: (work@signed_shifter.i)
             |vpiParent:
diff --git a/third_party/UHDM b/third_party/UHDM
index 66dd589a9a..1e28f737a3 160000
--- a/third_party/UHDM
+++ b/third_party/UHDM
@@ -1 +1 @@
-Subproject commit 66dd589a9a139affc1724b81d08dc990d3a5f398
+Subproject commit 1e28f737a3ab06688eac8961c555956559934545
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
index 324c64fb23..f32457ebbe 100644
--- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
+++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -64,12 +64,12 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
 -- Configuring done
 -- Generating done
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
-[  6%] Generating 10_lsu_bus_intf.sv
-[ 12%] Generating 11_ifu_bp_ctl.sv
-[ 18%] Generating 12_beh_lib.sv
-[ 25%] Generating 13_ifu_mem_ctl.sv
-[ 31%] Generating 14_mem_lib.sv
-[ 37%] Generating 15_exu.sv
+[  6%] Generating 15_exu.sv
+[ 12%] Generating 10_lsu_bus_intf.sv
+[ 18%] Generating 13_ifu_mem_ctl.sv
+[ 25%] Generating 14_mem_lib.sv
+[ 31%] Generating 11_ifu_bp_ctl.sv
+[ 37%] Generating 12_beh_lib.sv
 [ 43%] Generating 16_dec_decode_ctl.sv
 [ 50%] Generating 1_lsu_stbuf.sv
 [ 56%] Generating 2_ahb_to_axi4.sv
@@ -77,8 +77,8 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
 [ 68%] Generating 4_dec_tlu_ctl.sv
 [ 75%] Generating 5_lsu_bus_buffer.sv
 [ 81%] Generating 6_dbg.sv
-[ 87%] Generating 7_axi4_to_ahb.sv
-[ 93%] Generating 8_ifu_aln_ctl.sv
+[ 87%] Generating 8_ifu_aln_ctl.sv
+[ 93%] Generating 7_axi4_to_ahb.sv
 [100%] Generating 9_tb_top.sv
 [100%] Built target Parse
 Surelog parsing status: 0