diff --git a/src/DesignCompile/CompileExpression.cpp b/src/DesignCompile/CompileExpression.cpp index e4b0254a52..d04b498e1c 100644 --- a/src/DesignCompile/CompileExpression.cpp +++ b/src/DesignCompile/CompileExpression.cpp @@ -5093,7 +5093,19 @@ UHDM::any *CompileHelper::compileComplexFuncCall( std::string the_name(fC->SymName(name)); if (!hierPath) { VObjectType dtype = fC->Type(dotedName); - if (Bit_select && (fC->Child(Bit_select) || fC->Sibling(Bit_select))) { + VObjectType selectType = fC->Type(selectName); + if (selectName && + (selectType == VObjectType::paConstant_part_select_range)) { + result = compileSelectExpression(component, fC, dotedName, "", + compileDesign, reduce, pexpr, + instance, muteErrors); + if (result && (result->UhdmType() == UHDM::uhdmvar_select)) { + fC->populateCoreMembers(name, dotedName, result); + ((var_select *)result)->VpiName(sval); + } + return result; + } else if (Bit_select && + (fC->Child(Bit_select) || fC->Sibling(Bit_select))) { result = compileSelectExpression(component, fC, Bit_select, sval, compileDesign, reduce, pexpr, instance, muteErrors); diff --git a/tests/MultiPartSelect/MultiPartSelect.log b/tests/MultiPartSelect/MultiPartSelect.log new file mode 100644 index 0000000000..566f0be52a --- /dev/null +++ b/tests/MultiPartSelect/MultiPartSelect.log @@ -0,0 +1,573 @@ +[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/MultiPartSelect/slpp_all/surelog.log". +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/MultiPartSelect/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<118> s<117> l<1:1> el<1:0> +n<> u<2> t p<3> l<1:9> el<1:15> +n<> u<3> t p<32> c<2> s<4> l<1:9> el<1:15> +n<> u<4> t p<32> s<31> l<1:16> el<1:22> +n<> u<5> t p<26> s<15> l<2:5> el<2:10> +n<1> u<6> t p<7> l<2:12> el<2:13> +n<> u<7> t p<8> c<6> l<2:12> el<2:13> +n<> u<8> t p<9> c<7> l<2:12> el<2:13> +n<> u<9> t p<14> c<8> s<13> l<2:12> el<2:13> +n<0> u<10> t p<11> l<2:14> el<2:15> +n<> u<11> t p<12> c<10> l<2:14> el<2:15> +n<> u<12> t p<13> c<11> l<2:14> el<2:15> +n<> u<13> t p<14> c<12> l<2:14> el<2:15> +n<> u<14> t p<15> c<9> l<2:12> el<2:15> +n<> u<15> t p<26> c<14> s<25> l<2:11> el<2:16> +n<3> u<16> t p<17> l<2:17> el<2:18> +n<> u<17> t p<18> c<16> l<2:17> el<2:18> +n<> u<18> t p<19> c<17> l<2:17> el<2:18> +n<> u<19> t p<24> c<18> s<23> l<2:17> el<2:18> +n<0> u<20> t p<21> l<2:19> el<2:20> +n<> u<21> t p<22> c<20> l<2:19> el<2:20> +n<> u<22> t p<23> c<21> l<2:19> el<2:20> +n<> u<23> t p<24> c<22> l<2:19> el<2:20> +n<> u<24> t p<25> c<19> l<2:17> el<2:20> +n<> u<25> t p<26> c<24> l<2:16> el<2:21> +n<> u<26> t p<27> c<5> l<2:5> el<2:21> +n<> u<27> t p<31> c<26> s<30> l<2:5> el<2:21> +n u<28> t p<29> l<2:22> el<2:23> +n<> u<29> t p<30> c<28> l<2:22> el<2:23> +n<> u<30> t p<31> c<29> l<2:22> el<2:23> +n<> u<31> t p<32> c<27> l<2:5> el<2:24> +n<> u<32> t p<34> c<3> s<33> l<1:9> el<3:2> +n u<33> t p<34> l<3:3> el<3:8> +n<> u<34> t p<35> c<32> l<1:1> el<3:9> +n<> u<35> t p<36> c<34> l<1:1> el<3:9> +n<> u<36> t p<37> c<35> l<1:1> el<3:9> +n<> u<37> t p<38> c<36> l<1:1> el<3:9> +n<> u<38> t p<117> c<37> s<116> l<1:1> el<3:9> +n u<39> t p<43> s<40> l<5:1> el<5:7> +n u<40> t p<43> s<42> l<5:8> el<5:11> +n<> u<41> t p<42> l<5:12> el<5:12> +n<> u<42> t p<43> c<41> l<5:11> el<5:13> +n<> u<43> t p<115> c<39> s<51> l<5:1> el<5:14> +n u<44> t p<45> l<7:5> el<7:10> +n<> u<45> t p<49> c<44> s<48> l<7:5> el<7:10> +n u<46> t p<47> l<7:11> el<7:13> +n<> u<47> t p<48> c<46> l<7:11> el<7:13> +n<> u<48> t p<49> c<47> l<7:11> el<7:13> +n<> u<49> t p<50> c<45> l<7:5> el<7:13> +n<> u<50> t p<51> c<49> l<7:5> el<7:13> +n<> u<51> t p<115> c<50> s<82> l<7:5> el<7:14> +n u<52> t p<53> l<8:12> el<8:14> +n<> u<53> t p<71> c<52> s<70> l<8:12> el<8:14> +n u<54> t p<70> s<59> l<8:15> el<8:16> +n<1> u<55> t p<56> l<8:17> el<8:18> +n<> u<56> t p<57> c<55> l<8:17> el<8:18> +n<> u<57> t p<58> c<56> l<8:17> el<8:18> +n<> u<58> t p<59> c<57> l<8:17> el<8:18> +n<> u<59> t p<70> c<58> s<69> l<8:16> el<8:19> +n<3> u<60> t p<61> l<8:20> el<8:21> +n<> u<61> t p<62> c<60> l<8:20> el<8:21> +n<> u<62> t p<63> c<61> l<8:20> el<8:21> +n<> u<63> t p<68> c<62> s<67> l<8:20> el<8:21> +n<2> u<64> t p<65> l<8:22> el<8:23> +n<> u<65> t p<66> c<64> l<8:22> el<8:23> +n<> u<66> t p<67> c<65> l<8:22> el<8:23> +n<> u<67> t p<68> c<66> l<8:22> el<8:23> +n<> u<68> t p<69> c<63> l<8:20> el<8:23> +n<> u<69> t p<70> c<68> l<8:20> el<8:23> +n<> u<70> t p<71> c<54> l<8:14> el<8:24> +n<> u<71> t p<76> c<53> s<75> l<8:12> el<8:24> +n<2> u<72> t p<73> l<8:27> el<8:28> +n<> u<73> t p<74> c<72> l<8:27> el<8:28> +n<> u<74> t p<75> c<73> l<8:27> el<8:28> +n<> u<75> t p<76> c<74> l<8:27> el<8:28> +n<> u<76> t p<77> c<71> l<8:12> el<8:28> +n<> u<77> t p<78> c<76> l<8:12> el<8:28> +n<> u<78> t p<79> c<77> l<8:5> el<8:29> +n<> u<79> t p<80> c<78> l<8:5> el<8:29> +n<> u<80> t p<81> c<79> l<8:5> el<8:29> +n<> u<81> t p<82> c<80> l<8:5> el<8:29> +n<> u<82> t p<115> c<81> s<113> l<8:5> el<8:29> +n u<83> t p<84> l<9:12> el<9:14> +n<> u<84> t p<102> c<83> s<101> l<9:12> el<9:14> +n u<85> t p<101> s<90> l<9:15> el<9:16> +n<1> u<86> t p<87> l<9:17> el<9:18> +n<> u<87> t p<88> c<86> l<9:17> el<9:18> +n<> u<88> t p<89> c<87> l<9:17> el<9:18> +n<> u<89> t p<90> c<88> l<9:17> el<9:18> +n<> u<90> t p<101> c<89> s<100> l<9:16> el<9:19> +n<1> u<91> t p<92> l<9:20> el<9:21> +n<> u<92> t p<93> c<91> l<9:20> el<9:21> +n<> u<93> t p<94> c<92> l<9:20> el<9:21> +n<> u<94> t p<99> c<93> s<98> l<9:20> el<9:21> +n<0> u<95> t p<96> l<9:22> el<9:23> +n<> u<96> t p<97> c<95> l<9:22> el<9:23> +n<> u<97> t p<98> c<96> l<9:22> el<9:23> +n<> u<98> t p<99> c<97> l<9:22> el<9:23> +n<> u<99> t p<100> c<94> l<9:20> el<9:23> +n<> u<100> t p<101> c<99> l<9:20> el<9:23> +n<> u<101> t p<102> c<85> l<9:14> el<9:24> +n<> u<102> t p<107> c<84> s<106> l<9:12> el<9:24> +n<3> u<103> t p<104> l<9:27> el<9:28> +n<> u<104> t p<105> c<103> l<9:27> el<9:28> +n<> u<105> t p<106> c<104> l<9:27> el<9:28> +n<> u<106> t p<107> c<105> l<9:27> el<9:28> +n<> u<107> t p<108> c<102> l<9:12> el<9:28> +n<> u<108> t p<109> c<107> l<9:12> el<9:28> +n<> u<109> t p<110> c<108> l<9:5> el<9:29> +n<> u<110> t p<111> c<109> l<9:5> el<9:29> +n<> u<111> t p<112> c<110> l<9:5> el<9:29> +n<> u<112> t p<113> c<111> l<9:5> el<9:29> +n<> u<113> t p<115> c<112> s<114> l<9:5> el<9:29> +n<> u<114> t p<115> l<11:1> el<11:10> +n<> u<115> t p<116> c<43> l<5:1> el<11:10> +n<> u<116> t p<117> c<115> l<5:1> el<11:10> +n<> u<117> t p<118> c<38> l<1:1> el<11:10> +n<> u<118> t c<1> l<1:1> el<12:1> +AST_DEBUG_END +[WRN:PA0205] ${SURELOG_DIR}/tests/MultiPartSelect/dut.sv:5:1: No timescale set for "top". +[INF:CP0300] Compilation... +[INF:CP0303] ${SURELOG_DIR}/tests/MultiPartSelect/dut.sv:5:1: Compile module "work@top". +[INF:EL0526] Design Elaboration... +[NTE:EL0503] ${SURELOG_DIR}/tests/MultiPartSelect/dut.sv:5:1: Top level module "work@top". +[NTE:EL0508] Nb Top level modules: 1. +[NTE:EL0509] Max instance depth: 1. +[NTE:EL0510] Nb instances: 1. +[NTE:EL0511] Nb leaf instances: 1. +[INF:UH0706] Creating UHDM Model... +=== UHDM Object Stats Begin (Non-Elaborated Model) === +constant 20 +cont_assign 4 +design 1 +hier_path 4 +logic_net 1 +logic_typespec 1 +module_inst 4 +part_select 4 +range 2 +ref_obj 4 +ref_typespec 2 +struct_net 1 +struct_typespec 1 +typespec_member 1 +var_select 4 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... +=== UHDM Object Stats Begin (Elaborated Model) === +constant 20 +cont_assign 6 +design 1 +hier_path 6 +logic_net 1 +logic_typespec 1 +module_inst 4 +part_select 6 +range 2 +ref_obj 6 +ref_typespec 2 +struct_net 1 +struct_typespec 1 +typespec_member 1 +var_select 6 +=== UHDM Object Stats End === +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/MultiPartSelect/slpp_all/surelog.uhdm ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/MultiPartSelect/slpp_all/checker/surelog.chk.html ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/MultiPartSelect/slpp_all/surelog.uhdm ... +[INF:UH0711] Decompiling UHDM... +====== UHDM ======= +design: (work@top) +|vpiElaborated:1 +|vpiName:work@top +|uhdmallModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPartSelect/dut.sv, line:5:1, endln:11:10 + |vpiParent: + \_design: (work@top) + |vpiFullName:work@top + |vpiDefName:work@top + |vpiNet: + \_logic_net: (work@top.xx), line:7:11, endln:7:13 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPartSelect/dut.sv, line:5:1, endln:11:10 + |vpiName:xx + |vpiFullName:work@top.xx + |vpiContAssign: + \_cont_assign: , line:8:12, endln:8:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPartSelect/dut.sv, line:5:1, endln:11:10 + |vpiRhs: + \_constant: , line:8:27, endln:8:28 + |vpiParent: + \_cont_assign: , line:8:12, endln:8:28 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiLhs: + \_hier_path: (xx.a[1][3:2]), line:8:12, endln:8:24 + |vpiParent: + \_cont_assign: , line:8:12, endln:8:28 + |vpiActual: + \_ref_obj: (xx), line:8:15, endln:8:16 + |vpiParent: + \_hier_path: (xx.a[1][3:2]), line:8:12, endln:8:24 + |vpiName:xx + |vpiActual: + \_var_select: (work@top.xx.a[1][3:2].a), line:8:15, endln:8:19 + |vpiParent: + \_hier_path: (xx.a[1][3:2]), line:8:12, endln:8:24 + |vpiName:a + |vpiFullName:work@top.xx.a[1][3:2].a + |vpiIndex: + \_constant: , line:8:17, endln:8:18 + |vpiParent: + \_var_select: (work@top.xx.a[1][3:2].a), line:8:15, endln:8:19 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiIndex: + \_part_select: (work@top.xx.a[1][3:2].a), line:8:20, endln:8:23 + |vpiParent: + \_var_select: (work@top.xx.a[1][3:2].a), line:8:15, endln:8:19 + |vpiFullName:work@top.xx.a[1][3:2].a + |vpiConstantSelect:1 + |vpiLeftRange: + \_constant: , line:8:20, endln:8:21 + |vpiDecompile:3 + |vpiSize:64 + |UINT:3 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:8:22, endln:8:23 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiName:xx.a[1][3:2] + |vpiContAssign: + \_cont_assign: , line:9:12, endln:9:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPartSelect/dut.sv, line:5:1, endln:11:10 + |vpiRhs: + \_constant: , line:9:27, endln:9:28 + |vpiParent: + \_cont_assign: , line:9:12, endln:9:28 + |vpiDecompile:3 + |vpiSize:64 + |UINT:3 + |vpiConstType:9 + |vpiLhs: + \_hier_path: (xx.a[1][1:0]), line:9:12, endln:9:24 + |vpiParent: + \_cont_assign: , line:9:12, endln:9:28 + |vpiActual: + \_ref_obj: (xx), line:9:15, endln:9:16 + |vpiParent: + \_hier_path: (xx.a[1][1:0]), line:9:12, endln:9:24 + |vpiName:xx + |vpiActual: + \_var_select: (work@top.xx.a[1][1:0].a), line:9:15, endln:9:19 + |vpiParent: + \_hier_path: (xx.a[1][1:0]), line:9:12, endln:9:24 + |vpiName:a + |vpiFullName:work@top.xx.a[1][1:0].a + |vpiIndex: + \_constant: , line:9:17, endln:9:18 + |vpiParent: + \_var_select: (work@top.xx.a[1][1:0].a), line:9:15, endln:9:19 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiIndex: + \_part_select: (work@top.xx.a[1][1:0].a), line:9:20, endln:9:23 + |vpiParent: + \_var_select: (work@top.xx.a[1][1:0].a), line:9:15, endln:9:19 + |vpiFullName:work@top.xx.a[1][1:0].a + |vpiConstantSelect:1 + |vpiLeftRange: + \_constant: , line:9:20, endln:9:21 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:9:22, endln:9:23 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiName:xx.a[1][1:0] +|vpiTypedef: +\_struct_typespec: (tier1), line:1:9, endln:3:2 + |vpiParent: + \_design: (work@top) + |vpiName:tier1 + |vpiInstance: + \_design: (work@top) + |vpiPacked:1 + |vpiTypespecMember: + \_typespec_member: (a), line:2:22, endln:2:23 + |vpiParent: + \_struct_typespec: (tier1), line:1:9, endln:3:2 + |vpiName:a + |vpiTypespec: + \_ref_typespec: (tier1.a) + |vpiParent: + \_typespec_member: (a), line:2:22, endln:2:23 + |vpiFullName:tier1.a + |vpiActual: + \_logic_typespec: , line:2:5, endln:2:21 + |vpiRefFile:${SURELOG_DIR}/tests/MultiPartSelect/dut.sv + |vpiRefLineNo:2 + |vpiRefColumnNo:5 + |vpiRefEndLineNo:2 + |vpiRefEndColumnNo:21 +|uhdmtopModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPartSelect/dut.sv, line:5:1, endln:11:10 + |vpiName:work@top + |vpiDefName:work@top + |vpiTop:1 + |vpiNet: + \_struct_net: (work@top.xx), line:7:11, endln:7:13 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPartSelect/dut.sv, line:5:1, endln:11:10 + |vpiTypespec: + \_ref_typespec: (work@top.xx) + |vpiParent: + \_struct_net: (work@top.xx), line:7:11, endln:7:13 + |vpiFullName:work@top.xx + |vpiActual: + \_struct_typespec: (tier1), line:1:9, endln:3:2 + |vpiName:xx + |vpiFullName:work@top.xx + |vpiTopModule:1 + |vpiContAssign: + \_cont_assign: , line:8:12, endln:8:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPartSelect/dut.sv, line:5:1, endln:11:10 + |vpiRhs: + \_constant: , line:8:27, endln:8:28 + |vpiLhs: + \_hier_path: (xx.a[1][3:2]), line:8:12, endln:8:24 + |vpiParent: + \_cont_assign: , line:8:12, endln:8:28 + |vpiActual: + \_ref_obj: (xx), line:8:15, endln:8:16 + |vpiParent: + \_hier_path: (xx.a[1][3:2]), line:8:12, endln:8:24 + |vpiName:xx + |vpiActual: + \_struct_net: (work@top.xx), line:7:11, endln:7:13 + |vpiActual: + \_var_select: (work@top.xx.a[1][3:2].a), line:8:15, endln:8:19 + |vpiParent: + \_hier_path: (xx.a[1][3:2]), line:8:12, endln:8:24 + |vpiName:a + |vpiFullName:work@top.xx.a[1][3:2].a + |vpiActual: + \_typespec_member: (a), line:2:22, endln:2:23 + |vpiIndex: + \_constant: , line:8:17, endln:8:18 + |vpiParent: + \_var_select: (work@top.xx.a[1][3:2].a), line:8:15, endln:8:19 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiIndex: + \_part_select: (work@top.xx.a[1][3:2].a), line:8:20, endln:8:23 + |vpiParent: + \_var_select: (work@top.xx.a[1][3:2].a), line:8:15, endln:8:19 + |vpiFullName:work@top.xx.a[1][3:2].a + |vpiConstantSelect:1 + |vpiLeftRange: + \_constant: , line:8:20, endln:8:21 + |vpiParent: + \_part_select: (work@top.xx.a[1][3:2].a), line:8:20, endln:8:23 + |vpiDecompile:3 + |vpiSize:64 + |UINT:3 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:8:22, endln:8:23 + |vpiParent: + \_part_select: (work@top.xx.a[1][3:2].a), line:8:20, endln:8:23 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiName:xx.a[1][3:2] + |vpiContAssign: + \_cont_assign: , line:9:12, endln:9:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPartSelect/dut.sv, line:5:1, endln:11:10 + |vpiRhs: + \_constant: , line:9:27, endln:9:28 + |vpiLhs: + \_hier_path: (xx.a[1][1:0]), line:9:12, endln:9:24 + |vpiParent: + \_cont_assign: , line:9:12, endln:9:28 + |vpiActual: + \_ref_obj: (xx), line:9:15, endln:9:16 + |vpiParent: + \_hier_path: (xx.a[1][1:0]), line:9:12, endln:9:24 + |vpiName:xx + |vpiActual: + \_struct_net: (work@top.xx), line:7:11, endln:7:13 + |vpiActual: + \_var_select: (work@top.xx.a[1][1:0].a), line:9:15, endln:9:19 + |vpiParent: + \_hier_path: (xx.a[1][1:0]), line:9:12, endln:9:24 + |vpiName:a + |vpiFullName:work@top.xx.a[1][1:0].a + |vpiActual: + \_typespec_member: (a), line:2:22, endln:2:23 + |vpiIndex: + \_constant: , line:9:17, endln:9:18 + |vpiParent: + \_var_select: (work@top.xx.a[1][1:0].a), line:9:15, endln:9:19 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiIndex: + \_part_select: (work@top.xx.a[1][1:0].a), line:9:20, endln:9:23 + |vpiParent: + \_var_select: (work@top.xx.a[1][1:0].a), line:9:15, endln:9:19 + |vpiFullName:work@top.xx.a[1][1:0].a + |vpiConstantSelect:1 + |vpiLeftRange: + \_constant: , line:9:20, endln:9:21 + |vpiParent: + \_part_select: (work@top.xx.a[1][1:0].a), line:9:20, endln:9:23 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:9:22, endln:9:23 + |vpiParent: + \_part_select: (work@top.xx.a[1][1:0].a), line:9:20, endln:9:23 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiName:xx.a[1][1:0] +\_weaklyReferenced: +\_logic_typespec: , line:2:5, endln:2:21 + |vpiParent: + \_typespec_member: (a), line:2:22, endln:2:23 + |vpiRange: + \_range: , line:2:11, endln:2:16 + |vpiParent: + \_logic_typespec: , line:2:5, endln:2:21 + |vpiLeftRange: + \_constant: , line:2:12, endln:2:13 + |vpiParent: + \_range: , line:2:11, endln:2:16 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:2:14, endln:2:15 + |vpiParent: + \_range: , line:2:11, endln:2:16 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiRange: + \_range: , line:2:16, endln:2:21 + |vpiParent: + \_logic_typespec: , line:2:5, endln:2:21 + |vpiLeftRange: + \_constant: , line:2:17, endln:2:18 + |vpiParent: + \_range: , line:2:16, endln:2:21 + |vpiDecompile:3 + |vpiSize:64 + |UINT:3 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:2:19, endln:2:20 + |vpiParent: + \_range: , line:2:16, endln:2:21 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_cont_assign: , line:8:12, endln:8:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPartSelect/dut.sv, line:5:1, endln:11:10 + |vpiRhs: + \_constant: , line:8:27, endln:8:28 + |vpiLhs: + \_hier_path: (xx.a[1][3:2]), line:8:12, endln:8:24 + |vpiParent: + \_cont_assign: , line:8:12, endln:8:28 + |vpiActual: + \_ref_obj: (xx), line:8:15, endln:8:16 + |vpiParent: + \_hier_path: (xx.a[1][3:2]), line:8:12, endln:8:24 + |vpiName:xx + |vpiActual: + \_var_select: (work@top.xx.a[1][3:2].a), line:8:15, endln:8:19 + |vpiParent: + \_hier_path: (xx.a[1][3:2]), line:8:12, endln:8:24 + |vpiName:a + |vpiFullName:work@top.xx.a[1][3:2].a + |vpiIndex: + \_constant: , line:8:17, endln:8:18 + |vpiIndex: + \_part_select: (work@top.xx.a[1][3:2].a), line:8:20, endln:8:23 + |vpiParent: + \_var_select: (work@top.xx.a[1][3:2].a), line:8:15, endln:8:19 + |vpiFullName:work@top.xx.a[1][3:2].a + |vpiConstantSelect:1 + |vpiLeftRange: + \_constant: , line:8:20, endln:8:21 + |vpiRightRange: + \_constant: , line:8:22, endln:8:23 + |vpiName:xx.a[1][3:2] +\_cont_assign: , line:9:12, endln:9:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiPartSelect/dut.sv, line:5:1, endln:11:10 + |vpiRhs: + \_constant: , line:9:27, endln:9:28 + |vpiLhs: + \_hier_path: (xx.a[1][1:0]), line:9:12, endln:9:24 + |vpiParent: + \_cont_assign: , line:9:12, endln:9:28 + |vpiActual: + \_ref_obj: (xx), line:9:15, endln:9:16 + |vpiParent: + \_hier_path: (xx.a[1][1:0]), line:9:12, endln:9:24 + |vpiName:xx + |vpiActual: + \_var_select: (work@top.xx.a[1][1:0].a), line:9:15, endln:9:19 + |vpiParent: + \_hier_path: (xx.a[1][1:0]), line:9:12, endln:9:24 + |vpiName:a + |vpiFullName:work@top.xx.a[1][1:0].a + |vpiIndex: + \_constant: , line:9:17, endln:9:18 + |vpiIndex: + \_part_select: (work@top.xx.a[1][1:0].a), line:9:20, endln:9:23 + |vpiParent: + \_var_select: (work@top.xx.a[1][1:0].a), line:9:15, endln:9:19 + |vpiFullName:work@top.xx.a[1][1:0].a + |vpiConstantSelect:1 + |vpiLeftRange: + \_constant: , line:9:20, endln:9:21 + |vpiRightRange: + \_constant: , line:9:22, endln:9:23 + |vpiName:xx.a[1][1:0] +=================== +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 1 +[ NOTE] : 5 + +============================== Begin RoundTrip Results ============================== +[roundtrip]: ${SURELOG_DIR}/tests/MultiPartSelect/dut.sv | ${SURELOG_DIR}/build/regression/MultiPartSelect/roundtrip/dut_000.sv | 3 | 11 | +============================== End RoundTrip Results ============================== diff --git a/tests/MultiPartSelect/MultiPartSelect.sl b/tests/MultiPartSelect/MultiPartSelect.sl new file mode 100644 index 0000000000..b461620aca --- /dev/null +++ b/tests/MultiPartSelect/MultiPartSelect.sl @@ -0,0 +1 @@ +-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin diff --git a/tests/MultiPartSelect/dut.sv b/tests/MultiPartSelect/dut.sv new file mode 100644 index 0000000000..ac64b845c4 --- /dev/null +++ b/tests/MultiPartSelect/dut.sv @@ -0,0 +1,11 @@ +typedef struct packed { + logic [1:0][3:0] a; +} tier1; + +module top(); + + tier1 xx; + assign xx.a[1][3:2] = 2; + assign xx.a[1][1:0] = 3; + +endmodule