From 55adc24e20614992d3ee3497269ee41afcf94e8d Mon Sep 17 00:00:00 2001
From: alaindargelas <63669492+alaindargelas@users.noreply.github.com>
Date: Wed, 29 Nov 2023 20:13:01 -0800
Subject: [PATCH] Revert "typespec bug"

---
 src/DesignCompile/ElaborationStep.cpp         | 205 +++++++------
 .../ArrayMethodIterator.log                   |   2 -
 tests/BitSelectExpr/BitSelectExpr.log         |  71 +++--
 tests/BitSelectSelect/BitSelectSelect.log     | 111 ++++---
 tests/BitsOp/BitsOp.log                       |  21 +-
 tests/ClassFsm/ClassFsm.log                   |   2 -
 tests/ClassMemberRef/ClassMemberRef.log       |   2 -
 tests/ClassMethodCall/ClassMethodCall.log     |   2 -
 tests/ClassMini/ClassMini.log                 |   2 -
 tests/ClassParamAsParam/ClassParamAsParam.log |  36 ++-
 tests/ClassTypeParam/ClassTypeParam.log       |  38 ++-
 tests/FuncStruct/FuncStruct.log               |  87 +-----
 tests/HierBitSlice/HierBitSlice.log           | 270 +++++-------------
 tests/HierPathLhs/HierPathLhs.log             | 111 ++++---
 tests/LogicTypedef/LogicTypedef.log           |  38 +--
 tests/LogicTypespec/LogicTypespec.log         |  39 ++-
 tests/LowMemPkg/LowMemPkg.log                 |  15 +-
 tests/MultiIndexBind/MultiIndexBind.log       | 111 ++++---
 tests/NetLValue/NetLValue.log                 |  71 +++--
 tests/NetType/NetType.log                     |  12 -
 tests/PackageNet/PackageNet.log               |  21 +-
 tests/PackedArrayAssign/PackedArrayAssign.log |  75 +++--
 tests/PackedArrayStruct/PackedArrayStruct.log |  12 +-
 tests/PackedEnumPort/PackedEnumPort.log       |  72 +++--
 tests/ParamTypespec2/ParamTypespec2.log       |  71 +++--
 tests/SelectSelect/SelectSelect.log           | 111 ++++---
 tests/Selects/Selects.log                     |  73 +++--
 tests/StructVarImp/StructVarImp.log           |  71 +++--
 tests/TypedefAlias/TypedefAlias.log           |  25 +-
 tests/UnitEnum/UnitEnum.log                   |   4 -
 tests/UnitTest/UnitTest.log                   |   2 -
 tests/UnpackedTypespec/UnpackedTypespec.log   |  47 ++-
 third_party/tests/AzadiRTL/AzadiRTL.log       |  10 +-
 third_party/tests/CoresSweRV/CoresSweRV.log   |  12 +-
 .../tests/CoresSweRVMP/CoresSweRVMP.log       |  14 +-
 .../Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log  |  24 +-
 .../Earlgrey_Verilator_01_05_21.log           |  36 +--
 .../sim-verilator/Earlgrey_Verilator_0_1.log  |  16 +-
 third_party/tests/IncompTitan/IncompTitan.log |  12 +-
 .../tests/NyuziProcessor/NyuziProcessor.log   |  20 +-
 third_party/tests/OVMSwitch/OVMSwitch.log     |   6 +-
 third_party/tests/Opentitan/Earlgrey.log      |  16 +-
 third_party/tests/Opentitan/Opentitan.log     |  16 +-
 third_party/tests/Rp32/rp32.log               |  12 +-
 third_party/tests/Scr1/Scr1.log               |   8 +-
 third_party/tests/Scr1SvTests/Scr1SvTests.log |   8 +-
 third_party/tests/Tnoc/Tnoc.log               |   2 +-
 47 files changed, 871 insertions(+), 1171 deletions(-)

diff --git a/src/DesignCompile/ElaborationStep.cpp b/src/DesignCompile/ElaborationStep.cpp
index d89454caaf..3bf4e71e93 100644
--- a/src/DesignCompile/ElaborationStep.cpp
+++ b/src/DesignCompile/ElaborationStep.cpp
@@ -1676,113 +1676,7 @@ any* ElaborationStep::makeVar_(DesignComponent* component, Signal* sig,
 
   variables* obj = nullptr;
   bool found = false;
-
-  while ((!found) && dtype) {
-    if (Parameter* sit =
-            const_cast<Parameter*>(datatype_cast<const Parameter*>(dtype))) {
-      if (UHDM::typespec* spec = elabTypeParameter_(component, sit, instance)) {
-        if (variables* var = m_helper.getSimpleVarFromTypespec(
-                spec, packedDimensions, m_compileDesign)) {
-          var->VpiConstantVariable(sig->isConst());
-          var->VpiSigned(sig->isSigned());
-          var->VpiName(signame);
-          if (assignExp != nullptr) {
-            var->Expr(assignExp);
-            assignExp->VpiParent(var);
-          }
-          obj = var;
-          found = true;
-          break;
-        }
-      }
-    }
-    dtype = dtype->getDefinition();
-  }
-
-  if ((found == false) && tps) {
-    UHDM::UHDM_OBJECT_TYPE tpstype = tps->UhdmType();
-    found = true;
-    if (tpstype == uhdmstruct_typespec) {
-      struct_var* stv = s.MakeStruct_var();
-      obj = stv;
-    } else if (tpstype == uhdmlogic_typespec) {
-      logic_var* stv = s.MakeLogic_var();
-      // Do not set packedDimensions, it is a repeat of the typespec packed
-      // dimension.
-      // stv->Ranges(packedDimensions);
-      obj = stv;
-    } else if (tpstype == uhdmenum_typespec) {
-      enum_var* stv = s.MakeEnum_var();
-      obj = stv;
-    } else if (tpstype == uhdmbit_typespec) {
-      bit_var* stv = s.MakeBit_var();
-      stv->Ranges(unpackedDimensions);
-      obj = stv;
-    } else if (tpstype == uhdmbyte_typespec) {
-      byte_var* stv = s.MakeByte_var();
-      obj = stv;
-    } else if (tpstype == uhdmreal_typespec) {
-      real_var* stv = s.MakeReal_var();
-      obj = stv;
-    } else if (tpstype == uhdmint_typespec) {
-      int_var* stv = s.MakeInt_var();
-      obj = stv;
-    } else if (tpstype == uhdminteger_typespec) {
-      integer_var* stv = s.MakeInteger_var();
-      obj = stv;
-    } else if (tpstype == uhdmlong_int_typespec) {
-      long_int_var* stv = s.MakeLong_int_var();
-      obj = stv;
-    } else if (tpstype == uhdmshort_int_typespec) {
-      short_int_var* stv = s.MakeShort_int_var();
-      obj = stv;
-    } else if (tpstype == uhdmstring_typespec) {
-      string_var* stv = s.MakeString_var();
-      obj = stv;
-    } else if (tpstype == uhdmbit_typespec) {
-      bit_var* stv = s.MakeBit_var();
-      obj = stv;
-    } else if (tpstype == uhdmbyte_typespec) {
-      byte_var* stv = s.MakeByte_var();
-      obj = stv;
-    } else if (tpstype == uhdmtime_typespec) {
-      time_var* stv = s.MakeTime_var();
-      obj = stv;
-    } else if (tpstype == uhdmunion_typespec) {
-      union_var* stv = s.MakeUnion_var();
-      obj = stv;
-    } else if (tpstype == uhdmclass_typespec) {
-      class_var* stv = s.MakeClass_var();
-      obj = stv;
-    } else if (tpstype == uhdmpacked_array_typespec) {
-      packed_array_var* stv = s.MakePacked_array_var();
-      obj = stv;
-    } else if (tpstype == uhdmarray_typespec) {
-      UHDM::array_var* stv = s.MakeArray_var();
-      obj = stv;
-    } else {
-      found = false;
-    }
-
-    if (obj != nullptr) {
-      if (assignExp != nullptr) {
-        assignExp->VpiParent(obj);
-        obj->Expr(assignExp);
-      }
-      if (tps != nullptr) {
-        if (obj->Typespec() == nullptr) {
-          ref_typespec* rt = s.MakeRef_typespec();
-          rt->VpiParent(obj);
-          obj->Typespec(rt);
-        }
-        obj->Typespec()->Actual_typespec(tps);
-        tps->VpiParent(obj);
-      }
-      obj->VpiName(signame);
-    }
-  }
-
-  while ((!found) && dtype) {
+  while (dtype) {
     if (const TypeDef* tdef = datatype_cast<const TypeDef*>(dtype)) {
       if (tdef->getTypespec()) {
         tps = tdef->getTypespec();
@@ -1943,10 +1837,107 @@ any* ElaborationStep::makeVar_(DesignComponent* component, Signal* sig,
       obj = stv;
       found = true;
       break;
+    } else if (Parameter* sit = const_cast<Parameter*>(
+                   datatype_cast<const Parameter*>(dtype))) {
+      if (UHDM::typespec* spec = elabTypeParameter_(component, sit, instance)) {
+        if (variables* var = m_helper.getSimpleVarFromTypespec(
+                spec, packedDimensions, m_compileDesign)) {
+          var->VpiConstantVariable(sig->isConst());
+          var->VpiSigned(sig->isSigned());
+          var->VpiName(signame);
+          if (assignExp != nullptr) {
+            var->Expr(assignExp);
+            assignExp->VpiParent(var);
+          }
+          obj = var;
+          found = true;
+          break;
+        }
+      }
     }
     dtype = dtype->getDefinition();
   }
 
+  if ((found == false) && tps) {
+    UHDM::UHDM_OBJECT_TYPE tpstype = tps->UhdmType();
+    if (tpstype == uhdmstruct_typespec) {
+      struct_var* stv = s.MakeStruct_var();
+      obj = stv;
+    } else if (tpstype == uhdmlogic_typespec) {
+      logic_var* stv = s.MakeLogic_var();
+      // Do not set packedDimensions, it is a repeat of the typespec packed
+      // dimension.
+      // stv->Ranges(packedDimensions);
+      obj = stv;
+    } else if (tpstype == uhdmenum_typespec) {
+      enum_var* stv = s.MakeEnum_var();
+      obj = stv;
+    } else if (tpstype == uhdmbit_typespec) {
+      bit_var* stv = s.MakeBit_var();
+      stv->Ranges(unpackedDimensions);
+      obj = stv;
+    } else if (tpstype == uhdmbyte_typespec) {
+      byte_var* stv = s.MakeByte_var();
+      obj = stv;
+    } else if (tpstype == uhdmreal_typespec) {
+      real_var* stv = s.MakeReal_var();
+      obj = stv;
+    } else if (tpstype == uhdmint_typespec) {
+      int_var* stv = s.MakeInt_var();
+      obj = stv;
+    } else if (tpstype == uhdminteger_typespec) {
+      integer_var* stv = s.MakeInteger_var();
+      obj = stv;
+    } else if (tpstype == uhdmlong_int_typespec) {
+      long_int_var* stv = s.MakeLong_int_var();
+      obj = stv;
+    } else if (tpstype == uhdmshort_int_typespec) {
+      short_int_var* stv = s.MakeShort_int_var();
+      obj = stv;
+    } else if (tpstype == uhdmstring_typespec) {
+      string_var* stv = s.MakeString_var();
+      obj = stv;
+    } else if (tpstype == uhdmbit_typespec) {
+      bit_var* stv = s.MakeBit_var();
+      obj = stv;
+    } else if (tpstype == uhdmbyte_typespec) {
+      byte_var* stv = s.MakeByte_var();
+      obj = stv;
+    } else if (tpstype == uhdmtime_typespec) {
+      time_var* stv = s.MakeTime_var();
+      obj = stv;
+    } else if (tpstype == uhdmunion_typespec) {
+      union_var* stv = s.MakeUnion_var();
+      obj = stv;
+    } else if (tpstype == uhdmclass_typespec) {
+      class_var* stv = s.MakeClass_var();
+      obj = stv;
+    } else if (tpstype == uhdmpacked_array_typespec) {
+      packed_array_var* stv = s.MakePacked_array_var();
+      obj = stv;
+    } else if (tpstype == uhdmarray_typespec) {
+      UHDM::array_var* stv = s.MakeArray_var();
+      obj = stv;
+    }
+
+    if (obj != nullptr) {
+      if (assignExp != nullptr) {
+        assignExp->VpiParent(obj);
+        obj->Expr(assignExp);
+      }
+      if (tps != nullptr) {
+        if (obj->Typespec() == nullptr) {
+          ref_typespec* rt = s.MakeRef_typespec();
+          rt->VpiParent(obj);
+          obj->Typespec(rt);
+        }
+        obj->Typespec()->Actual_typespec(tps);
+        tps->VpiParent(obj);
+      }
+      obj->VpiName(signame);
+    }
+  }
+
   if (obj == nullptr) {
     variables* var = nullptr;
     if (subnettype == VObjectType::paIntegerAtomType_Shortint) {
diff --git a/tests/ArrayMethodIterator/ArrayMethodIterator.log b/tests/ArrayMethodIterator/ArrayMethodIterator.log
index 4ffee9b710..3d281514aa 100644
--- a/tests/ArrayMethodIterator/ArrayMethodIterator.log
+++ b/tests/ArrayMethodIterator/ArrayMethodIterator.log
@@ -628,8 +628,6 @@ design: (work@top)
     |vpiActual:
     \_class_typespec: (uvm_callback), line:10:50, endln:10:62
 \_class_typespec: (pkg::uvm_callbacks), line:29:1, endln:29:6
-  |vpiParent:
-  \_class_var: (work@top.c1), line:29:20, endln:29:22
   |vpiName:pkg::uvm_callbacks
   |vpiClassDefn:
   \_class_defn: (pkg::uvm_callbacks), file:${SURELOG_DIR}/tests/ArrayMethodIterator/dut.sv, line:10:1, endln:23:9
diff --git a/tests/BitSelectExpr/BitSelectExpr.log b/tests/BitSelectExpr/BitSelectExpr.log
index aedf0664ce..08aca8dab6 100644
--- a/tests/BitSelectExpr/BitSelectExpr.log
+++ b/tests/BitSelectExpr/BitSelectExpr.log
@@ -118,6 +118,7 @@ range                                                  3
 ref_obj                                                4
 ref_typespec                                           8
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 === UHDM Object Stats End ===
 [INF:UH0707] Elaborating UHDM...
@@ -139,6 +140,7 @@ range                                                  3
 ref_obj                                                6
 ref_typespec                                           9
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 === UHDM Object Stats End ===
 [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BitSelectExpr/slpp_all/surelog.uhdm ...
@@ -292,16 +294,41 @@ design: (work@top)
   \_packed_array_var: (work@top.sram_otp_key_o), line:7:29, endln:7:43
     |vpiParent:
     \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10
-    |vpiTypespec:
-    \_ref_typespec: (work@top.sram_otp_key_o)
-      |vpiParent:
-      \_packed_array_var: (work@top.sram_otp_key_o), line:7:29, endln:7:43
-      |vpiFullName:work@top.sram_otp_key_o
-      |vpiActual:
-      \_packed_array_typespec: , line:7:4, endln:7:28
     |vpiName:sram_otp_key_o
     |vpiFullName:work@top.sram_otp_key_o
     |vpiVisibility:1
+    |vpiRange:
+    \_range: , line:7:23, endln:7:28
+      |vpiParent:
+      \_packed_array_var: (work@top.sram_otp_key_o), line:7:29, endln:7:43
+      |vpiLeftRange:
+      \_constant: , line:7:24, endln:7:25
+        |vpiParent:
+        \_range: , line:7:23, endln:7:28
+        |vpiDecompile:2
+        |vpiSize:64
+        |UINT:2
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:7:26, endln:7:27
+        |vpiParent:
+        \_range: , line:7:23, endln:7:28
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiElement:
+    \_struct_var: (work@top.sram_otp_key_o)
+      |vpiParent:
+      \_packed_array_var: (work@top.sram_otp_key_o), line:7:29, endln:7:43
+      |vpiTypespec:
+      \_ref_typespec: (work@top.sram_otp_key_o)
+        |vpiParent:
+        \_struct_var: (work@top.sram_otp_key_o)
+        |vpiFullName:work@top.sram_otp_key_o
+        |vpiActual:
+        \_struct_typespec: (sram_otp_key_rsp_t), line:3:12, endln:5:5
+      |vpiFullName:work@top.sram_otp_key_o
   |vpiTypedef:
   \_struct_typespec: (sram_otp_key_rsp_t), line:3:12, endln:5:5
   |vpiDefName:work@top
@@ -374,36 +401,6 @@ design: (work@top)
   |vpiParent:
   \_int_var: (work@top.o), line:1:23, endln:1:24
   |vpiSigned:1
-\_packed_array_typespec: , line:7:4, endln:7:28
-  |vpiParent:
-  \_packed_array_var: (work@top.sram_otp_key_o), line:7:29, endln:7:43
-  |vpiRange:
-  \_range: , line:7:23, endln:7:28
-    |vpiParent:
-    \_packed_array_typespec: , line:7:4, endln:7:28
-    |vpiLeftRange:
-    \_constant: , line:7:24, endln:7:25
-      |vpiParent:
-      \_range: , line:7:23, endln:7:28
-      |vpiDecompile:2
-      |vpiSize:64
-      |UINT:2
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:7:26, endln:7:27
-      |vpiParent:
-      \_range: , line:7:23, endln:7:28
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiElemTypespec:
-  \_ref_typespec: (work@top.sram_otp_key_o)
-    |vpiParent:
-    \_packed_array_typespec: , line:7:4, endln:7:28
-    |vpiFullName:work@top.sram_otp_key_o
-    |vpiActual:
-    \_struct_typespec: (sram_otp_key_rsp_t), line:3:12, endln:5:5
 \_int_typespec: , line:1:19, endln:1:22
   |vpiSigned:1
 \_packed_array_typespec: , line:7:4, endln:7:28
diff --git a/tests/BitSelectSelect/BitSelectSelect.log b/tests/BitSelectSelect/BitSelectSelect.log
index 2f5752c7ab..bf7185b624 100644
--- a/tests/BitSelectSelect/BitSelectSelect.log
+++ b/tests/BitSelectSelect/BitSelectSelect.log
@@ -136,6 +136,7 @@ range                                                  7
 ref_obj                                                4
 ref_typespec                                           8
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 === UHDM Object Stats End ===
 [INF:UH0707] Elaborating UHDM...
@@ -157,6 +158,7 @@ range                                                  7
 ref_obj                                                6
 ref_typespec                                           9
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 === UHDM Object Stats End ===
 [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BitSelectSelect/slpp_all/surelog.uhdm ...
@@ -306,16 +308,61 @@ design: (work@top)
   \_packed_array_var: (work@top.a), line:7:28, endln:7:29
     |vpiParent:
     \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectSelect/dut.sv, line:2:1, endln:9:10
-    |vpiTypespec:
-    \_ref_typespec: (work@top.a)
-      |vpiParent:
-      \_packed_array_var: (work@top.a), line:7:28, endln:7:29
-      |vpiFullName:work@top.a
-      |vpiActual:
-      \_packed_array_typespec: , line:7:4, endln:7:27
     |vpiName:a
     |vpiFullName:work@top.a
     |vpiVisibility:1
+    |vpiRange:
+    \_range: , line:7:17, endln:7:22
+      |vpiParent:
+      \_packed_array_var: (work@top.a), line:7:28, endln:7:29
+      |vpiLeftRange:
+      \_constant: , line:7:18, endln:7:19
+        |vpiParent:
+        \_range: , line:7:17, endln:7:22
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:7:20, endln:7:21
+        |vpiParent:
+        \_range: , line:7:17, endln:7:22
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiRange:
+    \_range: , line:7:22, endln:7:27
+      |vpiParent:
+      \_packed_array_var: (work@top.a), line:7:28, endln:7:29
+      |vpiLeftRange:
+      \_constant: , line:7:23, endln:7:24
+        |vpiParent:
+        \_range: , line:7:22, endln:7:27
+        |vpiDecompile:2
+        |vpiSize:64
+        |UINT:2
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:7:25, endln:7:26
+        |vpiParent:
+        \_range: , line:7:22, endln:7:27
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiElement:
+    \_struct_var: (work@top.a)
+      |vpiParent:
+      \_packed_array_var: (work@top.a), line:7:28, endln:7:29
+      |vpiTypespec:
+      \_ref_typespec: (work@top.a)
+        |vpiParent:
+        \_struct_var: (work@top.a)
+        |vpiFullName:work@top.a
+        |vpiActual:
+        \_struct_typespec: (filter_ctl_t), line:3:12, endln:5:5
+      |vpiFullName:work@top.a
   |vpiTypedef:
   \_struct_typespec: (filter_ctl_t), line:3:12, endln:5:5
   |vpiDefName:work@top
@@ -426,56 +473,6 @@ design: (work@top)
   |vpiParent:
   \_int_var: (work@top.o), line:2:23, endln:2:24
   |vpiSigned:1
-\_packed_array_typespec: , line:7:4, endln:7:27
-  |vpiParent:
-  \_packed_array_var: (work@top.a), line:7:28, endln:7:29
-  |vpiRange:
-  \_range: , line:7:17, endln:7:22
-    |vpiParent:
-    \_packed_array_typespec: , line:7:4, endln:7:27
-    |vpiLeftRange:
-    \_constant: , line:7:18, endln:7:19
-      |vpiParent:
-      \_range: , line:7:17, endln:7:22
-      |vpiDecompile:1
-      |vpiSize:64
-      |UINT:1
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:7:20, endln:7:21
-      |vpiParent:
-      \_range: , line:7:17, endln:7:22
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiRange:
-  \_range: , line:7:22, endln:7:27
-    |vpiParent:
-    \_packed_array_typespec: , line:7:4, endln:7:27
-    |vpiLeftRange:
-    \_constant: , line:7:23, endln:7:24
-      |vpiParent:
-      \_range: , line:7:22, endln:7:27
-      |vpiDecompile:2
-      |vpiSize:64
-      |UINT:2
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:7:25, endln:7:26
-      |vpiParent:
-      \_range: , line:7:22, endln:7:27
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiElemTypespec:
-  \_ref_typespec: (work@top.a)
-    |vpiParent:
-    \_packed_array_typespec: , line:7:4, endln:7:27
-    |vpiFullName:work@top.a
-    |vpiActual:
-    \_struct_typespec: (filter_ctl_t), line:3:12, endln:5:5
 \_int_typespec: , line:2:19, endln:2:22
   |vpiSigned:1
 \_packed_array_typespec: , line:7:4, endln:7:22
diff --git a/tests/BitsOp/BitsOp.log b/tests/BitsOp/BitsOp.log
index b62980f2ff..2e6115ae6f 100644
--- a/tests/BitsOp/BitsOp.log
+++ b/tests/BitsOp/BitsOp.log
@@ -26,9 +26,9 @@
 always                                                 1
 assignment                                             1
 begin                                                  2
-bit_typespec                                           4
+bit_typespec                                           5
 bit_var                                                1
-constant                                             311
+constant                                             313
 cont_assign                                            2
 design                                                 1
 enum_const                                             4
@@ -50,7 +50,7 @@ param_assign                                          96
 parameter                                             96
 part_select                                            1
 port                                                   2
-range                                                 47
+range                                                 48
 ref_obj                                               77
 ref_typespec                                         231
 struct_net                                             2
@@ -63,9 +63,9 @@ typespec_member                                       32
 always                                                 2
 assignment                                             2
 begin                                                  4
-bit_typespec                                           4
+bit_typespec                                           5
 bit_var                                                1
-constant                                             311
+constant                                             313
 cont_assign                                            3
 design                                                 1
 enum_const                                             4
@@ -87,7 +87,7 @@ param_assign                                          96
 parameter                                             96
 part_select                                            2
 port                                                   3
-range                                                 47
+range                                                 48
 ref_obj                                               84
 ref_typespec                                         233
 struct_net                                             2
@@ -4158,16 +4158,7 @@ design: (work@dut)
       |UINT:0
       |vpiConstType:9
 \_bit_typespec: (MyBits), line:97:11, endln:97:31
-  |vpiParent:
-  \_bit_var: (work@dut.b), line:98:10, endln:98:11
   |vpiName:MyBits
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@dut.b.MyBits)
-    |vpiParent:
-    \_bit_typespec: (MyBits), line:97:11, endln:97:31
-    |vpiFullName:work@dut.b.MyBits
-    |vpiActual:
-    \_bit_typespec: (MyBits), line:97:11, endln:97:31
   |vpiRange:
   \_range: , line:97:14, endln:97:31
     |vpiParent:
diff --git a/tests/ClassFsm/ClassFsm.log b/tests/ClassFsm/ClassFsm.log
index 5fe7afc869..73b481ec50 100644
--- a/tests/ClassFsm/ClassFsm.log
+++ b/tests/ClassFsm/ClassFsm.log
@@ -2095,8 +2095,6 @@ design: (work@fsm_class)
   |vpiParent:
   \_logic_net: (work@fsm_class.x), line:1:49, endln:1:50
 \_class_typespec: (specificFSM), line:81:3, endln:81:14
-  |vpiParent:
-  \_class_var: (work@fsm_class.P), line:81:15, endln:81:16
   |vpiName:specificFSM
   |vpiClassDefn:
   \_class_defn: (work@fsm_class::specificFSM), file:${SURELOG_DIR}/tests/ClassFsm/dut.sv, line:26:3, endln:79:11
diff --git a/tests/ClassMemberRef/ClassMemberRef.log b/tests/ClassMemberRef/ClassMemberRef.log
index d60325524b..5b555cd187 100644
--- a/tests/ClassMemberRef/ClassMemberRef.log
+++ b/tests/ClassMemberRef/ClassMemberRef.log
@@ -565,8 +565,6 @@ design: (work@top)
   |vpiName:printer
 \_bit_typespec: , line:11:50, endln:11:53
 \_class_typespec: (pkg::uvm_printer), line:24:1, endln:24:6
-  |vpiParent:
-  \_class_var: (work@top.printer), line:24:18, endln:24:25
   |vpiName:pkg::uvm_printer
   |vpiClassDefn:
   \_class_defn: (pkg::uvm_printer), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:9:1, endln:14:9
diff --git a/tests/ClassMethodCall/ClassMethodCall.log b/tests/ClassMethodCall/ClassMethodCall.log
index e0b9502110..b89c3c3951 100644
--- a/tests/ClassMethodCall/ClassMethodCall.log
+++ b/tests/ClassMethodCall/ClassMethodCall.log
@@ -794,8 +794,6 @@ design: (work@door_mod)
 \_int_typespec: , line:29:19, endln:29:22
   |vpiSigned:1
 \_class_typespec: (pack::doorOpen), line:45:5, endln:45:11
-  |vpiParent:
-  \_class_var: (work@door_mod.open), line:45:20, endln:45:24
   |vpiName:pack::doorOpen
   |vpiClassDefn:
   \_class_defn: (pack::doorOpen), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:21:1, endln:38:9
diff --git a/tests/ClassMini/ClassMini.log b/tests/ClassMini/ClassMini.log
index f6fb7154d0..0d1bf9c678 100644
--- a/tests/ClassMini/ClassMini.log
+++ b/tests/ClassMini/ClassMini.log
@@ -539,8 +539,6 @@ design: (work@door_mod)
     \_constant: 
       |INT:0
 \_class_typespec: (pack::doorOpen), line:22:5, endln:22:11
-  |vpiParent:
-  \_class_var: (work@door_mod.open), line:22:20, endln:22:24
   |vpiName:pack::doorOpen
   |vpiClassDefn:
   \_class_defn: (pack::doorOpen), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:13:1, endln:17:9
diff --git a/tests/ClassParamAsParam/ClassParamAsParam.log b/tests/ClassParamAsParam/ClassParamAsParam.log
index da1925a895..829e407d37 100644
--- a/tests/ClassParamAsParam/ClassParamAsParam.log
+++ b/tests/ClassParamAsParam/ClassParamAsParam.log
@@ -78,16 +78,16 @@ design: (work@top)
     |vpiParent:
     \_class_defn: (work@config_db), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:14:1, endln:15:9
     |vpiRhs:
-    \_type_parameter: (work@top.misc2.config_db.T), line:14:23, endln:14:24
+    \_type_parameter: (config_db.T), line:14:23, endln:14:24
       |vpiParent:
       \_class_typespec: (config_db), line:18:3, endln:18:12
       |vpiName:T
-      |vpiFullName:work@top.misc2.config_db.T
+      |vpiFullName:config_db.T
       |vpiTypespec:
-      \_ref_typespec: (work@top.misc2.config_db.T)
+      \_ref_typespec: (config_db.T)
         |vpiParent:
-        \_type_parameter: (work@top.misc2.config_db.T), line:14:23, endln:14:24
-        |vpiFullName:work@top.misc2.config_db.T
+        \_type_parameter: (config_db.T), line:14:23, endln:14:24
+        |vpiFullName:config_db.T
         |vpiActual:
         \_class_typespec: (object), line:18:14, endln:18:20
     |vpiLhs:
@@ -145,7 +145,7 @@ design: (work@top)
     |vpiParent:
     \_class_defn: (work@resource), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:4:1, endln:5:9
     |vpiRhs:
-    \_type_parameter: (work@top.misc2.config_db.T), line:14:23, endln:14:24
+    \_type_parameter: (config_db.T), line:14:23, endln:14:24
     |vpiLhs:
     \_type_parameter: (work@resource::T), line:4:23, endln:4:24
 |uhdmallClasses:
@@ -186,7 +186,7 @@ design: (work@top)
     |vpiParent:
     \_class_defn: (work@resource_db), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:7:1, endln:12:9
     |vpiRhs:
-    \_type_parameter: (work@top.misc2.config_db.T), line:14:23, endln:14:24
+    \_type_parameter: (config_db.T), line:14:23, endln:14:24
     |vpiLhs:
     \_type_parameter: (work@resource_db::T), line:7:26, endln:7:27
   |vpiTypedef:
@@ -266,36 +266,34 @@ design: (work@top)
   |vpiClassDefn:
   \_class_defn: (work@resource), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:4:1, endln:5:9
 \_class_typespec: (config_db), line:18:3, endln:18:12
-  |vpiParent:
-  \_class_var: (work@top.misc2), line:18:32, endln:18:43
   |vpiName:config_db
   |vpiParameter:
-  \_type_parameter: (work@top.misc2.config_db.T), line:14:23, endln:14:24
+  \_type_parameter: (config_db.T), line:14:23, endln:14:24
   |vpiParamAssign:
   \_param_assign: , line:14:23, endln:14:24
     |vpiParent:
     \_class_typespec: (config_db), line:18:3, endln:18:12
     |vpiRhs:
-    \_type_parameter: (work@top.misc2.config_db.T), line:14:23, endln:14:24
+    \_type_parameter: (config_db.T), line:14:23, endln:14:24
     |vpiLhs:
     \_type_parameter: (work@config_db::T), line:14:23, endln:14:24
   |vpiClassDefn:
   \_class_defn: (work@config_db), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:14:1, endln:15:9
 \_class_typespec: (object), line:18:14, endln:18:20
   |vpiParent:
-  \_type_parameter: (work@top.misc2.config_db.T), line:14:23, endln:14:24
+  \_type_parameter: (config_db.T), line:14:23, endln:14:24
   |vpiName:object
   |vpiParameter:
-  \_type_parameter: (work@top.misc2.config_db.T.object.T), line:1:28, endln:1:29
+  \_type_parameter: (config_db.T.object.T), line:1:28, endln:1:29
     |vpiParent:
     \_class_typespec: (object), line:18:14, endln:18:20
     |vpiName:T
-    |vpiFullName:work@top.misc2.config_db.T.object.T
+    |vpiFullName:config_db.T.object.T
     |vpiTypespec:
-    \_ref_typespec: (work@top.misc2.config_db.T.object.T)
+    \_ref_typespec: (config_db.T.object.T)
       |vpiParent:
-      \_type_parameter: (work@top.misc2.config_db.T.object.T), line:1:28, endln:1:29
-      |vpiFullName:work@top.misc2.config_db.T.object.T
+      \_type_parameter: (config_db.T.object.T), line:1:28, endln:1:29
+      |vpiFullName:config_db.T.object.T
       |vpiActual:
       \_long_int_typespec: , line:18:22, endln:18:29
   |vpiParamAssign:
@@ -303,14 +301,14 @@ design: (work@top)
     |vpiParent:
     \_class_typespec: (object), line:18:14, endln:18:20
     |vpiRhs:
-    \_type_parameter: (work@top.misc2.config_db.T.object.T), line:1:28, endln:1:29
+    \_type_parameter: (config_db.T.object.T), line:1:28, endln:1:29
     |vpiLhs:
     \_type_parameter: (work@object::T), line:1:28, endln:1:29
   |vpiClassDefn:
   \_class_defn: (work@object), file:${SURELOG_DIR}/tests/ClassParamAsParam/dut.sv, line:1:9, endln:2:9
 \_long_int_typespec: , line:18:22, endln:18:29
   |vpiParent:
-  \_type_parameter: (work@top.misc2.config_db.T.object.T), line:1:28, endln:1:29
+  \_type_parameter: (config_db.T.object.T), line:1:28, endln:1:29
   |vpiSigned:1
 \_class_typespec: (resource_db), line:14:38, endln:14:49
   |vpiName:resource_db
diff --git a/tests/ClassTypeParam/ClassTypeParam.log b/tests/ClassTypeParam/ClassTypeParam.log
index 016e359a21..95c79d3717 100644
--- a/tests/ClassTypeParam/ClassTypeParam.log
+++ b/tests/ClassTypeParam/ClassTypeParam.log
@@ -135,16 +135,16 @@ design: (work@top)
     |vpiParent:
     \_class_defn: (work@uvm_config_db), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:16:1, endln:17:9
     |vpiRhs:
-    \_type_parameter: (work@top.misc2.uvm_config_db.T)
+    \_type_parameter: (uvm_config_db.T)
       |vpiParent:
       \_class_typespec: (uvm_config_db), line:26:3, endln:26:16
       |vpiName:T
-      |vpiFullName:work@top.misc2.uvm_config_db.T
+      |vpiFullName:uvm_config_db.T
       |vpiTypespec:
-      \_ref_typespec: (work@top.misc2.uvm_config_db.T)
+      \_ref_typespec: (uvm_config_db.T)
         |vpiParent:
-        \_type_parameter: (work@top.misc2.uvm_config_db.T)
-        |vpiFullName:work@top.misc2.uvm_config_db.T
+        \_type_parameter: (uvm_config_db.T)
+        |vpiFullName:uvm_config_db.T
         |vpiActual:
         \_class_typespec: (uvm_object), line:26:16, endln:26:37
     |vpiLhs:
@@ -154,16 +154,16 @@ design: (work@top)
     |vpiParent:
     \_class_defn: (work@uvm_config_db), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:16:1, endln:17:9
     |vpiRhs:
-    \_type_parameter: (work@top.misc2.uvm_config_db.T2), line:16:39, endln:16:41
+    \_type_parameter: (uvm_config_db.T2), line:16:39, endln:16:41
       |vpiParent:
       \_class_typespec: (uvm_config_db), line:26:3, endln:26:16
       |vpiName:T2
-      |vpiFullName:work@top.misc2.uvm_config_db.T2
+      |vpiFullName:uvm_config_db.T2
       |vpiTypespec:
-      \_ref_typespec: (work@top.misc2.uvm_config_db.T2)
+      \_ref_typespec: (uvm_config_db.T2)
         |vpiParent:
-        \_type_parameter: (work@top.misc2.uvm_config_db.T2), line:16:39, endln:16:41
-        |vpiFullName:work@top.misc2.uvm_config_db.T2
+        \_type_parameter: (uvm_config_db.T2), line:16:39, endln:16:41
+        |vpiFullName:uvm_config_db.T2
         |vpiActual:
         \_string_typespec: , line:26:30, endln:26:36
     |vpiLhs:
@@ -216,7 +216,7 @@ design: (work@top)
     |vpiParent:
     \_class_defn: (work@uvm_resource), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:4:1, endln:5:9
     |vpiRhs:
-    \_type_parameter: (work@top.misc2.uvm_config_db.T)
+    \_type_parameter: (uvm_config_db.T)
     |vpiLhs:
     \_type_parameter: (work@uvm_resource::T), line:4:27, endln:4:28
 |uhdmallClasses:
@@ -265,7 +265,7 @@ design: (work@top)
     |vpiParent:
     \_class_defn: (work@uvm_resource_db), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:7:1, endln:14:9
     |vpiRhs:
-    \_type_parameter: (work@top.misc2.uvm_config_db.T)
+    \_type_parameter: (uvm_config_db.T)
     |vpiLhs:
     \_type_parameter: (work@uvm_resource_db::T), line:7:30, endln:7:31
   |vpiTypedef:
@@ -445,19 +445,17 @@ design: (work@top)
   |vpiClassDefn:
   \_class_defn: (work@uvm_resource), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:4:1, endln:5:9
 \_class_typespec: (uvm_config_db), line:26:3, endln:26:16
-  |vpiParent:
-  \_class_var: (work@top.misc2), line:26:38, endln:26:49
   |vpiName:uvm_config_db
   |vpiParameter:
-  \_type_parameter: (work@top.misc2.uvm_config_db.T)
+  \_type_parameter: (uvm_config_db.T)
   |vpiParameter:
-  \_type_parameter: (work@top.misc2.uvm_config_db.T2), line:16:39, endln:16:41
+  \_type_parameter: (uvm_config_db.T2), line:16:39, endln:16:41
   |vpiParamAssign:
   \_param_assign: 
     |vpiParent:
     \_class_typespec: (uvm_config_db), line:26:3, endln:26:16
     |vpiRhs:
-    \_type_parameter: (work@top.misc2.uvm_config_db.T)
+    \_type_parameter: (uvm_config_db.T)
     |vpiLhs:
     \_type_parameter: (work@uvm_config_db::T), line:16:27, endln:16:28
   |vpiParamAssign:
@@ -465,20 +463,20 @@ design: (work@top)
     |vpiParent:
     \_class_typespec: (uvm_config_db), line:26:3, endln:26:16
     |vpiRhs:
-    \_type_parameter: (work@top.misc2.uvm_config_db.T2), line:16:39, endln:16:41
+    \_type_parameter: (uvm_config_db.T2), line:16:39, endln:16:41
     |vpiLhs:
     \_type_parameter: (work@uvm_config_db::T2), line:16:39, endln:16:41
   |vpiClassDefn:
   \_class_defn: (work@uvm_config_db), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:16:1, endln:17:9
 \_class_typespec: (uvm_object), line:26:16, endln:26:37
   |vpiParent:
-  \_type_parameter: (work@top.misc2.uvm_config_db.T)
+  \_type_parameter: (uvm_config_db.T)
   |vpiName:uvm_object
   |vpiClassDefn:
   \_class_defn: (work@uvm_object), file:${SURELOG_DIR}/tests/ClassTypeParam/dut.sv, line:1:9, endln:2:9
 \_string_typespec: , line:26:30, endln:26:36
   |vpiParent:
-  \_type_parameter: (work@top.misc2.uvm_config_db.T2), line:16:39, endln:16:41
+  \_type_parameter: (uvm_config_db.T2), line:16:39, endln:16:41
 \_class_typespec: (uvm_resource_db), line:16:55, endln:16:70
   |vpiName:uvm_resource_db
   |vpiClassDefn:
diff --git a/tests/FuncStruct/FuncStruct.log b/tests/FuncStruct/FuncStruct.log
index b9b405b0fb..03dfd90bee 100644
--- a/tests/FuncStruct/FuncStruct.log
+++ b/tests/FuncStruct/FuncStruct.log
@@ -246,7 +246,7 @@ AST_DEBUG_END
 assignment                                             6
 begin                                                  2
 bit_select                                             6
-constant                                              87
+constant                                              91
 cont_assign                                            4
 design                                                 1
 func_call                                              2
@@ -254,14 +254,14 @@ function                                               2
 import_typespec                                        1
 io_decl                                                4
 logic_net                                              2
-logic_typespec                                        30
+logic_typespec                                        32
 logic_var                                              7
 module_inst                                            6
 package                                                2
 packed_array_typespec                                  2
 param_assign                                           4
 parameter                                              4
-range                                                 36
+range                                                 38
 ref_obj                                                8
 ref_typespec                                          44
 === UHDM Object Stats End ===
@@ -270,7 +270,7 @@ ref_typespec                                          44
 assignment                                            12
 begin                                                  5
 bit_select                                            10
-constant                                              87
+constant                                              91
 cont_assign                                            6
 design                                                 1
 func_call                                              2
@@ -278,14 +278,14 @@ function                                               5
 import_typespec                                        1
 io_decl                                               10
 logic_net                                              2
-logic_typespec                                        30
+logic_typespec                                        32
 logic_var                                             13
 module_inst                                            6
 package                                                2
 packed_array_typespec                                  2
 param_assign                                           4
 parameter                                              4
-range                                                 36
+range                                                 38
 ref_obj                                               15
 ref_typespec                                          56
 === UHDM Object Stats End ===
@@ -873,7 +873,7 @@ design: (work@dut)
       \_logic_var: (work@dut.w), line:14:19, endln:14:20
       |vpiFullName:work@dut.w
       |vpiActual:
-      \_logic_typespec: , line:14:1, endln:14:18
+      \_logic_typespec: (sha_word_t), line:2:9, endln:2:21
     |vpiName:w
     |vpiFullName:work@dut.w
     |vpiVisibility:1
@@ -887,7 +887,7 @@ design: (work@dut)
       \_logic_var: (work@dut.hash), line:15:18, endln:15:22
       |vpiFullName:work@dut.hash
       |vpiActual:
-      \_logic_typespec: , line:15:1, endln:15:17
+      \_logic_typespec: (sha_word_t), line:2:9, endln:2:21
     |vpiName:hash
     |vpiFullName:work@dut.hash
     |vpiVisibility:1
@@ -1525,45 +1525,8 @@ design: (work@dut)
       |vpiSize:64
       |UINT:0
       |vpiConstType:9
-\_logic_typespec: , line:14:1, endln:14:18
-  |vpiParent:
-  \_logic_var: (work@dut.w), line:14:19, endln:14:20
-  |vpiElemTypespec:
-  \_ref_typespec: (work@dut.w)
-    |vpiParent:
-    \_logic_typespec: , line:14:1, endln:14:18
-    |vpiFullName:work@dut.w
-    |vpiActual:
-    \_logic_typespec: (sha_word_t), line:2:9, endln:2:21
-  |vpiRange:
-  \_range: , line:14:12, endln:14:18
-    |vpiParent:
-    \_logic_typespec: , line:14:1, endln:14:18
-    |vpiLeftRange:
-    \_constant: , line:14:13, endln:14:15
-      |vpiParent:
-      \_range: , line:14:12, endln:14:18
-      |vpiDecompile:15
-      |vpiSize:64
-      |UINT:15
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:14:16, endln:14:17
-      |vpiParent:
-      \_range: , line:14:12, endln:14:18
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
 \_logic_typespec: (sha_word_t), line:2:9, endln:2:21
   |vpiName:sha_word_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (sha_word_t)
-    |vpiParent:
-    \_logic_typespec: (sha_word_t), line:2:9, endln:2:21
-    |vpiFullName:sha_word_t
-    |vpiActual:
-    \_logic_typespec: (hmac_pkg::sha_word_t), line:2:9, endln:2:21
   |vpiInstance:
   \_package: hmac_pkg (hmac_pkg::), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:1:1, endln:9:11
   |vpiRange:
@@ -1586,42 +1549,8 @@ design: (work@dut)
       |vpiSize:64
       |UINT:0
       |vpiConstType:9
-\_logic_typespec: , line:15:1, endln:15:17
-  |vpiElemTypespec:
-  \_ref_typespec: 
-    |vpiParent:
-    \_logic_typespec: , line:15:1, endln:15:17
-    |vpiActual:
-    \_logic_typespec: (sha_word_t), line:2:9, endln:2:21
-  |vpiRange:
-  \_range: , line:15:12, endln:15:17
-    |vpiParent:
-    \_logic_typespec: , line:15:1, endln:15:17
-    |vpiLeftRange:
-    \_constant: , line:15:13, endln:15:14
-      |vpiParent:
-      \_range: , line:15:12, endln:15:17
-      |vpiDecompile:7
-      |vpiSize:64
-      |UINT:7
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:15:15, endln:15:16
-      |vpiParent:
-      \_range: , line:15:12, endln:15:17
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
 \_logic_typespec: (sha_word_t), line:2:9, endln:2:21
   |vpiName:sha_word_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (sha_word_t)
-    |vpiParent:
-    \_logic_typespec: (sha_word_t), line:2:9, endln:2:21
-    |vpiFullName:sha_word_t
-    |vpiActual:
-    \_logic_typespec: (hmac_pkg::sha_word_t), line:2:9, endln:2:21
   |vpiInstance:
   \_package: hmac_pkg (hmac_pkg::), file:${SURELOG_DIR}/tests/FuncStruct/dut.sv, line:1:1, endln:9:11
   |vpiRange:
diff --git a/tests/HierBitSlice/HierBitSlice.log b/tests/HierBitSlice/HierBitSlice.log
index 960a65d0d1..ead4b450eb 100644
--- a/tests/HierBitSlice/HierBitSlice.log
+++ b/tests/HierBitSlice/HierBitSlice.log
@@ -4567,7 +4567,7 @@ begin                                                 26
 bit_select                                            24
 case_item                                            193
 case_stmt                                              8
-constant                                             551
+constant                                             575
 cont_assign                                           30
 design                                                 1
 event_control                                          2
@@ -4580,7 +4580,7 @@ if_stmt                                                1
 int_typespec                                           2
 integer_typespec                                       2
 logic_net                                             52
-logic_typespec                                       118
+logic_typespec                                       130
 logic_var                                             46
 module_inst                                           12
 operation                                            233
@@ -4588,7 +4588,7 @@ packed_array_typespec                                  2
 parameter                                              2
 part_select                                           16
 port                                                  58
-range                                                 60
+range                                                 72
 ref_module                                             2
 ref_obj                                              581
 ref_typespec                                         204
@@ -4609,7 +4609,7 @@ begin                                                 51
 bit_select                                            47
 case_item                                            386
 case_stmt                                             16
-constant                                             557
+constant                                             581
 cont_assign                                           55
 design                                                 1
 event_control                                          4
@@ -4622,7 +4622,7 @@ if_stmt                                                2
 int_typespec                                           2
 integer_typespec                                       2
 logic_net                                             52
-logic_typespec                                       118
+logic_typespec                                       130
 logic_var                                             76
 module_inst                                           14
 operation                                            431
@@ -4630,7 +4630,7 @@ packed_array_typespec                                  2
 parameter                                              2
 part_select                                           28
 port                                                  87
-range                                                 60
+range                                                 72
 ref_module                                             2
 ref_obj                                             1106
 ref_typespec                                         275
@@ -22246,16 +22246,7 @@ design: (work@int_execute_stage)
       |UINT:0
       |vpiConstType:9
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_operand1), line:101:22, endln:101:35
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].lane_operand1.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_operand1.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -22276,30 +22267,8 @@ design: (work@int_execute_stage)
       |vpiSize:64
       |UINT:0
       |vpiConstType:9
-\_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_operand1), line:101:22, endln:101:35
-  |vpiParent:
-  \_gen_scope: (work@int_execute_stage.lane_alu_gen[0]), line:100:9, endln:274:12
-  |vpiTypespec:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].lane_operand1)
-    |vpiParent:
-    \_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_operand1), line:101:22, endln:101:35
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_operand1
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiName:lane_operand1
-  |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_operand1
-  |vpiVisibility:1
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_operand2), line:102:22, endln:102:35
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].lane_operand2.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_operand2.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -22334,16 +22303,7 @@ design: (work@int_execute_stage)
   |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_operand2
   |vpiVisibility:1
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_result), line:103:22, endln:103:33
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].lane_result.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_result.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -22364,30 +22324,8 @@ design: (work@int_execute_stage)
       |vpiSize:64
       |UINT:0
       |vpiConstType:9
-\_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_result), line:103:22, endln:103:33
-  |vpiParent:
-  \_gen_scope: (work@int_execute_stage.lane_alu_gen[0]), line:100:9, endln:274:12
-  |vpiTypespec:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].lane_result)
-    |vpiParent:
-    \_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_result), line:103:22, endln:103:33
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_result
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiName:lane_result
-  |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_result
-  |vpiVisibility:1
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[0].difference), line:104:22, endln:104:32
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].difference.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].difference.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -22574,16 +22512,7 @@ design: (work@int_execute_stage)
   |vpiFullName:work@int_execute_stage.lane_alu_gen[0].tz
   |vpiVisibility:1
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[0].reciprocal), line:112:22, endln:112:32
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].reciprocal.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].reciprocal.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -22670,16 +22599,7 @@ design: (work@int_execute_stage)
   |vpiFullName:work@int_execute_stage.lane_alu_gen[0].shift_in_sign
   |vpiVisibility:1
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[0].rshift), line:116:22, endln:116:28
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].rshift.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].rshift.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -22700,19 +22620,6 @@ design: (work@int_execute_stage)
       |vpiSize:64
       |UINT:0
       |vpiConstType:9
-\_logic_var: (work@int_execute_stage.lane_alu_gen[0].rshift), line:116:22, endln:116:28
-  |vpiParent:
-  \_gen_scope: (work@int_execute_stage.lane_alu_gen[0]), line:100:9, endln:274:12
-  |vpiTypespec:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].rshift)
-    |vpiParent:
-    \_logic_var: (work@int_execute_stage.lane_alu_gen[0].rshift), line:116:22, endln:116:28
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].rshift
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiName:rshift
-  |vpiFullName:work@int_execute_stage.lane_alu_gen[0].rshift
-  |vpiVisibility:1
 \_bit_select: (work@int_execute_stage.lane_alu_gen[1].difference), line:121:42, endln:121:44
   |vpiParent:
   \_cont_assign: , line:121:20, endln:121:45
@@ -24873,16 +24780,7 @@ design: (work@int_execute_stage)
       |UINT:0
       |vpiConstType:9
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_operand1), line:101:22, endln:101:35
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].lane_operand1.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_operand1.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -24903,30 +24801,8 @@ design: (work@int_execute_stage)
       |vpiSize:64
       |UINT:0
       |vpiConstType:9
-\_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_operand1), line:101:22, endln:101:35
-  |vpiParent:
-  \_gen_scope: (work@int_execute_stage.lane_alu_gen[1]), line:100:9, endln:274:12
-  |vpiTypespec:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].lane_operand1)
-    |vpiParent:
-    \_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_operand1), line:101:22, endln:101:35
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_operand1
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiName:lane_operand1
-  |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_operand1
-  |vpiVisibility:1
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_operand2), line:102:22, endln:102:35
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].lane_operand2.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_operand2.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -24961,16 +24837,7 @@ design: (work@int_execute_stage)
   |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_operand2
   |vpiVisibility:1
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_result), line:103:22, endln:103:33
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].lane_result.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_result.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -24991,30 +24858,8 @@ design: (work@int_execute_stage)
       |vpiSize:64
       |UINT:0
       |vpiConstType:9
-\_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_result), line:103:22, endln:103:33
-  |vpiParent:
-  \_gen_scope: (work@int_execute_stage.lane_alu_gen[1]), line:100:9, endln:274:12
-  |vpiTypespec:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].lane_result)
-    |vpiParent:
-    \_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_result), line:103:22, endln:103:33
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_result
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiName:lane_result
-  |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_result
-  |vpiVisibility:1
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[1].difference), line:104:22, endln:104:32
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].difference.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].difference.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -25201,16 +25046,7 @@ design: (work@int_execute_stage)
   |vpiFullName:work@int_execute_stage.lane_alu_gen[1].tz
   |vpiVisibility:1
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[1].reciprocal), line:112:22, endln:112:32
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].reciprocal.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].reciprocal.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -25297,16 +25133,7 @@ design: (work@int_execute_stage)
   |vpiFullName:work@int_execute_stage.lane_alu_gen[1].shift_in_sign
   |vpiVisibility:1
 \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiParent:
-  \_logic_var: (work@int_execute_stage.lane_alu_gen[1].rshift), line:116:22, endln:116:28
   |vpiName:scalar_t
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].rshift.scalar_t)
-    |vpiParent:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].rshift.scalar_t
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
   |vpiRange:
   \_range: , line:50:14, endln:50:20
     |vpiParent:
@@ -25327,19 +25154,6 @@ design: (work@int_execute_stage)
       |vpiSize:64
       |UINT:0
       |vpiConstType:9
-\_logic_var: (work@int_execute_stage.lane_alu_gen[1].rshift), line:116:22, endln:116:28
-  |vpiParent:
-  \_gen_scope: (work@int_execute_stage.lane_alu_gen[1]), line:100:9, endln:274:12
-  |vpiTypespec:
-  \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].rshift)
-    |vpiParent:
-    \_logic_var: (work@int_execute_stage.lane_alu_gen[1].rshift), line:116:22, endln:116:28
-    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].rshift
-    |vpiActual:
-    \_logic_typespec: (scalar_t), line:50:9, endln:50:20
-  |vpiName:rshift
-  |vpiFullName:work@int_execute_stage.lane_alu_gen[1].rshift
-  |vpiVisibility:1
 \_logic_typespec: , line:54:39, endln:54:39
 \_logic_typespec: , line:55:39, endln:55:39
 \_unsupported_typespec: (vector_mask_t), line:60:11, endln:60:24
@@ -25520,10 +25334,34 @@ design: (work@int_execute_stage)
   |vpiFullName:work@int_execute_stage.lane_alu_gen[0]
   |vpiVariables:
   \_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_operand1), line:101:22, endln:101:35
+    |vpiParent:
+    \_gen_scope: (work@int_execute_stage.lane_alu_gen[0]), line:100:9, endln:274:12
+    |vpiTypespec:
+    \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].lane_operand1)
+      |vpiParent:
+      \_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_operand1), line:101:22, endln:101:35
+      |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_operand1
+      |vpiActual:
+      \_logic_typespec: (scalar_t), line:50:9, endln:50:20
+    |vpiName:lane_operand1
+    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_operand1
+    |vpiVisibility:1
   |vpiVariables:
   \_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_operand2), line:102:22, endln:102:35
   |vpiVariables:
   \_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_result), line:103:22, endln:103:33
+    |vpiParent:
+    \_gen_scope: (work@int_execute_stage.lane_alu_gen[0]), line:100:9, endln:274:12
+    |vpiTypespec:
+    \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].lane_result)
+      |vpiParent:
+      \_logic_var: (work@int_execute_stage.lane_alu_gen[0].lane_result), line:103:22, endln:103:33
+      |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_result
+      |vpiActual:
+      \_logic_typespec: (scalar_t), line:50:9, endln:50:20
+    |vpiName:lane_result
+    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].lane_result
+    |vpiVisibility:1
   |vpiVariables:
   \_logic_var: (work@int_execute_stage.lane_alu_gen[0].difference), line:104:22, endln:104:32
   |vpiVariables:
@@ -25548,6 +25386,18 @@ design: (work@int_execute_stage)
   \_logic_var: (work@int_execute_stage.lane_alu_gen[0].shift_in_sign), line:115:19, endln:115:32
   |vpiVariables:
   \_logic_var: (work@int_execute_stage.lane_alu_gen[0].rshift), line:116:22, endln:116:28
+    |vpiParent:
+    \_gen_scope: (work@int_execute_stage.lane_alu_gen[0]), line:100:9, endln:274:12
+    |vpiTypespec:
+    \_ref_typespec: (work@int_execute_stage.lane_alu_gen[0].rshift)
+      |vpiParent:
+      \_logic_var: (work@int_execute_stage.lane_alu_gen[0].rshift), line:116:22, endln:116:28
+      |vpiFullName:work@int_execute_stage.lane_alu_gen[0].rshift
+      |vpiActual:
+      \_logic_typespec: (scalar_t), line:50:9, endln:50:20
+    |vpiName:rshift
+    |vpiFullName:work@int_execute_stage.lane_alu_gen[0].rshift
+    |vpiVisibility:1
   |vpiParameter:
   \_parameter: (work@int_execute_stage.lane_alu_gen[0].lane), line:99:0
   |vpiNet:
@@ -27312,10 +27162,34 @@ design: (work@int_execute_stage)
   |vpiFullName:work@int_execute_stage.lane_alu_gen[1]
   |vpiVariables:
   \_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_operand1), line:101:22, endln:101:35
+    |vpiParent:
+    \_gen_scope: (work@int_execute_stage.lane_alu_gen[1]), line:100:9, endln:274:12
+    |vpiTypespec:
+    \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].lane_operand1)
+      |vpiParent:
+      \_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_operand1), line:101:22, endln:101:35
+      |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_operand1
+      |vpiActual:
+      \_logic_typespec: (scalar_t), line:50:9, endln:50:20
+    |vpiName:lane_operand1
+    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_operand1
+    |vpiVisibility:1
   |vpiVariables:
   \_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_operand2), line:102:22, endln:102:35
   |vpiVariables:
   \_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_result), line:103:22, endln:103:33
+    |vpiParent:
+    \_gen_scope: (work@int_execute_stage.lane_alu_gen[1]), line:100:9, endln:274:12
+    |vpiTypespec:
+    \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].lane_result)
+      |vpiParent:
+      \_logic_var: (work@int_execute_stage.lane_alu_gen[1].lane_result), line:103:22, endln:103:33
+      |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_result
+      |vpiActual:
+      \_logic_typespec: (scalar_t), line:50:9, endln:50:20
+    |vpiName:lane_result
+    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].lane_result
+    |vpiVisibility:1
   |vpiVariables:
   \_logic_var: (work@int_execute_stage.lane_alu_gen[1].difference), line:104:22, endln:104:32
   |vpiVariables:
@@ -27340,6 +27214,18 @@ design: (work@int_execute_stage)
   \_logic_var: (work@int_execute_stage.lane_alu_gen[1].shift_in_sign), line:115:19, endln:115:32
   |vpiVariables:
   \_logic_var: (work@int_execute_stage.lane_alu_gen[1].rshift), line:116:22, endln:116:28
+    |vpiParent:
+    \_gen_scope: (work@int_execute_stage.lane_alu_gen[1]), line:100:9, endln:274:12
+    |vpiTypespec:
+    \_ref_typespec: (work@int_execute_stage.lane_alu_gen[1].rshift)
+      |vpiParent:
+      \_logic_var: (work@int_execute_stage.lane_alu_gen[1].rshift), line:116:22, endln:116:28
+      |vpiFullName:work@int_execute_stage.lane_alu_gen[1].rshift
+      |vpiActual:
+      \_logic_typespec: (scalar_t), line:50:9, endln:50:20
+    |vpiName:rshift
+    |vpiFullName:work@int_execute_stage.lane_alu_gen[1].rshift
+    |vpiVisibility:1
   |vpiParameter:
   \_parameter: (work@int_execute_stage.lane_alu_gen[1].lane), line:99:0
   |vpiNet:
diff --git a/tests/HierPathLhs/HierPathLhs.log b/tests/HierPathLhs/HierPathLhs.log
index 06b485c889..fe94cb0fcf 100644
--- a/tests/HierPathLhs/HierPathLhs.log
+++ b/tests/HierPathLhs/HierPathLhs.log
@@ -187,6 +187,7 @@ ref_obj                                               12
 ref_typespec                                           9
 ref_var                                                1
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 unsupported_typespec                                   1
 === UHDM Object Stats End ===
@@ -215,6 +216,7 @@ ref_obj                                               15
 ref_typespec                                          10
 ref_var                                                1
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 unsupported_typespec                                   1
 === UHDM Object Stats End ===
@@ -525,16 +527,61 @@ design: (work@alert_handler_reg_wrap)
   \_packed_array_var: (work@top.a), line:13:23, endln:13:24
     |vpiParent:
     \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10
-    |vpiTypespec:
-    \_ref_typespec: (work@top.a)
-      |vpiParent:
-      \_packed_array_var: (work@top.a), line:13:23, endln:13:24
-      |vpiFullName:work@top.a
-      |vpiActual:
-      \_packed_array_typespec: , line:13:3, endln:13:22
     |vpiName:a
     |vpiFullName:work@top.a
     |vpiVisibility:1
+    |vpiRange:
+    \_range: , line:13:12, endln:13:17
+      |vpiParent:
+      \_packed_array_var: (work@top.a), line:13:23, endln:13:24
+      |vpiLeftRange:
+      \_constant: , line:13:13, endln:13:14
+        |vpiParent:
+        \_range: , line:13:12, endln:13:17
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:13:15, endln:13:16
+        |vpiParent:
+        \_range: , line:13:12, endln:13:17
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiRange:
+    \_range: , line:13:17, endln:13:22
+      |vpiParent:
+      \_packed_array_var: (work@top.a), line:13:23, endln:13:24
+      |vpiLeftRange:
+      \_constant: , line:13:18, endln:13:19
+        |vpiParent:
+        \_range: , line:13:17, endln:13:22
+        |vpiDecompile:2
+        |vpiSize:64
+        |UINT:2
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:13:20, endln:13:21
+        |vpiParent:
+        \_range: , line:13:17, endln:13:22
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiElement:
+    \_struct_var: (work@top.a)
+      |vpiParent:
+      \_packed_array_var: (work@top.a), line:13:23, endln:13:24
+      |vpiTypespec:
+      \_ref_typespec: (work@top.a)
+        |vpiParent:
+        \_struct_var: (work@top.a)
+        |vpiFullName:work@top.a
+        |vpiActual:
+        \_struct_typespec: (struct_t), line:9:11, endln:11:4
+      |vpiFullName:work@top.a
   |vpiTypedef:
   \_struct_typespec: (struct_t), line:9:11, endln:11:4
   |vpiDefName:work@top
@@ -607,56 +654,6 @@ design: (work@alert_handler_reg_wrap)
   |vpiParent:
   \_typespec_member: (x), line:10:9, endln:10:10
   |vpiSigned:1
-\_packed_array_typespec: , line:13:3, endln:13:22
-  |vpiParent:
-  \_packed_array_var: (work@top.a), line:13:23, endln:13:24
-  |vpiRange:
-  \_range: , line:13:12, endln:13:17
-    |vpiParent:
-    \_packed_array_typespec: , line:13:3, endln:13:22
-    |vpiLeftRange:
-    \_constant: , line:13:13, endln:13:14
-      |vpiParent:
-      \_range: , line:13:12, endln:13:17
-      |vpiDecompile:1
-      |vpiSize:64
-      |UINT:1
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:13:15, endln:13:16
-      |vpiParent:
-      \_range: , line:13:12, endln:13:17
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiRange:
-  \_range: , line:13:17, endln:13:22
-    |vpiParent:
-    \_packed_array_typespec: , line:13:3, endln:13:22
-    |vpiLeftRange:
-    \_constant: , line:13:18, endln:13:19
-      |vpiParent:
-      \_range: , line:13:17, endln:13:22
-      |vpiDecompile:2
-      |vpiSize:64
-      |UINT:2
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:13:20, endln:13:21
-      |vpiParent:
-      \_range: , line:13:17, endln:13:22
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiElemTypespec:
-  \_ref_typespec: (work@top.a)
-    |vpiParent:
-    \_packed_array_typespec: , line:13:3, endln:13:22
-    |vpiFullName:work@top.a
-    |vpiActual:
-    \_struct_typespec: (struct_t), line:9:11, endln:11:4
 \_packed_array_typespec: , line:13:3, endln:13:17
   |vpiRange:
   \_range: , line:13:12, endln:13:17
diff --git a/tests/LogicTypedef/LogicTypedef.log b/tests/LogicTypedef/LogicTypedef.log
index 509af60745..d2fc5fa4ee 100644
--- a/tests/LogicTypedef/LogicTypedef.log
+++ b/tests/LogicTypedef/LogicTypedef.log
@@ -11,30 +11,30 @@
 [NTE:EL0511] Nb leaf instances: 1.
 [INF:UH0706] Creating UHDM Model...
 === UHDM Object Stats Begin (Non-Elaborated Model) ===
-bit_typespec                                           3
+bit_typespec                                           4
 bit_var                                                1
-constant                                              24
+constant                                              28
 design                                                 1
 logic_net                                              4
-logic_typespec                                         6
+logic_typespec                                         7
 logic_var                                              1
-module_inst                                            2
+module_inst                                            3
 packed_array_typespec                                  3
-range                                                 12
+range                                                 14
 ref_typespec                                          12
 === UHDM Object Stats End ===
 [INF:UH0707] Elaborating UHDM...
 === UHDM Object Stats Begin (Elaborated Model) ===
-bit_typespec                                           3
+bit_typespec                                           4
 bit_var                                                1
-constant                                              24
+constant                                              28
 design                                                 1
 logic_net                                              4
-logic_typespec                                         6
+logic_typespec                                         7
 logic_var                                              1
-module_inst                                            2
+module_inst                                            3
 packed_array_typespec                                  3
-range                                                 12
+range                                                 14
 ref_typespec                                          12
 === UHDM Object Stats End ===
 [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/LogicTypedef/slpp_unit/surelog.uhdm ...
@@ -229,16 +229,7 @@ design: (work@test)
   |vpiTopModule:1
 \_weaklyReferenced:
 \_logic_typespec: (log_two_bits), line:2:13, endln:2:24
-  |vpiParent:
-  \_logic_var: (work@test.logn), line:3:18, endln:3:22
   |vpiName:log_two_bits
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@test.logn.log_two_bits)
-    |vpiParent:
-    \_logic_typespec: (log_two_bits), line:2:13, endln:2:24
-    |vpiFullName:work@test.logn.log_two_bits
-    |vpiActual:
-    \_logic_typespec: (log_two_bits), line:2:13, endln:2:24
   |vpiRange:
   \_range: , line:2:19, endln:2:24
     |vpiParent:
@@ -260,16 +251,7 @@ design: (work@test)
       |UINT:0
       |vpiConstType:9
 \_bit_typespec: (bit_two_bits), line:8:13, endln:8:22
-  |vpiParent:
-  \_bit_var: (work@test.bitn), line:9:18, endln:9:22
   |vpiName:bit_two_bits
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@test.bitn.bit_two_bits)
-    |vpiParent:
-    \_bit_typespec: (bit_two_bits), line:8:13, endln:8:22
-    |vpiFullName:work@test.bitn.bit_two_bits
-    |vpiActual:
-    \_bit_typespec: (bit_two_bits), line:8:13, endln:8:22
   |vpiRange:
   \_range: , line:8:17, endln:8:22
     |vpiParent:
diff --git a/tests/LogicTypespec/LogicTypespec.log b/tests/LogicTypespec/LogicTypespec.log
index 61fc98cec1..acd0ff34bb 100644
--- a/tests/LogicTypespec/LogicTypespec.log
+++ b/tests/LogicTypespec/LogicTypespec.log
@@ -88,28 +88,28 @@ AST_DEBUG_END
 [NTE:EL0511] Nb leaf instances: 1.
 [INF:UH0706] Creating UHDM Model...
 === UHDM Object Stats Begin (Non-Elaborated Model) ===
-constant                                              20
+constant                                              22
 design                                                 1
 logic_net                                              1
-logic_typespec                                         2
+logic_typespec                                         3
 logic_var                                              1
 module_inst                                            4
 package                                                2
 packed_array_typespec                                  2
-range                                                 10
+range                                                 11
 ref_typespec                                           2
 === UHDM Object Stats End ===
 [INF:UH0707] Elaborating UHDM...
 === UHDM Object Stats Begin (Elaborated Model) ===
-constant                                              20
+constant                                              22
 design                                                 1
 logic_net                                              1
-logic_typespec                                         2
+logic_typespec                                         3
 logic_var                                              1
 module_inst                                            4
 package                                                2
 packed_array_typespec                                  2
-range                                                 10
+range                                                 11
 ref_typespec                                           2
 === UHDM Object Stats End ===
 [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/LogicTypespec/slpp_all/surelog.uhdm ...
@@ -224,13 +224,38 @@ design: (work@logic_typespec)
       \_logic_var: (work@logic_typespec.my_instance), line:7:50, endln:7:61
       |vpiFullName:work@logic_typespec.my_instance
       |vpiActual:
-      \_logic_typespec: (my_package::typedef_logic_typespec), line:2:9, endln:7:44
+      \_logic_typespec: (typedef_logic_typespec), line:2:9, endln:2:20
     |vpiName:my_instance
     |vpiFullName:work@logic_typespec.my_instance
     |vpiVisibility:1
   |vpiDefName:work@logic_typespec
   |vpiTop:1
   |vpiTopModule:1
+\_weaklyReferenced:
+\_logic_typespec: (typedef_logic_typespec), line:2:9, endln:2:20
+  |vpiName:typedef_logic_typespec
+  |vpiInstance:
+  \_package: my_package (my_package::), file:${SURELOG_DIR}/tests/LogicTypespec/dut.sv, line:1:1, endln:3:23
+  |vpiRange:
+  \_range: , line:2:15, endln:2:20
+    |vpiParent:
+    \_logic_typespec: (typedef_logic_typespec), line:2:9, endln:2:20
+    |vpiLeftRange:
+    \_constant: , line:2:16, endln:2:17
+      |vpiParent:
+      \_range: , line:2:15, endln:2:20
+      |vpiDecompile:1
+      |vpiSize:64
+      |UINT:1
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:2:18, endln:2:19
+      |vpiParent:
+      \_range: , line:2:15, endln:2:20
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
 ===================
 [  FATAL] : 0
 [ SYNTAX] : 0
diff --git a/tests/LowMemPkg/LowMemPkg.log b/tests/LowMemPkg/LowMemPkg.log
index e4c0c4f17f..0fbccbcf15 100644
--- a/tests/LowMemPkg/LowMemPkg.log
+++ b/tests/LowMemPkg/LowMemPkg.log
@@ -192,7 +192,7 @@ design: (work@top)
       \_logic_var: (work@top.a), line:5:13, endln:5:14
       |vpiFullName:work@top.a
       |vpiActual:
-      \_logic_typespec: (my_logic), line:20:9, endln:20:14
+      \_logic_typespec: (wddr_pkg::my_logic), line:20:9, endln:20:14
     |vpiName:a
     |vpiFullName:work@top.a
     |vpiVisibility:1
@@ -216,19 +216,6 @@ design: (work@top)
   |vpiTop:1
   |vpiTopModule:1
 \_weaklyReferenced:
-\_logic_typespec: (my_logic), line:20:9, endln:20:14
-  |vpiParent:
-  \_logic_var: (work@top.a), line:5:13, endln:5:14
-  |vpiName:my_logic
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@top.a.my_logic)
-    |vpiParent:
-    \_logic_typespec: (my_logic), line:20:9, endln:20:14
-    |vpiFullName:work@top.a.my_logic
-    |vpiActual:
-    \_logic_typespec: (wddr_pkg::my_logic), line:20:9, endln:20:14
-  |vpiInstance:
-  \_package: wddr_pkg (wddr_pkg::), file:${SURELOG_DIR}/tests/LowMemPkg/wddr_pkg.sv, line:19:1, endln:22:11
 \_logic_typespec: , line:6:4, endln:6:9
   |vpiParent:
   \_logic_var: (work@top.b), line:6:10, endln:6:11
diff --git a/tests/MultiIndexBind/MultiIndexBind.log b/tests/MultiIndexBind/MultiIndexBind.log
index 954716dab6..4309470a6b 100644
--- a/tests/MultiIndexBind/MultiIndexBind.log
+++ b/tests/MultiIndexBind/MultiIndexBind.log
@@ -192,6 +192,7 @@ range                                                  7
 ref_obj                                                5
 ref_typespec                                           8
 struct_typespec                                        2
+struct_var                                             1
 typespec_member                                        3
 union_typespec                                         1
 === UHDM Object Stats End ===
@@ -213,6 +214,7 @@ range                                                  7
 ref_obj                                               10
 ref_typespec                                           8
 struct_typespec                                        2
+struct_var                                             1
 typespec_member                                        3
 union_typespec                                         1
 === UHDM Object Stats End ===
@@ -421,16 +423,61 @@ design: (work@PreDecodeStage)
   \_packed_array_var: (work@PreDecodeStage.microOps), line:26:19, endln:26:27
     |vpiParent:
     \_module_inst: work@PreDecodeStage (work@PreDecodeStage), file:${SURELOG_DIR}/tests/MultiIndexBind/dut.sv, line:1:1, endln:30:10
-    |vpiTypespec:
-    \_ref_typespec: (work@PreDecodeStage.microOps)
-      |vpiParent:
-      \_packed_array_var: (work@PreDecodeStage.microOps), line:26:19, endln:26:27
-      |vpiFullName:work@PreDecodeStage.microOps
-      |vpiActual:
-      \_packed_array_typespec: , line:26:1, endln:26:18
     |vpiName:microOps
     |vpiFullName:work@PreDecodeStage.microOps
     |vpiVisibility:1
+    |vpiRange:
+    \_range: , line:26:8, endln:26:13
+      |vpiParent:
+      \_packed_array_var: (work@PreDecodeStage.microOps), line:26:19, endln:26:27
+      |vpiLeftRange:
+      \_constant: , line:26:9, endln:26:10
+        |vpiParent:
+        \_range: , line:26:8, endln:26:13
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:26:11, endln:26:12
+        |vpiParent:
+        \_range: , line:26:8, endln:26:13
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiRange:
+    \_range: , line:26:13, endln:26:18
+      |vpiParent:
+      \_packed_array_var: (work@PreDecodeStage.microOps), line:26:19, endln:26:27
+      |vpiLeftRange:
+      \_constant: , line:26:14, endln:26:15
+        |vpiParent:
+        \_range: , line:26:13, endln:26:18
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:26:16, endln:26:17
+        |vpiParent:
+        \_range: , line:26:13, endln:26:18
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiElement:
+    \_struct_var: (work@PreDecodeStage.microOps)
+      |vpiParent:
+      \_packed_array_var: (work@PreDecodeStage.microOps), line:26:19, endln:26:27
+      |vpiTypespec:
+      \_ref_typespec: (work@PreDecodeStage.microOps)
+        |vpiParent:
+        \_struct_var: (work@PreDecodeStage.microOps)
+        |vpiFullName:work@PreDecodeStage.microOps
+        |vpiActual:
+        \_struct_typespec: (OpInfo), line:19:9, endln:22:2
+      |vpiFullName:work@PreDecodeStage.microOps
   |vpiTypedef:
   \_enum_typespec: (IntALU_Code), line:4:1, endln:7:15
   |vpiTypedef:
@@ -526,56 +573,6 @@ design: (work@PreDecodeStage)
       |vpiSize:64
       |UINT:0
       |vpiConstType:9
-\_packed_array_typespec: , line:26:1, endln:26:18
-  |vpiParent:
-  \_packed_array_var: (work@PreDecodeStage.microOps), line:26:19, endln:26:27
-  |vpiRange:
-  \_range: , line:26:8, endln:26:13
-    |vpiParent:
-    \_packed_array_typespec: , line:26:1, endln:26:18
-    |vpiLeftRange:
-    \_constant: , line:26:9, endln:26:10
-      |vpiParent:
-      \_range: , line:26:8, endln:26:13
-      |vpiDecompile:1
-      |vpiSize:64
-      |UINT:1
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:26:11, endln:26:12
-      |vpiParent:
-      \_range: , line:26:8, endln:26:13
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiRange:
-  \_range: , line:26:13, endln:26:18
-    |vpiParent:
-    \_packed_array_typespec: , line:26:1, endln:26:18
-    |vpiLeftRange:
-    \_constant: , line:26:14, endln:26:15
-      |vpiParent:
-      \_range: , line:26:13, endln:26:18
-      |vpiDecompile:1
-      |vpiSize:64
-      |UINT:1
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:26:16, endln:26:17
-      |vpiParent:
-      \_range: , line:26:13, endln:26:18
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiElemTypespec:
-  \_ref_typespec: (work@PreDecodeStage.microOps)
-    |vpiParent:
-    \_packed_array_typespec: , line:26:1, endln:26:18
-    |vpiFullName:work@PreDecodeStage.microOps
-    |vpiActual:
-    \_struct_typespec: (OpInfo), line:19:9, endln:22:2
 \_packed_array_typespec: , line:26:1, endln:26:13
   |vpiRange:
   \_range: , line:26:8, endln:26:13
diff --git a/tests/NetLValue/NetLValue.log b/tests/NetLValue/NetLValue.log
index e31fdd0126..5fb0779de7 100644
--- a/tests/NetLValue/NetLValue.log
+++ b/tests/NetLValue/NetLValue.log
@@ -151,6 +151,7 @@ range                                                  3
 ref_obj                                                3
 ref_typespec                                           7
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 === UHDM Object Stats End ===
 [INF:UH0707] Elaborating UHDM...
@@ -172,6 +173,7 @@ range                                                  3
 ref_obj                                                6
 ref_typespec                                           7
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 === UHDM Object Stats End ===
 [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/NetLValue/slpp_all/surelog.uhdm ...
@@ -327,16 +329,41 @@ design: (work@t)
   \_packed_array_var: (work@t.s), line:3:11, endln:3:12
     |vpiParent:
     \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10
-    |vpiTypespec:
-    \_ref_typespec: (work@t.s)
-      |vpiParent:
-      \_packed_array_var: (work@t.s), line:3:11, endln:3:12
-      |vpiFullName:work@t.s
-      |vpiActual:
-      \_packed_array_typespec: , line:3:4, endln:3:10
     |vpiName:s
     |vpiFullName:work@t.s
     |vpiVisibility:1
+    |vpiRange:
+    \_range: , line:3:5, endln:3:10
+      |vpiParent:
+      \_packed_array_var: (work@t.s), line:3:11, endln:3:12
+      |vpiLeftRange:
+      \_constant: , line:3:6, endln:3:7
+        |vpiParent:
+        \_range: , line:3:5, endln:3:10
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:3:8, endln:3:9
+        |vpiParent:
+        \_range: , line:3:5, endln:3:10
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiElement:
+    \_struct_var: (work@t.s)
+      |vpiParent:
+      \_packed_array_var: (work@t.s), line:3:11, endln:3:12
+      |vpiTypespec:
+      \_ref_typespec: (work@t.s)
+        |vpiParent:
+        \_struct_var: (work@t.s)
+        |vpiFullName:work@t.s
+        |vpiActual:
+        \_struct_typespec: (S), line:2:12, endln:2:29
+      |vpiFullName:work@t.s
   |vpiVariables:
   \_int_var: (work@t.y), line:4:8, endln:4:9
     |vpiParent:
@@ -439,36 +466,6 @@ design: (work@t)
   |vpiParent:
   \_typespec_member: (x), line:2:25, endln:2:26
   |vpiSigned:1
-\_packed_array_typespec: , line:3:4, endln:3:10
-  |vpiParent:
-  \_packed_array_var: (work@t.s), line:3:11, endln:3:12
-  |vpiRange:
-  \_range: , line:3:5, endln:3:10
-    |vpiParent:
-    \_packed_array_typespec: , line:3:4, endln:3:10
-    |vpiLeftRange:
-    \_constant: , line:3:6, endln:3:7
-      |vpiParent:
-      \_range: , line:3:5, endln:3:10
-      |vpiDecompile:1
-      |vpiSize:64
-      |UINT:1
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:3:8, endln:3:9
-      |vpiParent:
-      \_range: , line:3:5, endln:3:10
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiElemTypespec:
-  \_ref_typespec: (work@t.s)
-    |vpiParent:
-    \_packed_array_typespec: , line:3:4, endln:3:10
-    |vpiFullName:work@t.s
-    |vpiActual:
-    \_struct_typespec: (S), line:2:12, endln:2:29
 \_int_typespec: , line:4:4, endln:4:7
   |vpiParent:
   \_int_var: (work@t.y), line:4:8, endln:4:9
diff --git a/tests/NetType/NetType.log b/tests/NetType/NetType.log
index 93252d8d03..afd2fcab4c 100644
--- a/tests/NetType/NetType.log
+++ b/tests/NetType/NetType.log
@@ -725,17 +725,6 @@ design: (work@dut)
 \_bit_typespec: , line:3:20, endln:3:23
 \_real_typespec: , line:41:20, endln:41:24
 \_real_typespec: , line:41:44, endln:41:48
-\_real_typespec: (my_real), line:9:9, endln:9:13
-  |vpiParent:
-  \_real_var: (work@dut.my_real_net), line:13:13, endln:13:24
-  |vpiName:my_real
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@dut.my_real_net.my_real)
-    |vpiParent:
-    \_real_typespec: (my_real), line:9:9, endln:9:13
-    |vpiFullName:work@dut.my_real_net.my_real
-    |vpiActual:
-    \_real_typespec: (my_real), line:9:9, endln:9:13
 ===================
 [  FATAL] : 0
 [ SYNTAX] : 0
@@ -751,7 +740,6 @@ design: (work@dut)
 [LINT]: ${SURELOG_DIR}/tests/NetType/dut.sv:41:20: Non synthesizable construct,
 [LINT]: ${SURELOG_DIR}/tests/NetType/dut.sv:41:20: Non synthesizable construct,
 [LINT]: ${SURELOG_DIR}/tests/NetType/dut.sv:41:44: Non synthesizable construct,
-[LINT]: ${SURELOG_DIR}/tests/NetType/dut.sv:9:9: Non synthesizable construct, my_real
 [LINT]: ${SURELOG_DIR}/tests/NetType/dut.sv:13:13: Non synthesizable construct, my_real_net
 [LINT]: ${SURELOG_DIR}/tests/NetType/dut.sv:18:9: Unsupported typespec, myalias
 [LINT]:   \_ :0:0:
diff --git a/tests/PackageNet/PackageNet.log b/tests/PackageNet/PackageNet.log
index 8f0a8d6edc..c2e346dc94 100644
--- a/tests/PackageNet/PackageNet.log
+++ b/tests/PackageNet/PackageNet.log
@@ -126,13 +126,13 @@ AST_DEBUG_END
 === UHDM Object Stats Begin (Non-Elaborated Model) ===
 assignment                                             1
 begin                                                  1
-constant                                              39
+constant                                              41
 design                                                 1
 import_typespec                                        1
 initial                                                1
 int_typespec                                          14
 logic_net                                              5
-logic_typespec                                         8
+logic_typespec                                         9
 logic_var                                              1
 module_inst                                            4
 operation                                              1
@@ -140,7 +140,7 @@ package                                                2
 packed_array_typespec                                  2
 param_assign                                          12
 parameter                                             14
-range                                                 10
+range                                                 11
 ref_obj                                                1
 ref_typespec                                          36
 === UHDM Object Stats End ===
@@ -148,13 +148,13 @@ ref_typespec                                          36
 === UHDM Object Stats Begin (Elaborated Model) ===
 assignment                                             2
 begin                                                  2
-constant                                              39
+constant                                              41
 design                                                 1
 import_typespec                                        1
 initial                                                2
 int_typespec                                          14
 logic_net                                              5
-logic_typespec                                         8
+logic_typespec                                         9
 logic_var                                              1
 module_inst                                            4
 operation                                              2
@@ -162,7 +162,7 @@ package                                                2
 packed_array_typespec                                  2
 param_assign                                          12
 parameter                                             14
-range                                                 10
+range                                                 11
 ref_obj                                                2
 ref_typespec                                          36
 === UHDM Object Stats End ===
@@ -753,16 +753,7 @@ design: (work@test)
   |vpiParent:
   \_ref_typespec: (work@test)
 \_logic_typespec: (word), line:6:9, endln:6:20
-  |vpiParent:
-  \_logic_var: (work@test.v), line:8:6, endln:8:7
   |vpiName:word
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@test.v.word)
-    |vpiParent:
-    \_logic_typespec: (word), line:6:9, endln:6:20
-    |vpiFullName:work@test.v.word
-    |vpiActual:
-    \_logic_typespec: (my_package1::word), line:6:9, endln:6:20
   |vpiInstance:
   \_package: my_package1 (my_package1::), file:${SURELOG_DIR}/tests/PackageNet/dut.sv, line:1:1, endln:10:11
   |vpiRange:
diff --git a/tests/PackedArrayAssign/PackedArrayAssign.log b/tests/PackedArrayAssign/PackedArrayAssign.log
index 52bf61d1ff..33dd638fe9 100644
--- a/tests/PackedArrayAssign/PackedArrayAssign.log
+++ b/tests/PackedArrayAssign/PackedArrayAssign.log
@@ -142,6 +142,7 @@ range                                                  8
 ref_obj                                                3
 ref_typespec                                           8
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 === UHDM Object Stats End ===
 [INF:UH0707] Elaborating UHDM...
@@ -161,6 +162,7 @@ range                                                  8
 ref_obj                                                5
 ref_typespec                                           9
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 === UHDM Object Stats End ===
 [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/PackedArrayAssign/slpp_all/surelog.uhdm ...
@@ -276,20 +278,13 @@ design: (work@top)
   \_packed_array_var: (work@top.a), line:6:23, endln:6:43
     |vpiParent:
     \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayAssign/dut.sv, line:1:1, endln:8:10
-    |vpiTypespec:
-    \_ref_typespec: (work@top.a)
-      |vpiParent:
-      \_packed_array_var: (work@top.a), line:6:23, endln:6:43
-      |vpiFullName:work@top.a
-      |vpiActual:
-      \_packed_array_typespec: , line:6:4, endln:6:22
     |vpiName:a
     |vpiFullName:work@top.a
     |vpiVisibility:1
     |vpiExpr:
     \_operation: , line:6:27, endln:6:43
       |vpiParent:
-      \_packed_array_var: (work@top.a), line:6:23, endln:6:43
+      \_struct_var: (work@top.a)
       |vpiOpType:75
       |vpiOperand:
       \_constant: , line:6:29, endln:6:35
@@ -303,6 +298,40 @@ design: (work@top)
         |vpiSize:10
         |DEC:0
         |vpiConstType:1
+    |vpiRange:
+    \_range: , line:6:17, endln:6:22
+      |vpiParent:
+      \_packed_array_var: (work@top.a), line:6:23, endln:6:43
+      |vpiLeftRange:
+      \_constant: , line:6:18, endln:6:19
+        |vpiParent:
+        \_range: , line:6:17, endln:6:22
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:6:20, endln:6:21
+        |vpiParent:
+        \_range: , line:6:17, endln:6:22
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiElement:
+    \_struct_var: (work@top.a)
+      |vpiParent:
+      \_packed_array_var: (work@top.a), line:6:23, endln:6:43
+      |vpiTypespec:
+      \_ref_typespec: (work@top.a)
+        |vpiParent:
+        \_struct_var: (work@top.a)
+        |vpiFullName:work@top.a
+        |vpiActual:
+        \_struct_typespec: (filter_ctl_t), line:2:12, endln:4:5
+      |vpiFullName:work@top.a
+      |vpiExpr:
+      \_operation: , line:6:27, endln:6:43
   |vpiTypedef:
   \_struct_typespec: (filter_ctl_t), line:2:12, endln:4:5
   |vpiDefName:work@top
@@ -433,36 +462,6 @@ design: (work@top)
       |vpiSize:64
       |UINT:0
       |vpiConstType:9
-\_packed_array_typespec: , line:6:4, endln:6:22
-  |vpiParent:
-  \_packed_array_var: (work@top.a), line:6:23, endln:6:43
-  |vpiRange:
-  \_range: , line:6:17, endln:6:22
-    |vpiParent:
-    \_packed_array_typespec: , line:6:4, endln:6:22
-    |vpiLeftRange:
-    \_constant: , line:6:18, endln:6:19
-      |vpiParent:
-      \_range: , line:6:17, endln:6:22
-      |vpiDecompile:1
-      |vpiSize:64
-      |UINT:1
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:6:20, endln:6:21
-      |vpiParent:
-      \_range: , line:6:17, endln:6:22
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiElemTypespec:
-  \_ref_typespec: (work@top.a)
-    |vpiParent:
-    \_packed_array_typespec: , line:6:4, endln:6:22
-    |vpiFullName:work@top.a
-    |vpiActual:
-    \_struct_typespec: (filter_ctl_t), line:2:12, endln:4:5
 \_logic_typespec: , line:1:19, endln:1:30
   |vpiRange:
   \_range: , line:1:25, endln:1:30
diff --git a/tests/PackedArrayStruct/PackedArrayStruct.log b/tests/PackedArrayStruct/PackedArrayStruct.log
index 917c05b1f0..39c9cb00b0 100644
--- a/tests/PackedArrayStruct/PackedArrayStruct.log
+++ b/tests/PackedArrayStruct/PackedArrayStruct.log
@@ -108,12 +108,12 @@ logic_net                                              3
 logic_typespec                                         4
 module_inst                                            4
 packed_array_typespec                                  1
-packed_array_var                                       1
 port                                                   2
 range                                                  5
 ref_obj                                                4
 ref_typespec                                           7
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 === UHDM Object Stats End ===
 [INF:UH0707] Elaborating UHDM...
@@ -125,12 +125,12 @@ logic_net                                              3
 logic_typespec                                         4
 module_inst                                            4
 packed_array_typespec                                  1
-packed_array_var                                       1
 port                                                   3
 range                                                  5
 ref_obj                                                7
 ref_typespec                                           8
 struct_typespec                                        1
+struct_var                                             1
 typespec_member                                        1
 === UHDM Object Stats End ===
 [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/PackedArrayStruct/slpp_all/surelog.uhdm ...
@@ -246,13 +246,13 @@ design: (work@top)
 \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10
   |vpiName:work@top
   |vpiVariables:
-  \_packed_array_var: (work@top.a), line:5:19, endln:5:20
+  \_struct_var: (work@top.a), line:5:19, endln:5:20
     |vpiParent:
     \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedArrayStruct/dut.sv, line:1:1, endln:7:10
     |vpiTypespec:
     \_ref_typespec: (work@top.a)
       |vpiParent:
-      \_packed_array_var: (work@top.a), line:5:19, endln:5:20
+      \_struct_var: (work@top.a), line:5:19, endln:5:20
       |vpiFullName:work@top.a
       |vpiActual:
       \_packed_array_typespec: (struct_array_t), line:2:12, endln:4:12
@@ -262,7 +262,7 @@ design: (work@top)
     |vpiExpr:
     \_constant: , line:5:23, endln:5:25
       |vpiParent:
-      \_packed_array_var: (work@top.a), line:5:19, endln:5:20
+      \_struct_var: (work@top.a), line:5:19, endln:5:20
       |vpiDecompile:4294967295
       |vpiSize:32
       |UINT:4294967295
@@ -320,7 +320,7 @@ design: (work@top)
       |vpiName:a
       |vpiFullName:work@top.a
       |vpiActual:
-      \_packed_array_var: (work@top.a), line:5:19, endln:5:20
+      \_struct_var: (work@top.a), line:5:19, endln:5:20
     |vpiLhs:
     \_ref_obj: (work@top.o), line:6:11, endln:6:12
       |vpiParent:
diff --git a/tests/PackedEnumPort/PackedEnumPort.log b/tests/PackedEnumPort/PackedEnumPort.log
index 8268a3e9e4..3ff8b27a15 100644
--- a/tests/PackedEnumPort/PackedEnumPort.log
+++ b/tests/PackedEnumPort/PackedEnumPort.log
@@ -151,6 +151,7 @@ constant                                              18
 design                                                 1
 enum_const                                             3
 enum_typespec                                          3
+enum_var                                               1
 int_typespec                                           6
 int_var                                                2
 logic_net                                              5
@@ -172,6 +173,7 @@ constant                                              18
 design                                                 1
 enum_const                                             3
 enum_typespec                                          3
+enum_var                                               1
 int_typespec                                           6
 int_var                                                2
 logic_net                                              5
@@ -457,16 +459,42 @@ design: (work@top)
   \_packed_array_var: (work@top.lc_clk_byp_ack), line:25:30, endln:25:44
     |vpiParent:
     \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16
-    |vpiTypespec:
-    \_ref_typespec: (work@top.lc_clk_byp_ack)
-      |vpiParent:
-      \_packed_array_var: (work@top.lc_clk_byp_ack), line:25:30, endln:25:44
-      |vpiFullName:work@top.lc_clk_byp_ack
-      |vpiActual:
-      \_packed_array_typespec: 
     |vpiName:lc_clk_byp_ack
     |vpiFullName:work@top.lc_clk_byp_ack
     |vpiVisibility:1
+    |vpiRange:
+    \_range: , line:25:24, endln:25:29
+      |vpiParent:
+      \_packed_array_var: (work@top.lc_clk_byp_ack), line:25:30, endln:25:44
+      |vpiLeftRange:
+      \_constant: , line:25:25, endln:25:26
+        |vpiParent:
+        \_range: , line:25:24, endln:25:29
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:25:27, endln:25:28
+        |vpiParent:
+        \_range: , line:25:24, endln:25:29
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiElement:
+    \_enum_var: (work@top.lc_clk_byp_ack.lc_clk_byp_ack)
+      |vpiParent:
+      \_packed_array_var: (work@top.lc_clk_byp_ack), line:25:30, endln:25:44
+      |vpiTypespec:
+      \_ref_typespec: (work@top.lc_clk_byp_ack.lc_clk_byp_ack)
+        |vpiParent:
+        \_enum_var: (work@top.lc_clk_byp_ack.lc_clk_byp_ack)
+        |vpiFullName:work@top.lc_clk_byp_ack.lc_clk_byp_ack
+        |vpiActual:
+        \_enum_typespec: (lc_ctrl_pkg::lc_tx_t), line:3:4, endln:5:14
+      |vpiName:lc_clk_byp_ack
+      |vpiFullName:work@top.lc_clk_byp_ack.lc_clk_byp_ack
   |vpiDefName:work@top
   |vpiTop:1
   |vpiTopModule:1
@@ -664,36 +692,6 @@ design: (work@top)
   |vpiParent:
   \_int_var: (work@top.p), line:24:37, endln:24:38
   |vpiSigned:1
-\_packed_array_typespec: 
-  |vpiParent:
-  \_packed_array_var: (work@top.lc_clk_byp_ack), line:25:30, endln:25:44
-  |vpiRange:
-  \_range: , line:25:24, endln:25:29
-    |vpiParent:
-    \_packed_array_typespec: 
-    |vpiLeftRange:
-    \_constant: , line:25:25, endln:25:26
-      |vpiParent:
-      \_range: , line:25:24, endln:25:29
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:25:27, endln:25:28
-      |vpiParent:
-      \_range: , line:25:24, endln:25:29
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiElemTypespec:
-  \_ref_typespec: (work@top.lc_clk_byp_ack)
-    |vpiParent:
-    \_packed_array_typespec: 
-    |vpiFullName:work@top.lc_clk_byp_ack
-    |vpiActual:
-    \_enum_typespec: (lc_ctrl_pkg::lc_tx_t), line:3:4, endln:5:14
 \_logic_typespec: , line:13:9, endln:13:14
 \_logic_typespec: , line:13:9, endln:13:14
   |vpiParent:
diff --git a/tests/ParamTypespec2/ParamTypespec2.log b/tests/ParamTypespec2/ParamTypespec2.log
index 1d0df25745..3042fb4f1c 100644
--- a/tests/ParamTypespec2/ParamTypespec2.log
+++ b/tests/ParamTypespec2/ParamTypespec2.log
@@ -211,6 +211,7 @@ ref_obj                                               14
 ref_typespec                                          81
 string_typespec                                       26
 struct_typespec                                       13
+struct_var                                             1
 tagged_pattern                                        26
 typespec_member                                       26
 === UHDM Object Stats End ===
@@ -238,6 +239,7 @@ ref_obj                                               20
 ref_typespec                                          86
 string_typespec                                       26
 struct_typespec                                       13
+struct_var                                             1
 tagged_pattern                                        26
 typespec_member                                       26
 === UHDM Object Stats End ===
@@ -773,16 +775,41 @@ design: (work@top)
     \_packed_array_var: (work@top.u_nmi_gen.a), line:15:25, endln:15:26
       |vpiParent:
       \_module_inst: work@nmi_gen (work@top.u_nmi_gen), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:22:4, endln:25:6
-      |vpiTypespec:
-      \_ref_typespec: (work@top.u_nmi_gen.a)
-        |vpiParent:
-        \_packed_array_var: (work@top.u_nmi_gen.a), line:15:25, endln:15:26
-        |vpiFullName:work@top.u_nmi_gen.a
-        |vpiActual:
-        \_packed_array_typespec: , line:15:10, endln:15:24
       |vpiName:a
       |vpiFullName:work@top.u_nmi_gen.a
       |vpiVisibility:1
+      |vpiRange:
+      \_range: , line:15:19, endln:15:24
+        |vpiParent:
+        \_packed_array_var: (work@top.u_nmi_gen.a), line:15:25, endln:15:26
+        |vpiLeftRange:
+        \_constant: , line:15:20, endln:15:21
+          |vpiParent:
+          \_range: , line:15:19, endln:15:24
+          |vpiDecompile:2
+          |vpiSize:64
+          |UINT:2
+          |vpiConstType:9
+        |vpiRightRange:
+        \_constant: , line:15:22, endln:15:23
+          |vpiParent:
+          \_range: , line:15:19, endln:15:24
+          |vpiDecompile:0
+          |vpiSize:64
+          |UINT:0
+          |vpiConstType:9
+      |vpiElement:
+      \_struct_var: (work@top.u_nmi_gen.a)
+        |vpiParent:
+        \_packed_array_var: (work@top.u_nmi_gen.a), line:15:25, endln:15:26
+        |vpiTypespec:
+        \_ref_typespec: (work@top.u_nmi_gen.a)
+          |vpiParent:
+          \_struct_var: (work@top.u_nmi_gen.a)
+          |vpiFullName:work@top.u_nmi_gen.a
+          |vpiActual:
+          \_struct_typespec: (prim_esc_pkg::esc_tx_t), line:2:11, endln:5:4
+        |vpiFullName:work@top.u_nmi_gen.a
     |vpiVariables:
     \_int_var: (work@top.u_nmi_gen.x), line:16:15, endln:16:16
       |vpiParent:
@@ -1286,36 +1313,6 @@ design: (work@top)
   \_ref_typespec: (work@top.u_nmi_gen.prim_esc_pkg::esc_tx_t.esc_n)
   |vpiInstance:
   \_package: prim_esc_pkg (prim_esc_pkg::), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:1:1, endln:10:26
-\_packed_array_typespec: , line:15:10, endln:15:24
-  |vpiParent:
-  \_packed_array_var: (work@top.u_nmi_gen.a), line:15:25, endln:15:26
-  |vpiRange:
-  \_range: , line:15:19, endln:15:24
-    |vpiParent:
-    \_packed_array_typespec: , line:15:10, endln:15:24
-    |vpiLeftRange:
-    \_constant: , line:15:20, endln:15:21
-      |vpiParent:
-      \_range: , line:15:19, endln:15:24
-      |vpiDecompile:2
-      |vpiSize:64
-      |UINT:2
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:15:22, endln:15:23
-      |vpiParent:
-      \_range: , line:15:19, endln:15:24
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiElemTypespec:
-  \_ref_typespec: (work@top.u_nmi_gen.a)
-    |vpiParent:
-    \_packed_array_typespec: , line:15:10, endln:15:24
-    |vpiFullName:work@top.u_nmi_gen.a
-    |vpiActual:
-    \_struct_typespec: (prim_esc_pkg::esc_tx_t), line:2:11, endln:5:4
 \_int_typespec: , line:16:11, endln:16:14
   |vpiSigned:1
 \_operation: , line:7:39, endln:8:54
diff --git a/tests/SelectSelect/SelectSelect.log b/tests/SelectSelect/SelectSelect.log
index 53e695f749..fee85380b5 100644
--- a/tests/SelectSelect/SelectSelect.log
+++ b/tests/SelectSelect/SelectSelect.log
@@ -404,6 +404,7 @@ range                                                 10
 ref_obj                                                1
 ref_typespec                                          20
 struct_typespec                                        1
+struct_var                                             1
 task                                                   9
 typespec_member                                        1
 === UHDM Object Stats End ===
@@ -434,6 +435,7 @@ range                                                 10
 ref_obj                                                1
 ref_typespec                                          25
 struct_typespec                                        1
+struct_var                                             1
 task                                                  18
 typespec_member                                        1
 === UHDM Object Stats End ===
@@ -993,16 +995,61 @@ design: (work@adc_ctrl_core)
   \_packed_array_var: (work@adc_ctrl_core.a), line:6:28, endln:6:29
     |vpiParent:
     \_module_inst: work@adc_ctrl_core (work@adc_ctrl_core), file:${SURELOG_DIR}/tests/SelectSelect/dut.sv, line:1:1, endln:8:10
-    |vpiTypespec:
-    \_ref_typespec: (work@adc_ctrl_core.a)
-      |vpiParent:
-      \_packed_array_var: (work@adc_ctrl_core.a), line:6:28, endln:6:29
-      |vpiFullName:work@adc_ctrl_core.a
-      |vpiActual:
-      \_packed_array_typespec: , line:6:4, endln:6:27
     |vpiName:a
     |vpiFullName:work@adc_ctrl_core.a
     |vpiVisibility:1
+    |vpiRange:
+    \_range: , line:6:17, endln:6:22
+      |vpiParent:
+      \_packed_array_var: (work@adc_ctrl_core.a), line:6:28, endln:6:29
+      |vpiLeftRange:
+      \_constant: , line:6:18, endln:6:19
+        |vpiParent:
+        \_range: , line:6:17, endln:6:22
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:6:20, endln:6:21
+        |vpiParent:
+        \_range: , line:6:17, endln:6:22
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiRange:
+    \_range: , line:6:22, endln:6:27
+      |vpiParent:
+      \_packed_array_var: (work@adc_ctrl_core.a), line:6:28, endln:6:29
+      |vpiLeftRange:
+      \_constant: , line:6:23, endln:6:24
+        |vpiParent:
+        \_range: , line:6:22, endln:6:27
+        |vpiDecompile:2
+        |vpiSize:64
+        |UINT:2
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:6:25, endln:6:26
+        |vpiParent:
+        \_range: , line:6:22, endln:6:27
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiElement:
+    \_struct_var: (work@adc_ctrl_core.a)
+      |vpiParent:
+      \_packed_array_var: (work@adc_ctrl_core.a), line:6:28, endln:6:29
+      |vpiTypespec:
+      \_ref_typespec: (work@adc_ctrl_core.a)
+        |vpiParent:
+        \_struct_var: (work@adc_ctrl_core.a)
+        |vpiFullName:work@adc_ctrl_core.a
+        |vpiActual:
+        \_struct_typespec: (filter_ctl_t), line:2:12, endln:4:5
+      |vpiFullName:work@adc_ctrl_core.a
   |vpiVariables:
   \_logic_var: (work@adc_ctrl_core.x), line:7:16, endln:7:33
     |vpiParent:
@@ -1295,56 +1342,6 @@ design: (work@adc_ctrl_core)
   |vpiSigned:1
 \_int_typespec: , line:66:26, endln:66:29
   |vpiSigned:1
-\_packed_array_typespec: , line:6:4, endln:6:27
-  |vpiParent:
-  \_packed_array_var: (work@adc_ctrl_core.a), line:6:28, endln:6:29
-  |vpiRange:
-  \_range: , line:6:17, endln:6:22
-    |vpiParent:
-    \_packed_array_typespec: , line:6:4, endln:6:27
-    |vpiLeftRange:
-    \_constant: , line:6:18, endln:6:19
-      |vpiParent:
-      \_range: , line:6:17, endln:6:22
-      |vpiDecompile:1
-      |vpiSize:64
-      |UINT:1
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:6:20, endln:6:21
-      |vpiParent:
-      \_range: , line:6:17, endln:6:22
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiRange:
-  \_range: , line:6:22, endln:6:27
-    |vpiParent:
-    \_packed_array_typespec: , line:6:4, endln:6:27
-    |vpiLeftRange:
-    \_constant: , line:6:23, endln:6:24
-      |vpiParent:
-      \_range: , line:6:22, endln:6:27
-      |vpiDecompile:2
-      |vpiSize:64
-      |UINT:2
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:6:25, endln:6:26
-      |vpiParent:
-      \_range: , line:6:22, endln:6:27
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiElemTypespec:
-  \_ref_typespec: (work@adc_ctrl_core.a)
-    |vpiParent:
-    \_packed_array_typespec: , line:6:4, endln:6:27
-    |vpiFullName:work@adc_ctrl_core.a
-    |vpiActual:
-    \_struct_typespec: (filter_ctl_t), line:2:12, endln:4:5
 \_logic_typespec: , line:7:4, endln:7:15
   |vpiParent:
   \_logic_var: (work@adc_ctrl_core.x), line:7:16, endln:7:33
diff --git a/tests/Selects/Selects.log b/tests/Selects/Selects.log
index cb0a7ec350..901dcbb8ec 100644
--- a/tests/Selects/Selects.log
+++ b/tests/Selects/Selects.log
@@ -168,7 +168,7 @@ range                                                  4
 ref_obj                                                3
 ref_typespec                                          13
 struct_typespec                                        2
-struct_var                                             1
+struct_var                                             2
 typespec_member                                        2
 === UHDM Object Stats End ===
 [INF:UH0707] Elaborating UHDM...
@@ -187,7 +187,7 @@ range                                                  4
 ref_obj                                                3
 ref_typespec                                          13
 struct_typespec                                        2
-struct_var                                             1
+struct_var                                             2
 typespec_member                                        2
 === UHDM Object Stats End ===
 [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/Selects/slpp_all/surelog.uhdm ...
@@ -329,16 +329,41 @@ design: (work@t)
   \_packed_array_var: (work@t.sw_rst_ctrl_n), line:12:44, endln:12:57
     |vpiParent:
     \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/Selects/dut.sv, line:1:1, endln:16:10
-    |vpiTypespec:
-    \_ref_typespec: (work@t.sw_rst_ctrl_n)
-      |vpiParent:
-      \_packed_array_var: (work@t.sw_rst_ctrl_n), line:12:44, endln:12:57
-      |vpiFullName:work@t.sw_rst_ctrl_n
-      |vpiActual:
-      \_packed_array_typespec: , line:12:3, endln:12:43
     |vpiName:sw_rst_ctrl_n
     |vpiFullName:work@t.sw_rst_ctrl_n
     |vpiVisibility:1
+    |vpiRange:
+    \_range: , line:12:38, endln:12:43
+      |vpiParent:
+      \_packed_array_var: (work@t.sw_rst_ctrl_n), line:12:44, endln:12:57
+      |vpiLeftRange:
+      \_constant: , line:12:39, endln:12:40
+        |vpiParent:
+        \_range: , line:12:38, endln:12:43
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:12:41, endln:12:42
+        |vpiParent:
+        \_range: , line:12:38, endln:12:43
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiElement:
+    \_struct_var: (work@t.sw_rst_ctrl_n)
+      |vpiParent:
+      \_packed_array_var: (work@t.sw_rst_ctrl_n), line:12:44, endln:12:57
+      |vpiTypespec:
+      \_ref_typespec: (work@t.sw_rst_ctrl_n)
+        |vpiParent:
+        \_struct_var: (work@t.sw_rst_ctrl_n)
+        |vpiFullName:work@t.sw_rst_ctrl_n
+        |vpiActual:
+        \_struct_typespec: (rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t), line:3:11, endln:5:4
+      |vpiFullName:work@t.sw_rst_ctrl_n
   |vpiVariables:
   \_logic_var: (work@t.X), line:14:9, endln:14:38
     |vpiParent:
@@ -465,36 +490,6 @@ design: (work@t)
     |vpiFullName:work@t.rstmgr_reg2hw_t.sw_rst_ctrl_n
     |vpiActual:
     \_struct_typespec: (rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t), line:3:11, endln:5:4
-\_packed_array_typespec: , line:12:3, endln:12:43
-  |vpiParent:
-  \_packed_array_var: (work@t.sw_rst_ctrl_n), line:12:44, endln:12:57
-  |vpiRange:
-  \_range: , line:12:38, endln:12:43
-    |vpiParent:
-    \_packed_array_typespec: , line:12:3, endln:12:43
-    |vpiLeftRange:
-    \_constant: , line:12:39, endln:12:40
-      |vpiParent:
-      \_range: , line:12:38, endln:12:43
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:12:41, endln:12:42
-      |vpiParent:
-      \_range: , line:12:38, endln:12:43
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiElemTypespec:
-  \_ref_typespec: (work@t.sw_rst_ctrl_n)
-    |vpiParent:
-    \_packed_array_typespec: , line:12:3, endln:12:43
-    |vpiFullName:work@t.sw_rst_ctrl_n
-    |vpiActual:
-    \_struct_typespec: (rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t), line:3:11, endln:5:4
 \_logic_typespec: , line:14:3, endln:14:8
   |vpiParent:
   \_logic_var: (work@t.X), line:14:9, endln:14:38
diff --git a/tests/StructVarImp/StructVarImp.log b/tests/StructVarImp/StructVarImp.log
index 6066becbce..3eb8d2e8fc 100644
--- a/tests/StructVarImp/StructVarImp.log
+++ b/tests/StructVarImp/StructVarImp.log
@@ -504,6 +504,7 @@ range                                                  7
 ref_obj                                                3
 ref_typespec                                          67
 struct_typespec                                       14
+struct_var                                             1
 task                                                   9
 typespec_member                                       24
 === UHDM Object Stats End ===
@@ -535,6 +536,7 @@ range                                                  7
 ref_obj                                                3
 ref_typespec                                          72
 struct_typespec                                       14
+struct_var                                             1
 task                                                  18
 typespec_member                                       24
 === UHDM Object Stats End ===
@@ -1547,16 +1549,41 @@ design: (work@top)
   \_packed_array_var: (work@top.region_cfgs), line:36:56, endln:36:67
     |vpiParent:
     \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructVarImp/dut.sv, line:33:1, endln:38:10
-    |vpiTypespec:
-    \_ref_typespec: (work@top.region_cfgs)
-      |vpiParent:
-      \_packed_array_var: (work@top.region_cfgs), line:36:56, endln:36:67
-      |vpiFullName:work@top.region_cfgs
-      |vpiActual:
-      \_packed_array_typespec: , line:36:3, endln:36:55
     |vpiName:region_cfgs
     |vpiFullName:work@top.region_cfgs
     |vpiVisibility:1
+    |vpiRange:
+    \_range: , line:36:42, endln:36:55
+      |vpiParent:
+      \_packed_array_var: (work@top.region_cfgs), line:36:56, endln:36:67
+      |vpiLeftRange:
+      \_ref_obj: (work@top.region_cfgs.MpRegions), line:36:43, endln:36:52
+        |vpiParent:
+        \_range: , line:36:42, endln:36:55
+        |vpiName:MpRegions
+        |vpiFullName:work@top.region_cfgs.MpRegions
+        |vpiActual:
+        \_logic_net: (work@top.MpRegions), line:36:43, endln:36:52
+      |vpiRightRange:
+      \_constant: , line:36:53, endln:36:54
+        |vpiParent:
+        \_range: , line:36:42, endln:36:55
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+    |vpiElement:
+    \_struct_var: (work@top.region_cfgs)
+      |vpiParent:
+      \_packed_array_var: (work@top.region_cfgs), line:36:56, endln:36:67
+      |vpiTypespec:
+      \_ref_typespec: (work@top.region_cfgs)
+        |vpiParent:
+        \_struct_var: (work@top.region_cfgs)
+        |vpiFullName:work@top.region_cfgs
+        |vpiActual:
+        \_struct_typespec: (flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_cfg_mreg_t), line:7:11, endln:26:4
+      |vpiFullName:work@top.region_cfgs
   |vpiParameter:
   \_parameter: (work@top.NBanks), line:4:17, endln:4:23
     |vpiParent:
@@ -2328,36 +2355,6 @@ design: (work@top)
   |vpiSigned:1
 \_int_typespec: , line:66:26, endln:66:29
   |vpiSigned:1
-\_packed_array_typespec: , line:36:3, endln:36:55
-  |vpiParent:
-  \_packed_array_var: (work@top.region_cfgs), line:36:56, endln:36:67
-  |vpiRange:
-  \_range: , line:36:42, endln:36:55
-    |vpiParent:
-    \_packed_array_typespec: , line:36:3, endln:36:55
-    |vpiLeftRange:
-    \_ref_obj: (work@top.region_cfgs.MpRegions), line:36:43, endln:36:52
-      |vpiParent:
-      \_range: , line:36:42, endln:36:55
-      |vpiName:MpRegions
-      |vpiFullName:work@top.region_cfgs.MpRegions
-      |vpiActual:
-      \_logic_net: (work@top.MpRegions), line:36:43, endln:36:52
-    |vpiRightRange:
-    \_constant: , line:36:53, endln:36:54
-      |vpiParent:
-      \_range: , line:36:42, endln:36:55
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiElemTypespec:
-  \_ref_typespec: (work@top.region_cfgs)
-    |vpiParent:
-    \_packed_array_typespec: , line:36:3, endln:36:55
-    |vpiFullName:work@top.region_cfgs
-    |vpiActual:
-    \_struct_typespec: (flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_cfg_mreg_t), line:7:11, endln:26:4
 \_packed_array_typespec: , line:36:3, endln:36:55
   |vpiRange:
   \_range: , line:36:42, endln:36:55
diff --git a/tests/TypedefAlias/TypedefAlias.log b/tests/TypedefAlias/TypedefAlias.log
index 5a4ab1d998..bf13741ada 100644
--- a/tests/TypedefAlias/TypedefAlias.log
+++ b/tests/TypedefAlias/TypedefAlias.log
@@ -15,30 +15,30 @@
 [NTE:EL0511] Nb leaf instances: 1.
 [INF:UH0706] Creating UHDM Model...
 === UHDM Object Stats Begin (Non-Elaborated Model) ===
-constant                                              10
+constant                                              12
 design                                                 1
 logic_net                                              2
-logic_typespec                                         8
+logic_typespec                                         9
 logic_var                                              2
-module_inst                                            2
+module_inst                                            3
 package                                                4
 packed_array_typespec                                  1
-range                                                  5
+range                                                  6
 ref_typespec                                          13
 struct_typespec                                        4
 typespec_member                                        4
 === UHDM Object Stats End ===
 [INF:UH0707] Elaborating UHDM...
 === UHDM Object Stats Begin (Elaborated Model) ===
-constant                                              10
+constant                                              12
 design                                                 1
 logic_net                                              2
-logic_typespec                                         8
+logic_typespec                                         9
 logic_var                                              2
-module_inst                                            2
+module_inst                                            3
 package                                                4
 packed_array_typespec                                  1
-range                                                  5
+range                                                  6
 ref_typespec                                          13
 struct_typespec                                        4
 typespec_member                                        4
@@ -354,16 +354,7 @@ design: (work@test)
   |vpiInstance:
   \_package: package1 (package1::), file:${SURELOG_DIR}/tests/TypedefAlias/dut.sv, line:1:1, endln:7:22
 \_logic_typespec: (t_two_bits), line:16:13, endln:16:24
-  |vpiParent:
-  \_logic_var: (work@test.kkkk), line:18:16, endln:18:20
   |vpiName:t_two_bits
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@test.kkkk.t_two_bits)
-    |vpiParent:
-    \_logic_typespec: (t_two_bits), line:16:13, endln:16:24
-    |vpiFullName:work@test.kkkk.t_two_bits
-    |vpiActual:
-    \_logic_typespec: (t_two_bits), line:16:13, endln:16:24
   |vpiRange:
   \_range: , line:16:19, endln:16:24
     |vpiParent:
diff --git a/tests/UnitEnum/UnitEnum.log b/tests/UnitEnum/UnitEnum.log
index e8958d9483..c85347837a 100644
--- a/tests/UnitEnum/UnitEnum.log
+++ b/tests/UnitEnum/UnitEnum.log
@@ -1199,14 +1199,10 @@ design: (work@top)
   \_logic_net: (work@top.env), line:21:13, endln:21:16
   |vpiName:Environment
 \_class_typespec: (Configuration1), line:22:1, endln:22:15
-  |vpiParent:
-  \_class_var: (work@top.cfg), line:22:16, endln:22:19
   |vpiName:Configuration1
   |vpiClassDefn:
   \_class_defn: (pkg::Configuration1), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:3:1, endln:4:9
 \_class_typespec: (Configuration2), line:23:1, endln:23:15
-  |vpiParent:
-  \_class_var: (work@top.cfg), line:23:16, endln:23:19
   |vpiName:Configuration2
   |vpiClassDefn:
   \_class_defn: (work@Configuration2), file:${SURELOG_DIR}/tests/UnitEnum/top.v, line:10:1, endln:11:9
diff --git a/tests/UnitTest/UnitTest.log b/tests/UnitTest/UnitTest.log
index 650e50371c..d9af083f83 100644
--- a/tests/UnitTest/UnitTest.log
+++ b/tests/UnitTest/UnitTest.log
@@ -2569,8 +2569,6 @@ design: (work@tb_operators)
   \_logic_net: (work@memory_ctrl1.toto1), line:59:5, endln:59:10
   |vpiName:DD1
 \_class_typespec: (DD2), line:61:1, endln:61:4
-  |vpiParent:
-  \_class_var: (work@memory_ctrl1.toto2), line:61:5, endln:61:10
   |vpiName:DD2
   |vpiClassDefn:
   \_class_defn: (work@DD2), file:${SURELOG_DIR}/tests/UnitTest/top.v, line:54:1, endln:55:9
diff --git a/tests/UnpackedTypespec/UnpackedTypespec.log b/tests/UnpackedTypespec/UnpackedTypespec.log
index c515b4a515..6932c1a2de 100644
--- a/tests/UnpackedTypespec/UnpackedTypespec.log
+++ b/tests/UnpackedTypespec/UnpackedTypespec.log
@@ -212,41 +212,41 @@ AST_DEBUG_END
 [NTE:EL0511] Nb leaf instances: 1.
 [INF:UH0706] Creating UHDM Model...
 === UHDM Object Stats Begin (Non-Elaborated Model) ===
-array_typespec                                         6
+array_typespec                                         8
 array_var                                              1
-constant                                              32
+constant                                              34
 design                                                 1
 enum_const                                             3
 enum_typespec                                          1
-int_typespec                                           3
+int_typespec                                           4
 integer_typespec                                       1
 logic_net                                              1
 logic_typespec                                         2
 module_inst                                            5
 operation                                              1
 packed_array_typespec                                  7
-range                                                 15
-ref_typespec                                          15
+range                                                 16
+ref_typespec                                          16
 string_typespec                                        1
 tagged_pattern                                         2
 === UHDM Object Stats End ===
 [INF:UH0707] Elaborating UHDM...
 === UHDM Object Stats Begin (Elaborated Model) ===
-array_typespec                                         6
+array_typespec                                         8
 array_var                                              1
-constant                                              32
+constant                                              34
 design                                                 1
 enum_const                                             3
 enum_typespec                                          1
-int_typespec                                           3
+int_typespec                                           4
 integer_typespec                                       1
 logic_net                                              1
 logic_typespec                                         2
 module_inst                                            5
 operation                                              1
 packed_array_typespec                                  7
-range                                                 15
-ref_typespec                                          15
+range                                                 16
+ref_typespec                                          16
 string_typespec                                        1
 tagged_pattern                                         2
 === UHDM Object Stats End ===
@@ -628,17 +628,14 @@ design: (work@top)
     \_packed_array_typespec: , line:18:11, endln:18:28
     |vpiActual:
     \_enum_typespec: (unit_type_t), line:10:4, endln:14:17
-\_array_typespec: (triple), line:4:11, endln:4:27
+\_integer_typespec: , line:5:16, endln:5:17
+  |INT:1
+\_string_typespec: (default), line:5:21, endln:5:28
   |vpiParent:
-  \_array_var: (work@top.b), line:5:10, endln:5:11
+  \_tagged_pattern: , line:5:29, endln:5:30
+  |vpiName:default
+\_array_typespec: (triple), line:4:11, endln:4:27
   |vpiName:triple
-  |vpiTypedefAlias:
-  \_ref_typespec: (work@top.b.triple)
-    |vpiParent:
-    \_array_typespec: (triple), line:4:11, endln:4:27
-    |vpiFullName:work@top.b.triple
-    |vpiActual:
-    \_array_typespec: (triple), line:4:11, endln:4:27
   |vpiRange:
   \_range: , line:4:22, endln:4:27
     |vpiParent:
@@ -660,22 +657,16 @@ design: (work@top)
       |UINT:3
       |vpiConstType:9
   |vpiElemTypespec:
-  \_ref_typespec: (work@top.b.triple)
+  \_ref_typespec: (triple)
     |vpiParent:
     \_array_typespec: (triple), line:4:11, endln:4:27
-    |vpiFullName:work@top.b.triple
+    |vpiFullName:triple
     |vpiActual:
     \_int_typespec: , line:4:11, endln:4:14
 \_int_typespec: , line:4:11, endln:4:14
   |vpiParent:
-  \_ref_typespec: (work@top.b.triple)
+  \_ref_typespec: (triple)
   |vpiSigned:1
-\_integer_typespec: , line:5:16, endln:5:17
-  |INT:1
-\_string_typespec: (default), line:5:21, endln:5:28
-  |vpiParent:
-  \_tagged_pattern: , line:5:29, endln:5:30
-  |vpiName:default
 \_array_typespec: (triple), line:4:11, endln:4:27
   |vpiName:triple
   |vpiTypedefAlias:
diff --git a/third_party/tests/AzadiRTL/AzadiRTL.log b/third_party/tests/AzadiRTL/AzadiRTL.log
index 8a15c2f05e..23700df356 100644
--- a/third_party/tests/AzadiRTL/AzadiRTL.log
+++ b/third_party/tests/AzadiRTL/AzadiRTL.log
@@ -13873,13 +13873,13 @@ property_spec                                         31
 range                                              90009
 ref_module                                           476
 ref_obj                                            57560
-ref_typespec                                      149108
+ref_typespec                                      149096
 ref_var                                               67
 return_stmt                                          118
 string_typespec                                    18806
 struct_net                                            67
 struct_typespec                                     3856
-struct_var                                           535
+struct_var                                           540
 sys_func_call                                        788
 tagged_pattern                                     18364
 task                                                   9
@@ -13951,16 +13951,16 @@ parameter                                          11553
 part_select                                         2783
 port                                               23276
 property_spec                                        110
-range                                              90043
+range                                              90047
 ref_module                                           476
 ref_obj                                           124705
-ref_typespec                                      175876
+ref_typespec                                      175828
 ref_var                                               95
 return_stmt                                          317
 string_typespec                                    18977
 struct_net                                            67
 struct_typespec                                     3856
-struct_var                                           721
+struct_var                                           730
 sys_func_call                                       1409
 tagged_pattern                                     18535
 task                                                  18
diff --git a/third_party/tests/CoresSweRV/CoresSweRV.log b/third_party/tests/CoresSweRV/CoresSweRV.log
index 43a8158aa0..4378993f2f 100644
--- a/third_party/tests/CoresSweRV/CoresSweRV.log
+++ b/third_party/tests/CoresSweRV/CoresSweRV.log
@@ -2436,7 +2436,7 @@ disable_fork                                           5
 do_while                                              51
 enum_const                                           503
 enum_typespec                                         94
-enum_var                                             194
+enum_var                                             196
 event_control                                         70
 event_stmt                                            10
 event_typespec                                        10
@@ -2487,7 +2487,7 @@ real_typespec                                         33
 real_var                                               8
 ref_module                                          2139
 ref_obj                                           136747
-ref_typespec                                       91132
+ref_typespec                                       91108
 ref_var                                             1830
 repeat                                                26
 return_stmt                                         3379
@@ -2495,7 +2495,7 @@ string_typespec                                     3204
 string_var                                          1403
 struct_net                                           199
 struct_typespec                                       52
-struct_var                                            47
+struct_var                                            55
 sys_func_call                                       1383
 tagged_pattern                                         3
 task                                                 587
@@ -2542,7 +2542,7 @@ disable_fork                                          15
 do_while                                             146
 enum_const                                           663
 enum_typespec                                        165
-enum_var                                            1651
+enum_var                                            1653
 event_control                                        132
 event_stmt                                            58
 event_typespec                                        10
@@ -2594,7 +2594,7 @@ real_typespec                                         33
 real_var                                              10
 ref_module                                          2139
 ref_obj                                           383727
-ref_typespec                                      191645
+ref_typespec                                      191621
 ref_var                                             8701
 repeat                                               207
 return_stmt                                        19618
@@ -2602,7 +2602,7 @@ string_typespec                                     3204
 string_var                                          5169
 struct_net                                           199
 struct_typespec                                       66
-struct_var                                           176
+struct_var                                           184
 sys_func_call                                      10631
 tagged_pattern                                         3
 task                                                4747
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
index 472ab27c44..06196339ae 100644
--- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
+++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -77,7 +77,7 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
   CMake that the project does not need compatibility with older versions.
 
 
--- Configuring done (0.1s)
+-- Configuring done (0.0s)
 -- Generating done (0.0s)
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
 [  6%] Generating 10_lsu_bus_intf.sv
@@ -2527,7 +2527,7 @@ disable_fork                                           5
 do_while                                              51
 enum_const                                           503
 enum_typespec                                         94
-enum_var                                             194
+enum_var                                             196
 event_control                                         70
 event_stmt                                            10
 event_typespec                                        10
@@ -2578,7 +2578,7 @@ real_typespec                                         33
 real_var                                               8
 ref_module                                          2139
 ref_obj                                           136747
-ref_typespec                                       91132
+ref_typespec                                       91108
 ref_var                                             1830
 repeat                                                26
 return_stmt                                         3379
@@ -2586,7 +2586,7 @@ string_typespec                                     3204
 string_var                                          1403
 struct_net                                           199
 struct_typespec                                       52
-struct_var                                            47
+struct_var                                            55
 sys_func_call                                       1383
 tagged_pattern                                         3
 task                                                 587
@@ -2633,7 +2633,7 @@ disable_fork                                          15
 do_while                                             146
 enum_const                                           663
 enum_typespec                                        165
-enum_var                                            1651
+enum_var                                            1653
 event_control                                        132
 event_stmt                                            58
 event_typespec                                        10
@@ -2685,7 +2685,7 @@ real_typespec                                         33
 real_var                                              10
 ref_module                                          2139
 ref_obj                                           383727
-ref_typespec                                      191645
+ref_typespec                                      191621
 ref_var                                             8701
 repeat                                               207
 return_stmt                                        19618
@@ -2693,7 +2693,7 @@ string_typespec                                     3204
 string_var                                          5169
 struct_net                                           199
 struct_typespec                                       66
-struct_var                                           176
+struct_var                                           184
 sys_func_call                                      10631
 tagged_pattern                                         3
 task                                                4747
diff --git a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log
index a191dbe859..feb0eaee86 100644
--- a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log
+++ b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log
@@ -6169,7 +6169,7 @@ case_stmt                                            231
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                          343956
+constant                                          344035
 cont_assign                                        19794
 design                                                 1
 enum_const                                          2548
@@ -6197,11 +6197,11 @@ integer_typespec                                     480
 integer_var                                            1
 io_decl                                              253
 logic_net                                          27147
-logic_typespec                                     68006
+logic_typespec                                     68028
 logic_var                                          13044
 module_inst                                         6189
 named_begin                                          496
-operation                                         101469
+operation                                         101476
 package                                               80
 packed_array_net                                       8
 packed_array_typespec                                170
@@ -6211,16 +6211,16 @@ parameter                                          31957
 part_select                                         3319
 port                                               38152
 property_spec                                          2
-range                                              48090
+range                                              48126
 ref_module                                          1917
-ref_obj                                           155542
+ref_obj                                           155549
 ref_typespec                                      129765
 ref_var                                               80
 return_stmt                                          111
 string_typespec                                     3809
 struct_net                                           184
 struct_typespec                                     2238
-struct_var                                          1120
+struct_var                                          1130
 sys_func_call                                        321
 tagged_pattern                                      2681
 task                                                   9
@@ -6244,7 +6244,7 @@ case_stmt                                            614
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                          348665
+constant                                          348744
 cont_assign                                        47364
 design                                                 1
 enum_const                                          2553
@@ -6272,11 +6272,11 @@ integer_typespec                                     480
 integer_var                                            1
 io_decl                                             2275
 logic_net                                          27147
-logic_typespec                                     68006
+logic_typespec                                     68028
 logic_var                                          23278
 module_inst                                         6953
 named_begin                                          984
-operation                                         200393
+operation                                         200400
 package                                               80
 packed_array_net                                       8
 packed_array_typespec                                170
@@ -6286,16 +6286,16 @@ parameter                                          31957
 part_select                                         9422
 port                                               67958
 property_spec                                          4
-range                                              48569
+range                                              48605
 ref_module                                          1917
-ref_obj                                           389021
+ref_obj                                           389028
 ref_typespec                                      208061
 ref_var                                               80
 return_stmt                                         1419
 string_typespec                                     4099
 struct_net                                           184
 struct_typespec                                     2238
-struct_var                                          1482
+struct_var                                          1492
 sys_func_call                                        450
 tagged_pattern                                      2971
 task                                                  18
diff --git a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log
index 4f67579646..7ebbba682a 100644
--- a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log
+++ b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log
@@ -14342,12 +14342,12 @@ chandle_var                                           14
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                          926574
+constant                                          926727
 cont_assign                                        39267
 design                                                 1
 enum_const                                         31253
 enum_typespec                                       8348
-enum_var                                            1150
+enum_var                                            1174
 event_control                                       1182
 final_stmt                                             8
 for_stmt                                             430
@@ -14374,12 +14374,12 @@ interface_inst                                        10
 interface_typespec                                     1
 io_decl                                              433
 logic_net                                          68737
-logic_typespec                                    228788
+logic_typespec                                    228832
 logic_var                                          30672
 method_func_call                                       1
-module_inst                                        23137
+module_inst                                        23138
 named_begin                                         1113
-operation                                         228138
+operation                                         228151
 package                                              142
 packed_array_net                                      30
 packed_array_typespec                                660
@@ -14388,17 +14388,17 @@ param_assign                                      107337
 parameter                                         122316
 part_select                                         4960
 port                                               91788
-range                                             167861
+range                                             167931
 ref_module                                          5040
-ref_obj                                           332689
-ref_typespec                                      453756
+ref_obj                                           332702
+ref_typespec                                      453726
 ref_var                                              174
 return_stmt                                          429
 string_typespec                                    36713
 string_var                                            19
 struct_net                                           571
 struct_typespec                                    24138
-struct_var                                          1794
+struct_var                                          1840
 sys_func_call                                        500
 tagged_pattern                                     33133
 task                                                   9
@@ -14427,12 +14427,12 @@ chandle_var                                           14
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                          935934
+constant                                          936087
 cont_assign                                       147474
 design                                                 1
 enum_const                                         31258
 enum_typespec                                       8349
-enum_var                                            1901
+enum_var                                            1925
 event_control                                      15153
 final_stmt                                            15
 for_stmt                                            8970
@@ -14459,12 +14459,12 @@ interface_inst                                        10
 interface_typespec                                     1
 io_decl                                            19631
 logic_net                                          68737
-logic_typespec                                    228788
+logic_typespec                                    228832
 logic_var                                          81286
 method_func_call                                       1
-module_inst                                        32676
+module_inst                                        32677
 named_begin                                         3234
-operation                                         635794
+operation                                         635807
 package                                              142
 packed_array_net                                      30
 packed_array_typespec                                660
@@ -14473,17 +14473,17 @@ param_assign                                      145647
 parameter                                         122316
 part_select                                        22451
 port                                              224742
-range                                             171004
+range                                             171087
 ref_module                                          5040
-ref_obj                                          1087983
-ref_typespec                                      796928
+ref_obj                                          1087996
+ref_typespec                                      796720
 ref_var                                              176
 return_stmt                                        15514
 string_typespec                                    37103
 string_var                                            36
 struct_net                                           571
 struct_typespec                                    24138
-struct_var                                          2359
+struct_var                                          2418
 sys_func_call                                       2410
 tagged_pattern                                     33523
 task                                                  18
diff --git a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log
index 8bf29d9f5e..7218d51d19 100644
--- a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log
+++ b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log
@@ -5824,7 +5824,7 @@ chandle_var                                           11
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                          321203
+constant                                          321233
 cont_assign                                        19205
 design                                                 1
 enum_const                                          2446
@@ -5854,7 +5854,7 @@ integer_var                                            1
 interface_inst                                         1
 io_decl                                              357
 logic_net                                          26847
-logic_typespec                                     68443
+logic_typespec                                     68458
 logic_var                                          12617
 module_inst                                         5797
 named_begin                                          491
@@ -5867,7 +5867,7 @@ param_assign                                       18185
 parameter                                          22126
 part_select                                         3296
 port                                               37447
-range                                              49277
+range                                              49292
 ref_module                                          1821
 ref_obj                                           155177
 ref_typespec                                      128338
@@ -5877,7 +5877,7 @@ string_typespec                                     3868
 string_var                                            14
 struct_net                                           177
 struct_typespec                                     2237
-struct_var                                          1108
+struct_var                                          1118
 sys_func_call                                        396
 tagged_pattern                                      2681
 task                                                   9
@@ -5905,7 +5905,7 @@ chandle_var                                           11
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                          325958
+constant                                          325988
 cont_assign                                        43470
 design                                                 1
 enum_const                                          2451
@@ -5935,7 +5935,7 @@ integer_var                                            1
 interface_inst                                         1
 io_decl                                             2569
 logic_net                                          26847
-logic_typespec                                     68443
+logic_typespec                                     68458
 logic_var                                          21763
 module_inst                                         6364
 named_begin                                          955
@@ -5948,7 +5948,7 @@ param_assign                                       24522
 parameter                                          22126
 part_select                                         9045
 port                                               64704
-range                                              49756
+range                                              49771
 ref_module                                          1821
 ref_obj                                           371893
 ref_typespec                                      202183
@@ -5958,7 +5958,7 @@ string_typespec                                     4158
 string_var                                            31
 struct_net                                           177
 struct_typespec                                     2237
-struct_var                                          1466
+struct_var                                          1476
 sys_func_call                                        639
 tagged_pattern                                      2971
 task                                                  18
diff --git a/third_party/tests/IncompTitan/IncompTitan.log b/third_party/tests/IncompTitan/IncompTitan.log
index c4aff1b021..a25716e6ad 100644
--- a/third_party/tests/IncompTitan/IncompTitan.log
+++ b/third_party/tests/IncompTitan/IncompTitan.log
@@ -5336,7 +5336,7 @@ case_stmt                                            117
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                          403050
+constant                                          403123
 cont_assign                                        18019
 cover                                                 20
 design                                                 1
@@ -5367,11 +5367,11 @@ integer_typespec                                     226
 integer_var                                            8
 io_decl                                              273
 logic_net                                          35503
-logic_typespec                                     99471
+logic_typespec                                     99490
 logic_var                                          12596
 module_inst                                        10358
 named_begin                                          395
-operation                                         103306
+operation                                         103313
 package                                               92
 packed_array_net                                       8
 packed_array_typespec                                241
@@ -5384,9 +5384,9 @@ prop_formal_decl                                       3
 property_decl                                          1
 property_inst                                          4
 property_spec                                        479
-range                                              75199
+range                                              75232
 ref_module                                          2376
-ref_obj                                           166314
+ref_obj                                           166321
 ref_typespec                                      167850
 ref_var                                               74
 return_stmt                                          137
@@ -5394,7 +5394,7 @@ sequence_decl                                         36
 string_typespec                                    10655
 struct_net                                           147
 struct_typespec                                     5521
-struct_var                                          1283
+struct_var                                          1295
 sys_func_call                                       2746
 tagged_pattern                                      7929
 task                                                   9
diff --git a/third_party/tests/NyuziProcessor/NyuziProcessor.log b/third_party/tests/NyuziProcessor/NyuziProcessor.log
index ece6a35424..1b534595de 100644
--- a/third_party/tests/NyuziProcessor/NyuziProcessor.log
+++ b/third_party/tests/NyuziProcessor/NyuziProcessor.log
@@ -893,7 +893,7 @@ case_stmt                                            141
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                          140204
+constant                                          141204
 cont_assign                                         2227
 design                                                 1
 enum_const                                         13241
@@ -926,23 +926,23 @@ interface_inst                                        48
 interface_typespec                                   104
 io_decl                                              831
 logic_net                                           3752
-logic_typespec                                     20512
+logic_typespec                                     20996
 logic_var                                           2684
 modport                                               77
 module_array                                           3
 module_inst                                         1039
 module_typespec                                        3
 named_begin                                            8
-operation                                          24167
+operation                                          24199
 package                                              100
 packed_array_typespec                               2258
 param_assign                                       52436
 parameter                                          76277
 part_select                                          435
 port                                                3875
-range                                              17993
+range                                              18477
 ref_module                                           187
-ref_obj                                            33502
+ref_obj                                            33534
 ref_typespec                                      143084
 string_typespec                                       84
 string_var                                             1
@@ -972,7 +972,7 @@ case_stmt                                            434
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                          142226
+constant                                          143226
 cont_assign                                         5561
 design                                                 1
 enum_const                                         13246
@@ -1005,23 +1005,23 @@ interface_inst                                        48
 interface_typespec                                   104
 io_decl                                              845
 logic_net                                           3752
-logic_typespec                                     20512
+logic_typespec                                     20996
 logic_var                                           6026
 modport                                               77
 module_array                                           3
 module_inst                                         1207
 module_typespec                                        3
 named_begin                                           50
-operation                                          45813
+operation                                          45845
 package                                              100
 packed_array_typespec                               2258
 param_assign                                       83958
 parameter                                          76277
 part_select                                         1179
 port                                                7457
-range                                              18138
+range                                              18622
 ref_module                                           187
-ref_obj                                            90410
+ref_obj                                            90442
 ref_typespec                                      211143
 string_typespec                                       84
 string_var                                             1
diff --git a/third_party/tests/OVMSwitch/OVMSwitch.log b/third_party/tests/OVMSwitch/OVMSwitch.log
index fc1f3d46c6..5baa1d6c2c 100644
--- a/third_party/tests/OVMSwitch/OVMSwitch.log
+++ b/third_party/tests/OVMSwitch/OVMSwitch.log
@@ -367,7 +367,7 @@ array_var                                            315
 assignment                                          4149
 begin                                               2825
 bit_select                                           963
-bit_typespec                                        1065
+bit_typespec                                        1115
 bit_var                                              721
 break_stmt                                            21
 byte_typespec                                         90
@@ -379,7 +379,7 @@ class_typespec                                      4665
 class_var                                           2854
 clocking_block                                        10
 clocking_io_decl                                      30
-constant                                           13667
+constant                                           13767
 constraint                                             6
 cont_assign                                           90
 delay_control                                         49
@@ -433,7 +433,7 @@ param_assign                                        2562
 parameter                                           4702
 part_select                                            8
 port                                                  73
-range                                               1062
+range                                               1112
 real_typespec                                         18
 real_var                                               3
 ref_module                                             3
diff --git a/third_party/tests/Opentitan/Earlgrey.log b/third_party/tests/Opentitan/Earlgrey.log
index 9e2c49bef8..e82645189c 100644
--- a/third_party/tests/Opentitan/Earlgrey.log
+++ b/third_party/tests/Opentitan/Earlgrey.log
@@ -25175,7 +25175,7 @@ case_stmt                                            132
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                          213950
+constant                                          213980
 cont_assign                                        13781
 design                                                 1
 enum_const                                          2016
@@ -25201,7 +25201,7 @@ integer_typespec                                     310
 integer_var                                            2
 io_decl                                              149
 logic_net                                          20837
-logic_typespec                                     49064
+logic_typespec                                     49079
 logic_var                                           9486
 module_inst                                         4621
 named_begin                                          354
@@ -25215,7 +25215,7 @@ parameter                                          14891
 part_select                                         1855
 port                                               29628
 property_spec                                          2
-range                                              35774
+range                                              35789
 ref_module                                          1426
 ref_obj                                           112463
 ref_typespec                                       93012
@@ -25224,7 +25224,7 @@ return_stmt                                           46
 string_typespec                                     2488
 struct_net                                           108
 struct_typespec                                     1426
-struct_var                                           989
+struct_var                                           999
 sys_func_call                                        144
 tagged_pattern                                      1564
 task                                                   9
@@ -25248,7 +25248,7 @@ case_stmt                                            336
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                          217395
+constant                                          217425
 cont_assign                                        30746
 design                                                 1
 enum_const                                          2021
@@ -25274,7 +25274,7 @@ integer_typespec                                     310
 integer_var                                          518
 io_decl                                             2054
 logic_net                                          20837
-logic_typespec                                     49064
+logic_typespec                                     49079
 logic_var                                          15169
 module_inst                                         5056
 named_begin                                          736
@@ -25288,7 +25288,7 @@ parameter                                          14891
 part_select                                         4274
 port                                               51234
 property_spec                                          4
-range                                              36090
+range                                              36105
 ref_module                                          1426
 ref_obj                                           265401
 ref_typespec                                      148130
@@ -25297,7 +25297,7 @@ return_stmt                                          424
 string_typespec                                     2758
 struct_net                                           108
 struct_typespec                                     1426
-struct_var                                          1289
+struct_var                                          1299
 sys_func_call                                        171
 tagged_pattern                                      1834
 task                                                  18
diff --git a/third_party/tests/Opentitan/Opentitan.log b/third_party/tests/Opentitan/Opentitan.log
index 520a075b93..801c1f0c3c 100644
--- a/third_party/tests/Opentitan/Opentitan.log
+++ b/third_party/tests/Opentitan/Opentitan.log
@@ -4190,7 +4190,7 @@ chandle_var                                            2
 class_defn                                           613
 class_typespec                                      8456
 class_var                                           3308
-constant                                          248555
+constant                                          248585
 constraint                                             4
 cont_assign                                        13810
 continue_stmt                                         52
@@ -4233,7 +4233,7 @@ integer_var                                            2
 interface_inst                                         5
 io_decl                                             7058
 logic_net                                          20866
-logic_typespec                                     49187
+logic_typespec                                     49202
 logic_var                                           9559
 long_int_typespec                                     99
 long_int_var                                          20
@@ -4255,7 +4255,7 @@ prop_formal_decl                                       3
 property_decl                                          1
 property_inst                                          4
 property_spec                                        642
-range                                              37826
+range                                              37841
 real_typespec                                         33
 real_var                                               8
 ref_module                                          1427
@@ -4269,7 +4269,7 @@ string_typespec                                     5657
 string_var                                          1366
 struct_net                                           108
 struct_typespec                                     1441
-struct_var                                          1025
+struct_var                                          1037
 sys_func_call                                       3237
 tagged_pattern                                      1565
 task                                                 583
@@ -4307,7 +4307,7 @@ chandle_var                                            2
 class_defn                                           613
 class_typespec                                      8828
 class_var                                          22226
-constant                                          252325
+constant                                          252355
 constraint                                            10
 cont_assign                                        30814
 continue_stmt                                        173
@@ -4350,7 +4350,7 @@ integer_var                                          518
 interface_inst                                         7
 io_decl                                            57608
 logic_net                                          20866
-logic_typespec                                     49187
+logic_typespec                                     49202
 logic_var                                          15382
 long_int_typespec                                     99
 long_int_var                                         167
@@ -4373,7 +4373,7 @@ prop_formal_decl                                       6
 property_decl                                          2
 property_inst                                          8
 property_spec                                       4757
-range                                              39932
+range                                              39949
 real_typespec                                         33
 real_var                                              10
 ref_module                                          1427
@@ -4387,7 +4387,7 @@ string_typespec                                     5927
 string_var                                          5120
 struct_net                                           108
 struct_typespec                                     1455
-struct_var                                          1454
+struct_var                                          1468
 sys_func_call                                      20107
 tagged_pattern                                      1835
 task                                                4739
diff --git a/third_party/tests/Rp32/rp32.log b/third_party/tests/Rp32/rp32.log
index 96fab04f7e..2ef29f431b 100644
--- a/third_party/tests/Rp32/rp32.log
+++ b/third_party/tests/Rp32/rp32.log
@@ -246,7 +246,7 @@ case_stmt                                             50
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                            7824
+constant                                            7964
 cont_assign                                          220
 design                                                 1
 enum_const                                           532
@@ -272,7 +272,7 @@ interface_inst                                        13
 interface_typespec                                    21
 io_decl                                              235
 logic_net                                            560
-logic_typespec                                      1458
+logic_typespec                                      1528
 logic_var                                            258
 modport                                               22
 module_array                                           7
@@ -286,7 +286,7 @@ param_assign                                         160
 parameter                                            165
 part_select                                           80
 port                                                 438
-range                                               1289
+range                                               1359
 ref_module                                            25
 ref_obj                                             6413
 ref_typespec                                       10829
@@ -318,7 +318,7 @@ case_stmt                                            249
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                            8546
+constant                                            8686
 cont_assign                                          319
 design                                                 1
 enum_const                                           537
@@ -344,7 +344,7 @@ interface_inst                                        13
 interface_typespec                                    21
 io_decl                                              428
 logic_net                                            560
-logic_typespec                                      1458
+logic_typespec                                      1528
 logic_var                                            262
 modport                                               22
 module_array                                           7
@@ -358,7 +358,7 @@ param_assign                                         160
 parameter                                            165
 part_select                                          217
 port                                                 542
-range                                               1289
+range                                               1359
 ref_module                                            25
 ref_obj                                            21113
 ref_typespec                                       11312
diff --git a/third_party/tests/Scr1/Scr1.log b/third_party/tests/Scr1/Scr1.log
index 7842e0f35f..ce0b254928 100644
--- a/third_party/tests/Scr1/Scr1.log
+++ b/third_party/tests/Scr1/Scr1.log
@@ -233,7 +233,7 @@ case_stmt                                            107
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                           12123
+constant                                           12127
 cont_assign                                          604
 delay_control                                          8
 design                                                 1
@@ -260,7 +260,7 @@ integer_typespec                                      59
 integer_var                                            3
 io_decl                                               27
 logic_net                                           2985
-logic_typespec                                      4193
+logic_typespec                                      4195
 logic_var                                            828
 method_func_call                                       5
 module_inst                                          140
@@ -274,7 +274,7 @@ parameter                                            891
 part_select                                          318
 port                                                2564
 property_spec                                         38
-range                                               2896
+range                                               2898
 ref_module                                            42
 ref_obj                                            12272
 ref_typespec                                        6673
@@ -283,7 +283,7 @@ string_typespec                                       19
 string_var                                            10
 struct_net                                            28
 struct_typespec                                       23
-struct_var                                            25
+struct_var                                            31
 sys_func_call                                        217
 task                                                  11
 task_call                                              3
diff --git a/third_party/tests/Scr1SvTests/Scr1SvTests.log b/third_party/tests/Scr1SvTests/Scr1SvTests.log
index 24b01caaa3..270952df58 100644
--- a/third_party/tests/Scr1SvTests/Scr1SvTests.log
+++ b/third_party/tests/Scr1SvTests/Scr1SvTests.log
@@ -165,7 +165,7 @@ case_stmt                                            121
 class_defn                                             8
 class_typespec                                         4
 class_var                                              3
-constant                                           12176
+constant                                           12178
 cont_assign                                         1130
 delay_control                                          7
 design                                                 1
@@ -192,7 +192,7 @@ integer_typespec                                      74
 integer_var                                            3
 io_decl                                               27
 logic_net                                           3237
-logic_typespec                                      4681
+logic_typespec                                      4682
 logic_var                                           1058
 method_func_call                                       4
 module_inst                                          153
@@ -206,7 +206,7 @@ parameter                                            933
 part_select                                          319
 port                                                2646
 property_spec                                         32
-range                                               2889
+range                                               2890
 ref_module                                            43
 ref_obj                                            13627
 ref_typespec                                        7310
@@ -215,7 +215,7 @@ string_typespec                                       16
 string_var                                             8
 struct_net                                            25
 struct_typespec                                       21
-struct_var                                            25
+struct_var                                            31
 sys_func_call                                        131
 tagged_pattern                                         1
 task                                                   9
diff --git a/third_party/tests/Tnoc/Tnoc.log b/third_party/tests/Tnoc/Tnoc.log
index 19af89de02..1248021543 100644
--- a/third_party/tests/Tnoc/Tnoc.log
+++ b/third_party/tests/Tnoc/Tnoc.log
@@ -4089,7 +4089,7 @@ short_int_typespec                                777968
 string_typespec                                    68237
 struct_net                                            54
 struct_typespec                                    97439
-struct_var                                            62
+struct_var                                          3424
 sys_func_call                                         17
 tagged_pattern                                     68237
 task                                                   9