From 8a9d67e13474a01b71da8a791e46723b2b19d791 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Mon, 16 Oct 2023 22:52:42 -0700 Subject: [PATCH] Report first 10 syntax errors --- .vscode/launch.json | 2 +- .../SourceCompile/AntlrParserErrorListener.h | 4 +- .../AntlrParserErrorListener.cpp | 4 +- tests/PreProcMacro/PreProcMacro.log | 29 +- third_party/UHDM | 2 +- .../tests/CoresSweRVMP/CoresSweRVMP.log | 10 +- third_party/tests/Google/Google.log | 142 +++- third_party/tests/Icarus/Icarus.log | 26 +- third_party/tests/UtdSV/UtdSV.log | 10 +- third_party/tests/Verilator/Verilator.log | 340 ++++++++-- third_party/tests/Yosys/Yosys.log | 30 +- .../tests/YosysTestSuite/YosysTestSuite.log | 254 ++++++- third_party/tests/YosysTests/YosysTests.log | 620 ++++++++++++++++-- third_party/tests/Zachjs/Zachjs.log | 102 ++- 14 files changed, 1395 insertions(+), 180 deletions(-) diff --git a/.vscode/launch.json b/.vscode/launch.json index e03dae94ff..3f2be90596 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -837,7 +837,7 @@ "type": "cppdbg", "request": "launch", "program": "${workspaceFolder}/dbuild/bin/surelog", - "args": ["-parse", "tests/ScratchPad.sv", "-elabuhdm", "-d", "inst", "-synth", "-d", "ast", "-d", "uhdm", "-d", "uhdmstats", "-d", "vpi_ids", "-replay", "-nocache", "-nobuiltin"], + "args": ["-parse", "tests/ScratchPad.sv", "-elabuhdm", "-d", "inst", "-synth", "-d", "ast", "-d", "uhdm", "-d", "uhdmstats", "-d", "vpi_ids", "-replay", "-nobuiltin"], "stopAtEntry": false, "cwd": "${workspaceFolder}", "environment": [], diff --git a/include/Surelog/SourceCompile/AntlrParserErrorListener.h b/include/Surelog/SourceCompile/AntlrParserErrorListener.h index 4f7002fc16..a482e31a0e 100644 --- a/include/Surelog/SourceCompile/AntlrParserErrorListener.h +++ b/include/Surelog/SourceCompile/AntlrParserErrorListener.h @@ -40,7 +40,7 @@ class AntlrParserErrorListener : public antlr4::ANTLRErrorListener { AntlrParserErrorListener(ParseFile *parser, bool watchDogOn, uint32_t lineOffset, PathId fileId) : m_parser(parser), - m_reportedSyntaxError(false), + m_reportedSyntaxError(0), m_watchDogOn(watchDogOn), m_barked(false), m_lineOffset(lineOffset), @@ -70,7 +70,7 @@ class AntlrParserErrorListener : public antlr4::ANTLRErrorListener { antlr4::atn::ATNConfigSet *configs) override; ParseFile *m_parser; - bool m_reportedSyntaxError; + int m_reportedSyntaxError; bool m_watchDogOn; bool m_barked; uint32_t m_lineOffset; diff --git a/src/SourceCompile/AntlrParserErrorListener.cpp b/src/SourceCompile/AntlrParserErrorListener.cpp index 6aa670b535..dff41c316a 100644 --- a/src/SourceCompile/AntlrParserErrorListener.cpp +++ b/src/SourceCompile/AntlrParserErrorListener.cpp @@ -51,7 +51,7 @@ void AntlrParserErrorListener::syntaxError( charPositionInLine, ":"); } } - if (m_reportedSyntaxError == false) { + if (m_reportedSyntaxError < 10) { SymbolId msgId = m_parser->registerSymbol(msg); int32_t adjustedLine = m_parser->getLineNb(line + m_lineOffset); Location loc1(m_parser->getFileId(line + m_lineOffset), adjustedLine, @@ -60,8 +60,8 @@ void AntlrParserErrorListener::syntaxError( Location loc3(m_parser->getCompileSourceFile()->getFileId(), 0, 0); Error err(ErrorDefinition::PA_SYNTAX_ERROR, {loc1, loc2, loc3}); m_parser->addError(err); - m_reportedSyntaxError = true; } + m_reportedSyntaxError++; } void AntlrParserErrorListener::reportAmbiguity( diff --git a/tests/PreProcMacro/PreProcMacro.log b/tests/PreProcMacro/PreProcMacro.log index 814e8ff311..8ebcea3ed4 100644 --- a/tests/PreProcMacro/PreProcMacro.log +++ b/tests/PreProcMacro/PreProcMacro.log @@ -219,10 +219,37 @@ AST_DEBUG_END [SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', SURELOG_MACRO_NOT_DEFINED:check1!!! A ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:17:4:. +[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', + SURELOG_MACRO_NOT_DEFINED:check1!!! A + ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:17:4:. +[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:6:4: Syntax error: no viable alternative at input 'A \n "A is ifdef'd"', + "A is ifdef'd" + ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:18:4:. +[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:8:4: Syntax error: extraneous input '"A is not ifdef'd"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + "A is not ifdef'd" + ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:20:4:. +[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', + SURELOG_MACRO_NOT_DEFINED:check1!!! B + ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:26:4:. +[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', + SURELOG_MACRO_NOT_DEFINED:check1!!! B + ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:26:4:. +[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:6:4: Syntax error: no viable alternative at input 'B \n "B is ifdef'd"', + "B is ifdef'd" + ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:27:4:. +[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:8:4: Syntax error: extraneous input '"B is not ifdef'd"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + "B is not ifdef'd" + ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:29:4:. +[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', + SURELOG_MACRO_NOT_DEFINED:check1!!! A + ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:35:4:. +[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', + SURELOG_MACRO_NOT_DEFINED:check1!!! A + ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:35:4:. [ERR:PA0203] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5: Unknown macro "check1". [ERR:PA0203] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:7: Unknown macro "check2". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 10 [ ERROR] : 4 [WARNING] : 0 [ NOTE] : 0 diff --git a/third_party/UHDM b/third_party/UHDM index 3a9214ceae..7e9ae0f58e 160000 --- a/third_party/UHDM +++ b/third_party/UHDM @@ -1 +1 @@ -Subproject commit 3a9214ceae499aa57aafd5464bb2876cb351f40b +Subproject commit 7e9ae0f58ec946c021d0321194b2aa198d7bdaa0 diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index f1fafffc83..46d011a605 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -80,10 +80,10 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required): -- Configuring done (0.1s) -- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -[ 6%] Generating 10_lsu_bus_intf.sv +[ 6%] Generating 12_beh_lib.sv [ 12%] Generating 13_ifu_mem_ctl.sv -[ 18%] Generating 12_beh_lib.sv -[ 25%] Generating 11_ifu_bp_ctl.sv +[ 18%] Generating 11_ifu_bp_ctl.sv +[ 25%] Generating 10_lsu_bus_intf.sv [ 31%] Generating 14_mem_lib.sv [ 37%] Generating 15_exu.sv [ 43%] Generating 16_dec_decode_ctl.sv @@ -93,8 +93,8 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required): [ 68%] Generating 4_dec_tlu_ctl.sv [ 75%] Generating 5_lsu_bus_buffer.sv [ 81%] Generating 6_dbg.sv -[ 87%] Generating 8_ifu_aln_ctl.sv -[ 93%] Generating 7_axi4_to_ahb.sv +[ 87%] Generating 7_axi4_to_ahb.sv +[ 93%] Generating 8_ifu_aln_ctl.sv [100%] Generating 9_tb_top.sv [100%] Built target Parse Surelog parsing status: 0 diff --git a/third_party/tests/Google/Google.log b/third_party/tests/Google/Google.log index 9203845c11..ba9573d417 100644 --- a/third_party/tests/Google/Google.log +++ b/third_party/tests/Google/Google.log @@ -11,8 +11,11 @@ Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.7.2-real-constants-illegal.sv:20:8: Syntax error: no viable alternative at input 'module top();\n logic [31:0] a;\n\n initial begin;\n a = .', a = .12; ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.7.2-real-constants-illegal.sv:20:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.7.2-real-constants-illegal.sv:19:2: Syntax error: mismatched input 'initial' expecting , + initial begin; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.7.2-real-constants-illegal.sv:19:2:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -216,8 +219,17 @@ Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6--wrong-identifiers.sv:17:6: Syntax error: no viable alternative at input 'module identifiers();\n reg $', reg $dollar; ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6--wrong-identifiers.sv:17:6:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6--wrong-identifiers.sv:17:6: Syntax error: extraneous input '$' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + reg $dollar; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6--wrong-identifiers.sv:17:6:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6--wrong-identifiers.sv:18:6: Syntax error: extraneous input '0' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + reg 0number; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6--wrong-identifiers.sv:18:6:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6--wrong-identifiers.sv:19: Syntax error: extraneous input 'endmodule' expecting , +endmodule +^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6--wrong-identifiers.sv:19:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 4 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -268,8 +280,11 @@ Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.7.1--integers-signed-illegal.sv:20:10: Syntax error: no viable alternative at input 'module top();\n logic [7:0] a;\n\n initial begin\n a = 8'd', a = 8'd-6; ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.7.1--integers-signed-illegal.sv:20:10:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.7.1--integers-signed-illegal.sv:19:2: Syntax error: mismatched input 'initial' expecting , + initial begin + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.7.1--integers-signed-illegal.sv:19:2:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -298,9 +313,15 @@ Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:8: Syntax error: no viable alternative at input 'module top();\nint a = SURELOG_MACRO_NOT_DEFINED:VAR_1!!!', int a = SURELOG_MACRO_NOT_DEFINED:VAR_1!!! + SURELOG_MACRO_NOT_DEFINED:VAR_2!!! ; ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:8: Syntax error: no viable alternative at input '= SURELOG_MACRO_NOT_DEFINED:VAR_1!!!', +int a = SURELOG_MACRO_NOT_DEFINED:VAR_1!!! + SURELOG_MACRO_NOT_DEFINED:VAR_2!!! ; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:44: Syntax error: mismatched input '+' expecting , +int a = SURELOG_MACRO_NOT_DEFINED:VAR_1!!! + SURELOG_MACRO_NOT_DEFINED:VAR_2!!! ; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:44:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18: Unknown macro "VAR_1". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 3 [WARNING] : 0 [ NOTE] : 0 @@ -553,8 +574,11 @@ Processing: -cd chapter-15 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-15/15.4--mailbox-blocking.sv:21:1: Syntax error: no viable alternative at input 'module top();\n\nmailbox m;\n\ninitial begin\n\tm = new();\n\tstring', string msg = "abc"; ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-15/15.4--mailbox-blocking.sv:21:1:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-15/15.4--mailbox-blocking.sv:19: Syntax error: mismatched input 'initial' expecting , +initial begin +^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-15/15.4--mailbox-blocking.sv:19:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -562,8 +586,11 @@ Processing: -cd chapter-15 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-15/15.4--mailbox-non-blocking.sv:21:1: Syntax error: no viable alternative at input 'module top();\n\nmailbox m;\n\ninitial begin\n\tm = new();\n\tstring', string msg = "abc"; ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-15/15.4--mailbox-non-blocking.sv:21:1:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-15/15.4--mailbox-non-blocking.sv:19: Syntax error: mismatched input 'initial' expecting , +initial begin +^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-15/15.4--mailbox-non-blocking.sv:19:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -745,8 +772,11 @@ Processing: -cd chapter-11 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-11/11.3.6--assign_in_expr_inv.sv:23:7: Syntax error: no viable alternative at input 'module top();\n\nint a;\nint b;\nint c;\n\ninitial begin\n\ta = b =', a = b = c = 5; ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-11/11.3.6--assign_in_expr_inv.sv:23:7:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-11/11.3.6--assign_in_expr_inv.sv:22: Syntax error: mismatched input 'initial' expecting , +initial begin +^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-11/11.3.6--assign_in_expr_inv.sv:22:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -2003,8 +2033,11 @@ ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_12.s [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_12.sv:19: Syntax error: no viable alternative at input 'module top ();\n`', `MACRO1 // ILLEGAL: b and c omitted, no default for c ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.5.1--define-expansion_12.sv:19:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_12.sv:20: Syntax error: extraneous input 'endmodule' expecting , +endmodule +^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.5.1--define-expansion_12.sv:20:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 1 [WARNING] : 0 [ NOTE] : 0 @@ -2131,8 +2164,11 @@ ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_6.sv [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_6.sv:19: Syntax error: no viable alternative at input 'module top ();\n`', `D ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.5.1--define-expansion_6.sv:19:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_6.sv:20: Syntax error: extraneous input 'endmodule' expecting , +endmodule +^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.5.1--define-expansion_6.sv:20:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 1 [WARNING] : 0 [ NOTE] : 0 @@ -2319,8 +2355,11 @@ Processing: -cd chapter-22 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.3--resetall_illegal.sv:19: Syntax error: no viable alternative at input 'module top ();\n`', `resetall ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.3--resetall_illegal.sv:19:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.3--resetall_illegal.sv:20: Syntax error: extraneous input 'endmodule' expecting , +endmodule +^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.3--resetall_illegal.sv:20:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 1 [WARNING] : 0 [ NOTE] : 0 @@ -4464,8 +4503,14 @@ Processing: -cd chapter-6 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.23--type_op_compare.sv:18:19: Syntax error: no viable alternative at input 'module top #( parameter type T = type(logic[11:0]) )\n ();\n initial begin\n case (type(T))', case (type(T)) ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.23--type_op_compare.sv:18:19:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.23--type_op_compare.sv:15:51: Syntax error: mismatched input ')' expecting ';', +module top #( parameter type T = type(logic[11:0]) ) + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.23--type_op_compare.sv:15:51:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.23--type_op_compare.sv:17:3: Syntax error: mismatched input 'initial' expecting , + initial begin + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.23--type_op_compare.sv:17:3:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -4785,8 +4830,17 @@ Processing: -cd chapter-6 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:7: Syntax error: no viable alternative at input 'module top();\n\tlogic vectored', logic vectored [15:0] a = 0; ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:7:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:7: Syntax error: mismatched input 'vectored' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + logic vectored [15:0] a = 0; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:7:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:23: Syntax error: missing ';' at 'a', + logic vectored [15:0] a = 0; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:23:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:19:1: Syntax error: mismatched input 'assign' expecting , + assign a[1] = 1; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:19:1:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 4 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -8217,8 +8271,35 @@ Processing: -cd chapter-18 -I../../../UVM/1800.2-2017-1.0/src/ ../../../UVM/1800 [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:32:20: Syntax error: extraneous input ';' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, 'default', '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'endcase', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, 0 : zero; ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7368:20:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:33:21: Syntax error: extraneous input ';' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, 'default', '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'endcase', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + 1 : first; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7369:21:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:34:12: Syntax error: mismatched input '2' expecting {'virtual', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'void', DOLLAR_UNIT, 'endsequence', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + 2 : second; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7370:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:35:12: Syntax error: extraneous input 'default' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + default : third; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7371:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:36:8: Syntax error: extraneous input 'endcase' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + endcase; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7372:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:37:19: Syntax error: no viable alternative at input '{ x =', + zero : { x = 0; }; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7373:19:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:37:24: Syntax error: extraneous input '}' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + zero : { x = 0; }; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7373:24:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:38:20: Syntax error: no viable alternative at input '{ x =', + first : { x = 10; }; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7374:20:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:38:26: Syntax error: extraneous input '}' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + first : { x = 10; }; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7374:26:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:39:21: Syntax error: no viable alternative at input '{ x =', + second : { x = 2; }; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7375:21:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 13 [ NOTE] : 0 @@ -8435,8 +8516,35 @@ Processing: -cd chapter-18 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:20:18: Syntax error: extraneous input ';' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, 'default', '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'endcase', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, 0 : zero; ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:20:18:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:21:19: Syntax error: extraneous input ';' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, 'default', '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'endcase', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + 1 : first; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:21:19:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:22:10: Syntax error: mismatched input '2' expecting {'virtual', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'void', DOLLAR_UNIT, 'endsequence', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + 2 : second; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:22:10:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:23:10: Syntax error: extraneous input 'default' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', 'endfunction', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + default : third; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:23:10:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:24:6: Syntax error: extraneous input 'endcase' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', 'endfunction', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + endcase; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:24:6:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:25:18: Syntax error: no viable alternative at input '{ x =', + zero2 : { x = 0; }; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:25:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:25:23: Syntax error: extraneous input '}' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', 'endfunction', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + zero2 : { x = 0; }; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:25:23:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:26:18: Syntax error: no viable alternative at input '{ x =', + first : { x = 10; }; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:26:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:26:24: Syntax error: extraneous input '}' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', 'endfunction', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + first : { x = 10; }; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:26:24:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:27:19: Syntax error: no viable alternative at input '{ x =', + second : { x = 2; }; + ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:27:19:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -8839,7 +8947,7 @@ Processing: -cd chapter-25 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - [ NOTE] : 0 Processed 1134 tests. [ FATAL] : 0 -[ SYNTAX] : 39 +[ SYNTAX] : 75 [ ERROR] : 144 [WARNING] : 1762 [ NOTE] : 0 diff --git a/third_party/tests/Icarus/Icarus.log b/third_party/tests/Icarus/Icarus.log index ecf0c87c14..16b73bd420 100644 --- a/third_party/tests/Icarus/Icarus.log +++ b/third_party/tests/Icarus/Icarus.log @@ -562,8 +562,20 @@ Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -t [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/specify_01.v:13:9: Syntax error: no viable alternative at input '(clk,d =>', (clk,d => q) = (tR_clk_q,tF_clk_q); ^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/specify_01.v:13:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/specify_01.v:13:17: Syntax error: extraneous input '(' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + (clk,d => q) = (tR_clk_q,tF_clk_q); + ^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/specify_01.v:13:17:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/specify_01.v:13:26: Syntax error: mismatched input ',' expecting '=', + (clk,d => q) = (tR_clk_q,tF_clk_q); + ^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/specify_01.v:13:26:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/specify_01.v:13:35: Syntax error: mismatched input ')' expecting '=', + (clk,d => q) = (tR_clk_q,tF_clk_q); + ^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/specify_01.v:13:35:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/specify_01.v:14: Syntax error: extraneous input 'endspecify' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, +endspecify +^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/specify_01.v:14:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 5 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1865,8 +1877,11 @@ Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -t [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/escape2a.v:14: Syntax error: no viable alternative at input 'module part1 (\n#~@6A_A#~@,\n#~@6Y_A#~@,\nVCC ,\nGND ,\n#~@6A_B#~@,\n#~@6Y_B#~@,\n#~@6A_C#~@,\n#~@6Y_C#~@,\n#~@6A_D#~@,\n#~@6Y_D#~@,\n#~@6A_E#~@,\n// note: there is not a space character before the nl below\n\', \6Y_E ^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/escape2a.v:14:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/escape2a.v:17: Syntax error: mismatched input 'input' expecting , +input #~@6A_A#~@; +^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/escape2a.v:17:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -2251,8 +2266,11 @@ Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -t [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/escape2b.v:15: Syntax error: no viable alternative at input 'module part2 (\n#~@6A_A#~@,\n#~@6Y_A#~@,\nVCC ,\nGND ,\n#~@6A_B#~@,\n#~@6Y_B#~@,\n#~@6A_C#~@,\n#~@6Y_C#~@,\n#~@6A_D#~@,\n#~@6Y_D#~@,\n#~@6A_E#~@,\n// note: there is not a space character before the nl below\n// no space character after nl also\n\', \6Y_E ^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/escape2b.v:15:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/escape2b.v:18: Syntax error: mismatched input 'input' expecting , +input #~@6A_A#~@; +^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/escape2b.v:18:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -4220,7 +4238,7 @@ Processing: -cd contrib +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -ti [ NOTE] : 0 Processed 697 tests. [ FATAL] : 0 -[ SYNTAX] : 3 +[ SYNTAX] : 9 [ ERROR] : 12 [WARNING] : 15 [ NOTE] : 0 diff --git a/third_party/tests/UtdSV/UtdSV.log b/third_party/tests/UtdSV/UtdSV.log index f434920b46..a81052464e 100644 --- a/third_party/tests/UtdSV/UtdSV.log +++ b/third_party/tests/UtdSV/UtdSV.log @@ -3365,8 +3365,14 @@ Processing: -cd . +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescal [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/UtdSV/ifdef-2.v:17: Syntax error: extraneous input '"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, "first_block, second_block not defined, ^-- ${SURELOG_DIR}/build/regression/UtdSV/slpp_all/lib/work/ifdef-2.v:17:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/UtdSV/ifdef-2.v:17:38: Syntax error: mismatched input ',' expecting '(', +"first_block, second_block not defined, + ^-- ${SURELOG_DIR}/build/regression/UtdSV/slpp_all/lib/work/ifdef-2.v:17:38:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/UtdSV/ifdef-2.v:18: Syntax error: mismatched input '"' expecting {'(', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, +"); +^-- ${SURELOG_DIR}/build/regression/UtdSV/slpp_all/lib/work/ifdef-2.v:18:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 2 [WARNING] : 0 [ NOTE] : 0 @@ -5092,7 +5098,7 @@ Processing: -cd . +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescal [ NOTE] : 0 Processed 300 tests. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 18 [WARNING] : 3269 [ NOTE] : 0 diff --git a/third_party/tests/Verilator/Verilator.log b/third_party/tests/Verilator/Verilator.log index 83aa16442a..c4b2d1ec88 100644 --- a/third_party/tests/Verilator/Verilator.log +++ b/third_party/tests/Verilator/Verilator.log @@ -236,8 +236,11 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_var_dup_bad.v:65:3: Syntax error: extraneous input 'output' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, output bad_reout_port; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_var_dup_bad.v:65:3:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_var_dup_bad.v:65:24: Syntax error: no viable alternative at input 'bad_reout_port;', + output bad_reout_port; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_var_dup_bad.v:65:24:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -346,8 +349,32 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:14:7: Syntax error: no viable alternative at input 'sub\n #(,', #(, // Not found ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:14:7:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:15:15: Syntax error: no viable alternative at input '(1', + .NEXIST(1), // Not found + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:15:15:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:16:10: Syntax error: no viable alternative at input '(2', + .P(2), + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:16:10:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:17:10: Syntax error: no viable alternative at input '(3', + .P(3)) // Dup + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:17:10:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:18:8: Syntax error: no viable alternative at input '(.', + sub (.o(o), + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:18:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:18:12: Syntax error: extraneous input ')' expecting ',', + sub (.o(o), + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:18:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:19:8: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .i(i), + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:19:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:20:8: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .i(i2), // Dup + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:20:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:21:8: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .nexist(i2) // Not found + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:21:8:. +[ FATAL] : 0 +[ SYNTAX] : 9 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -410,9 +437,12 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_display.v:11:39: Syntax error: no viable alternative at input 'module t ();\n\n\n SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls and sformat conversion."', SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls and sformat conversion." ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_display.v:11:39:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_display.v:11:39: Syntax error: mismatched input '"Only Verilator supports PLI-ish DPI calls and sformat conversion."' expecting , + SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls and sformat conversion." + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_display.v:11:39:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_display.v:11: Unknown macro "error". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 2 [WARNING] : 0 [ NOTE] : 0 @@ -610,8 +640,14 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_flag_language.v:10:11: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n\n // See also t_preproc_kwd.v\n\n integer bit', integer bit; initial bit = 1; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_flag_language.v:10:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_flag_language.v:10:11: Syntax error: mismatched input 'bit' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + integer bit; initial bit = 1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_flag_language.v:10:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_flag_language.v:10:16: Syntax error: mismatched input 'initial' expecting , + integer bit; initial bit = 1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_flag_language.v:10:16:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -988,8 +1024,35 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter.v:10:13: Syntax error: no viable alternative at input 'example line 10', example line 10; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:10:13:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter.v:11:13: Syntax error: no viable alternative at input 'example line 11', +example line 11; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:11:13:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:6:9: Syntax error: no viable alternative at input 'inc line 6', +inc line 6; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:18:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:7:9: Syntax error: no viable alternative at input 'inc line 7', +inc line 7; // example_lint_off_line FOO + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:19:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:8:9: Syntax error: no viable alternative at input 'inc line 8', +inc line 8; // example_lint_off_line BAR + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:20:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:9:9: Syntax error: no viable alternative at input 'inc line 9', +inc line 9; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:21:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:6:9: Syntax error: no viable alternative at input 'inc line 6', +inc line 6; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:29:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:7:9: Syntax error: no viable alternative at input 'inc line 7', +inc line 7; // example_lint_off_line FOO + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:30:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:8:9: Syntax error: no viable alternative at input 'inc line 8', +inc line 8; // example_lint_off_line BAR + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:31:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:9:9: Syntax error: no viable alternative at input 'inc line 9', +inc line 9; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:32:9:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1188,8 +1251,14 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_modportlist.v:10:26: Syntax error: no viable alternative at input 'my_module m(.clk(clk), iface', my_module m(.clk(clk), iface); ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_modportlist.v:10:26:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_modportlist.v:10:15: Syntax error: no viable alternative at input '(.', + my_module m(.clk(clk), iface); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_modportlist.v:10:15:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_modportlist.v:10:23: Syntax error: extraneous input ')' expecting ',', + my_module m(.clk(clk), iface); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_modportlist.v:10:23:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1298,8 +1367,14 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_const_dec_mixed_bad.v:8:35: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n\n parameter [200:0] MIXED = 32'dx_1', parameter [200:0] MIXED = 32'dx_1; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_const_dec_mixed_bad.v:8:35:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_const_dec_mixed_bad.v:8:35: Syntax error: extraneous input '1' expecting ';', + parameter [200:0] MIXED = 32'dx_1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_const_dec_mixed_bad.v:8:35:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_const_dec_mixed_bad.v:10: Syntax error: extraneous input 'endmodule' expecting , +endmodule +^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_const_dec_mixed_bad.v:10:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1319,8 +1394,11 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_trace_primitive.v:34: Syntax error: extraneous input 'assign' expecting {'input', 'output', 'reg', '(*', 'table', 'initial'}, assign b = ~a; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_trace_primitive.v:34:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_trace_primitive.v:35: Syntax error: mismatched input 'endprimitive' expecting , +endprimitive +^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_trace_primitive.v:35:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1334,8 +1412,20 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum.v:33:16: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n\n localparam FIVE = 5;\n\n enum { e0,\n\t e1,\n\t e3=3,\n\t e5=FIVE,\n\t e10_[2] = 10,\n\t e12,\n\t e20_[5:7] = 25,\n\t e20_z,\n\t e30_[7:5] = 30,\n\t e30_z\n\t } EN;\n\n enum {\n\t z5 = e5\n\t } ZN;\n\n typedef enum [', typedef enum [2:0] { ONES=~0 } three_t; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum.v:33:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum.v:33:16: Syntax error: no viable alternative at input 'enum [', + typedef enum [2:0] { ONES=~0 } three_t; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum.v:33:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum.v:33:16: Syntax error: mismatched input '[' expecting {'{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + typedef enum [2:0] { ONES=~0 } three_t; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum.v:33:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum.v:33:22: Syntax error: mismatched input '{' expecting ';', + typedef enum [2:0] { ONES=~0 } three_t; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum.v:33:22:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum.v:41:3: Syntax error: mismatched input 'initial' expecting , + initial begin + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum.v:41:3:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 5 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1513,8 +1603,14 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing.v:10:21: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n wire ok = 1'b0;\n // verilator lint_off PINNOCONNECT\n // verilator lint_off PINCONNECTEMPTY\n sub sub (.ok(ok), ,', sub sub (.ok(ok), , .nc()); ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing.v:10:21:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing.v:10:11: Syntax error: no viable alternative at input 'sub sub (', + sub sub (.ok(ok), , .nc()); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing.v:10:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing.v:13: Syntax error: mismatched input 'endmodule' expecting , +endmodule +^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing.v:13:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1539,8 +1635,35 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:29:16: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at ';', integer signed; initial signed = 1; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:29:16:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:29:26: Syntax error: mismatched input 'signed' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + integer signed; initial signed = 1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:29:26:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:29:33: Syntax error: mismatched input '=' expecting {'[', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + integer signed; initial signed = 1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:29:33:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:29:35: Syntax error: mismatched input '1' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + integer signed; initial signed = 1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:29:35:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:35:10: Syntax error: mismatched input 'bit' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + integer bit; initial bit = 1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:35:10:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:35:23: Syntax error: mismatched input 'bit' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + integer bit; initial bit = 1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:35:23:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:35:27: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', + integer bit; initial bit = 1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:35:27:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:41:10: Syntax error: mismatched input 'final' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + integer final; initial final = 1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:41:10:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:41:25: Syntax error: mismatched input 'final' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + integer final; initial final = 1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:41:25:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:41:31: Syntax error: mismatched input '=' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + integer final; initial final = 1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:41:31:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 1 [WARNING] : 0 [ NOTE] : 0 @@ -1600,8 +1723,11 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_implicit_def_bad.v:14: Syntax error: extraneous input '`default_nettype' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, `default_nettype none ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_implicit_def_bad.v:14:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_implicit_def_bad.v:15:3: Syntax error: mismatched input 'assign' expecting , + assign imp_err = 1'b1; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_implicit_def_bad.v:15:3:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 1 [WARNING] : 0 [ NOTE] : 0 @@ -1647,8 +1773,14 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing_bad.v:8:21: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n wire ok = 1'b0;\n sub sub (.ok(ok), ,', sub sub (.ok(ok), , .nc()); ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing_bad.v:8:21:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing_bad.v:8:11: Syntax error: no viable alternative at input 'sub sub (', + sub sub (.ok(ok), , .nc()); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing_bad.v:8:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing_bad.v:9: Syntax error: mismatched input 'endmodule' expecting , +endmodule +^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing_bad.v:9:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1707,8 +1839,26 @@ ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:17:9: No default value [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:21:3: Syntax error: no viable alternative at input '$display("left side: \"right side\"" // The 'left' as the variable name shouldn't match the "left" in the `" string\n initial', initial begin ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:33:3:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:20:15: Syntax error: no viable alternative at input '("left side: \"right side\""', + $display("left side: \"right side\"" // The 'left' as the variable name shouldn't match the "left" in the `" string + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:32:15:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:31: Syntax error: extraneous input ')' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', ':', 'virtual', 'type', 'bind', 'const', 'static', 'local', 'super', '{', '->', 'if', 'foreach', 'automatic', 'localparam', 'parameter', 'import', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', 'var', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', 'let', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, +); +^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:35:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:39:15: Syntax error: no viable alternative at input '$display(`', + $display(`"standalone`"); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:43:15:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:39:14: Syntax error: mismatched input '(' expecting ';', + $display(`"standalone`"); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:43:14:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:39:16: Syntax error: mismatched input '"standalone`"' expecting Simple_identifier, + $display(`"standalone`"); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:43:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:49:6: Syntax error: mismatched input '$' expecting , + $display("Line %0d File \"%s\"",49,"${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v"); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:53:6:. +[ FATAL] : 0 +[ SYNTAX] : 7 [ ERROR] : 1 [WARNING] : 1 [ NOTE] : 0 @@ -1820,8 +1970,17 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_slice_bad.v:38:30: Syntax error: mismatched input '[' expecting '=', assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_slice_bad.v:38:30:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_slice_bad.v:38:41: Syntax error: extraneous input '=' expecting {'[', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_slice_bad.v:38:41:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_slice_bad.v:38:53: Syntax error: mismatched input '?' expecting ';', + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_slice_bad.v:38:53:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_slice_bad.v:38:82: Syntax error: extraneous input ':' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_slice_bad.v:38:82:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 4 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1883,8 +2042,11 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_multi_ref_bad.v:18:18: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n reg dimn;\n reg [1:0] dim0;\n reg [1:0] dim1 [1:0];\n reg [1:0] dim2 [1:0][1:0];\n reg dim0nv[1:0];\n\n initial begin\n dimn[1:0] = 0; // Bad: Not ranged\n dim0[1][1] = 0; // Bad: Not arrayed\n dim1[1][1][1] = 0; // Bad: Not arrayed to right depth\n dim2[1][1][1] = 0; // OK\n dim2[0 +: 1][', dim2[0 +: 1][1] = 0; // Bad: Range on non-bits ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_multi_ref_bad.v:18:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_multi_ref_bad.v:13:3: Syntax error: mismatched input 'initial' expecting , + initial begin + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_multi_ref_bad.v:13:3:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -2004,8 +2166,14 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_langext_order.v:10:15: Syntax error: no viable alternative at input 'input do', module t(input do); ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_langext_order.v:10:15:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_langext_order.v:11:29: Syntax error: no viable alternative at input 't_langext_order_sub sub (.do', + t_langext_order_sub sub (.do(do)); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_langext_order.v:11:29:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_langext_order.v:11:28: Syntax error: no viable alternative at input '(.', + t_langext_order_sub sub (.do(do)); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_langext_order.v:11:28:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -2119,9 +2287,12 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_sys.v:15:39: Syntax error: no viable alternative at input 'module t ();\n\n\n SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls."', SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls." ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_sys.v:15:39:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_sys.v:15:39: Syntax error: mismatched input '"Only Verilator supports PLI-ish DPI calls."' expecting , + SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls." + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_sys.v:15:39:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_sys.v:15: Unknown macro "error". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 2 [WARNING] : 0 [ NOTE] : 0 @@ -2260,8 +2431,11 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat2.v:85:3: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input clk; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat2.v:85:3:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat2.v:85:18: Syntax error: no viable alternative at input 'clk;', + input clk; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat2.v:85:18:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -2547,8 +2721,11 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_hierarchy_identifier.v:30:26: Syntax error: mismatched input '\' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, if (cnt==SIZE) begin : \0escaped___name ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_hierarchy_identifier.v:30:26:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_hierarchy_identifier.v:33:3: Syntax error: extraneous input 'end' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + end : \0escaped___name + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_hierarchy_identifier.v:33:3:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -2989,8 +3166,11 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_attr_parenstar.v:32:12: Syntax error: no viable alternative at input '@ (*', always @ (* ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_attr_parenstar.v:32:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_attr_parenstar.v:35:3: Syntax error: extraneous input 'end' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + end + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_attr_parenstar.v:35:3:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -3136,8 +3316,14 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_var_bad_sv.v:7:7: Syntax error: mismatched input 'do' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, reg do; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_var_bad_sv.v:7:7:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_var_bad_sv.v:8:13: Syntax error: no viable alternative at input 'mod mod (.do', + mod mod (.do(bar)); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_var_bad_sv.v:8:13:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_var_bad_sv.v:8:12: Syntax error: no viable alternative at input '(.', + mod mod (.do(bar)); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_var_bad_sv.v:8:12:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -3428,9 +3614,12 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_lib_library.v:7:10: Syntax error: no viable alternative at input '[SURELOG_MACRO_NOT_DEFINED:WIDTH!!!', input [SURELOG_MACRO_NOT_DEFINED:WIDTH!!! -1:0] a; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_lib_library.v:7:10:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_lib_library.v:7:45: Syntax error: extraneous input '-' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + input [SURELOG_MACRO_NOT_DEFINED:WIDTH!!! -1:0] a; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_lib_library.v:7:45:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_lib_library.v:7: Unknown macro "WIDTH". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 2 [WARNING] : 0 [ NOTE] : 0 @@ -3927,8 +4116,14 @@ ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc.v:97:9: No default value fo [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_inc2.vh:4:8: Syntax error: no viable alternative at input 'At file "${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_inc2.vh"', At file "${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_inc2.vh" line 4 ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc.v:10:8:. -[ FATAL] : 0 -[ SYNTAX] : 4 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc.v:29:4: Syntax error: no viable alternative at input 'text.', +text. + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc.v:35:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc.v:84:1: Syntax error: mismatched input '$' expecting , + $c("Zap(\"","bug2","\");"); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc.v:100:1:. +[ FATAL] : 0 +[ SYNTAX] : 6 [ ERROR] : 28 [WARNING] : 22 [ NOTE] : 0 @@ -4015,8 +4210,11 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat6.v:97:3: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input clk; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat6.v:97:3:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat6.v:97:18: Syntax error: no viable alternative at input 'clk;', + input clk; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat6.v:97:18:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -4390,9 +4588,12 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_circdef_bad.v:13:18: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '(*', '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, typedef logic [12-SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! +: SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! -1:0] d_t; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_circdef_bad.v:13:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_circdef_bad.v:13:61: Syntax error: mismatched input '+:' expecting , +typedef logic [12-SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! +: SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! -1:0] d_t; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_circdef_bad.v:13:61:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_circdef_bad.v:13: Unknown macro "SEL_NUM_BITS". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 4 [WARNING] : 0 [ NOTE] : 0 @@ -4599,8 +4800,11 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat5.v:84:3: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input clk; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat5.v:84:3:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat5.v:84:18: Syntax error: no viable alternative at input 'clk;', + input clk; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat5.v:84:18:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -4628,10 +4832,13 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_undefineall.v:9:37: Syntax error: extraneous input '"Test setup error, PREDEF_COMMAND_LINE pre-missing"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, SURELOG_MACRO_NOT_DEFINED:error!!! "Test setup error, PREDEF_COMMAND_LINE pre-missing" ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_undefineall.v:9:37:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_undefineall.v:14:37: Syntax error: extraneous input '"Deleted too much, no PREDEF_COMMAND_LINE"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + SURELOG_MACRO_NOT_DEFINED:error!!! "Deleted too much, no PREDEF_COMMAND_LINE" + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_undefineall.v:14:37:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_undefineall.v:9: Unknown macro "error". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_undefineall.v:14: Unknown macro "error". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 4 [WARNING] : 0 [ NOTE] : 0 @@ -4646,9 +4853,18 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_down_gen.v:75:52: Syntax error: missing '(' at 'choke', SURELOG_MACRO_NOT_DEFINED:error!!! Commercial sims choke on cross ref here ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_down_gen.v:75:52:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_down_gen.v:75:61: Syntax error: mismatched input 'cross' expecting '(', +SURELOG_MACRO_NOT_DEFINED:error!!! Commercial sims choke on cross ref here + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_down_gen.v:75:61:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_down_gen.v:76:10: Syntax error: missing '(' at '.', + isub.g.value = i_value; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_down_gen.v:76:10:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_down_gen.v:76:12: Syntax error: mismatched input '.' expecting ')', + isub.g.value = i_value; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_down_gen.v:76:12:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_down_gen.v:75: Unknown macro "error". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 4 [ ERROR] : 2 [WARNING] : 0 [ NOTE] : 0 @@ -4907,8 +5123,23 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:15:16: Syntax error: no viable alternative at input 'enum [', typedef enum [3:0] { ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:15:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:15:16: Syntax error: mismatched input '[' expecting {'{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + typedef enum [3:0] { + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:15:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:15:22: Syntax error: mismatched input '{' expecting ';', + typedef enum [3:0] { + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:15:22:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:16:15: Syntax error: mismatched input '1' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + E01 = 1, + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:16:15:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:17:15: Syntax error: mismatched input '3' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + E03 = 3, + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:17:15:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:18:15: Syntax error: mismatched input '4' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + E04 = 4 + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:18:15:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 6 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -4916,8 +5147,14 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_in_inc_bad_2.vh:8:6: Syntax error: mismatched input 'if' expecting '(', if if if; ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_in_inc_bad.v:18:6:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_in_inc_bad_2.vh:8:9: Syntax error: mismatched input 'if' expecting '(', + if if if; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_in_inc_bad.v:18:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_in_inc_bad_2.vh:8:11: Syntax error: mismatched input ';' expecting '(', + if if if; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_in_inc_bad.v:18:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5164,13 +5401,25 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:49: Syntax error: extraneous input '#' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, #include "t_extend_class_c.h" // Header for contained object ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_extend_class.v:49:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:51:19: Syntax error: no viable alternative at input 't_extend_class_c*', + t_extend_class_c* m_myobjp; // Pointer to object we are embedding + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_extend_class.v:51:19:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:53:12: Syntax error: no viable alternative at input 'm_myobjp =', + m_myobjp = new t_extend_class_c(); // Construct contained object + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_extend_class.v:53:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:53:14: Syntax error: extraneous input 'new' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + m_myobjp = new t_extend_class_c(); // Construct contained object + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_extend_class.v:53:14:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:53:34: Syntax error: missing '=' at '(', + m_myobjp = new t_extend_class_c(); // Construct contained object + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_extend_class.v:53:34:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:48: Unknown macro "systemc_header". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:50: Unknown macro "systemc_interface". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:52: Unknown macro "systemc_ctor". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:54: Unknown macro "systemc_dtor". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:56: Unknown macro "verilog". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 5 [ ERROR] : 10 [WARNING] : 0 [ NOTE] : 0 @@ -5186,9 +5435,12 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_var.v:67:2: Syntax error: no viable alternative at input 'module sub (/*AUTOARG*/\n // Outputs\n fr_a, fr_b, fr_chk,\n // Inputs\n in\n );\n\nSURELOG_MACRO_NOT_DEFINED:systemc_imp_header!!! \n void', void mon_class_name(const char* namep); ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_var.v:67:2:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_var.v:67:2: Syntax error: mismatched input 'void' expecting , + void mon_class_name(const char* namep); + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_var.v:67:2:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_var.v:66: Unknown macro "systemc_imp_header". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 3 [WARNING] : 0 [ NOTE] : 0 @@ -5288,8 +5540,11 @@ Processing: -cd t_sv_cpu_code +incdir+. -parse -noelab -nocache -nobuiltin -nono [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/ports.sv:44:9: Syntax error: extraneous input 'SURELOG_MACRO_NOT_DEFINED:PACKED!!!' expecting {'{', 'packed'}, struct SURELOG_MACRO_NOT_DEFINED:PACKED!!! ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_sv_cpu_code/ports.sv:44:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/ports.sv:49:11: Syntax error: extraneous input 'SURELOG_MACRO_NOT_DEFINED:PACKED!!!' expecting {'{', 'packed'}, + struct SURELOG_MACRO_NOT_DEFINED:PACKED!!! + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_sv_cpu_code/ports.sv:49:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 2 [WARNING] : 0 [ NOTE] : 0 @@ -5317,6 +5572,9 @@ Processing: -cd t_sv_cpu_code +incdir+. -parse -noelab -nocache -nobuiltin -nono [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:18:6: Syntax error: no viable alternative at input ''{\n SURELOG_MACRO_NOT_DEFINED:LDI!!!', SURELOG_MACRO_NOT_DEFINED:LDI!!! ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_sv_cpu_code/rom.sv:18:6:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:36:6: Syntax error: mismatched input '}' expecting , + }; + ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_sv_cpu_code/rom.sv:36:6:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:18: Unknown macro "LDI". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:19: Unknown macro "LDI". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:20: Unknown macro "LDI". @@ -5332,7 +5590,7 @@ Processing: -cd t_sv_cpu_code +incdir+. -parse -noelab -nocache -nobuiltin -nono [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:33: Unknown macro "JMP". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:35: Unknown macro "EOP". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 28 [WARNING] : 0 [ NOTE] : 0 @@ -5391,7 +5649,7 @@ Processing: -cd t_sv_bus_mux_demux +incdir+. -parse -noelab -nocache -nobuiltin [ NOTE] : 0 Processed 837 tests. [ FATAL] : 0 -[ SYNTAX] : 54 +[ SYNTAX] : 140 [ ERROR] : 153 [WARNING] : 43 [ NOTE] : 0 diff --git a/third_party/tests/Yosys/Yosys.log b/third_party/tests/Yosys/Yosys.log index 34c2637241..6298676aad 100644 --- a/third_party/tests/Yosys/Yosys.log +++ b/third_party/tests/Yosys/Yosys.log @@ -844,8 +844,11 @@ Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -tim [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err02.v:3:16: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', input integer [3:0]x ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err02.v:3:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err02.v:3:21: Syntax error: extraneous input 'x' expecting ')', + input integer [3:0]x + ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err02.v:3:21:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -853,8 +856,14 @@ Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -tim [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err10.v:2:18: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', parameter integer [2:0]x=0; ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err10.v:2:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err10.v:2:23: Syntax error: missing ';' at 'x', +parameter integer [2:0]x=0; + ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err10.v:2:23:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err10.v:2:25: Syntax error: mismatched input '0' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, +parameter integer [2:0]x=0; + ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err10.v:2:25:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -862,8 +871,11 @@ Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -tim [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err05.v:2: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input x[2:0]; ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err05.v:2:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err05.v:2:12: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at ';', +input x[2:0]; + ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err05.v:2:12:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -879,8 +891,11 @@ Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -tim [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err01.v:2:8: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', integer [31:0]w; ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err01.v:2:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err01.v:2:14: Syntax error: extraneous input 'w' expecting ';', +integer [31:0]w; + ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err01.v:2:14:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -981,8 +996,11 @@ Processing: -cd various +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -ti [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/various/shregmap.v:15:7: Syntax error: no viable alternative at input 'module \', module \$__SHREG_DFF_P_ (input C, D, output Q); ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/various/shregmap.v:15:7:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/various/shregmap.v:19: Syntax error: mismatched input 'always' expecting , +always @(posedge C) +^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/various/shregmap.v:19:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1781,7 +1799,7 @@ Processing: -cd simple +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -tim [ NOTE] : 0 Processed 253 tests. [ FATAL] : 0 -[ SYNTAX] : 10 +[ SYNTAX] : 16 [ ERROR] : 3 [WARNING] : 229 [ NOTE] : 0 diff --git a/third_party/tests/YosysTestSuite/YosysTestSuite.log b/third_party/tests/YosysTestSuite/YosysTestSuite.log index 32e8f6d59d..122ba407de 100644 --- a/third_party/tests/YosysTestSuite/YosysTestSuite.log +++ b/third_party/tests/YosysTestSuite/YosysTestSuite.log @@ -153,8 +153,11 @@ Processing: -cd asicworld code_verilog_tutorial_first_counter_tb.v -writepp -par [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_first_counter_tb.v:9:16: Syntax error: no viable alternative at input 'module testbench();\n// Declare inputs as regs and outputs as wires\nreg clock = 1, reset = 0, enable = 0;\nwire [3:0] counter_out;\ninteger file;\n\n// Initialize all variables\ninitial begin \n file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!!', file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! ); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_first_counter_tb.v:9:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_first_counter_tb.v:8: Syntax error: mismatched input 'initial' expecting , +initial begin +^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_first_counter_tb.v:8:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 1 [WARNING] : 0 [ NOTE] : 0 @@ -217,8 +220,11 @@ Processing: -cd asicworld code_verilog_tutorial_fsm_full_tb.v -writepp -parse -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_fsm_full_tb.v:10:16: Syntax error: no viable alternative at input 'module testbench();\nreg clock = 0 , reset ;\nreg req_0 , req_1 , req_2 , req_3; \nwire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;\ninteger file;\n\ninitial begin\n // $dumpfile("testbench.vcd");\n // $dumpvars(0, testbench);\n file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!!', file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! ); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_fsm_full_tb.v:10:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_fsm_full_tb.v:7: Syntax error: mismatched input 'initial' expecting , +initial begin +^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_fsm_full_tb.v:7:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 1 [WARNING] : 0 [ NOTE] : 0 @@ -353,9 +359,12 @@ Processing: -cd asicworld code_verilog_tutorial_counter_tb.v -writepp -parse -no [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_counter_tb.v:34:14: Syntax error: mismatched input '(' expecting ';', file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! ); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_counter_tb.v:34:14:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_counter_tb.v:34:52: Syntax error: extraneous input ')' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! ); + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_counter_tb.v:34:52:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_counter_tb.v:34: Unknown macro "outfile". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 2 [WARNING] : 0 [ NOTE] : 0 @@ -526,8 +535,11 @@ Processing: -cd asicworld code_hdl_models_arbiter_tb.v -writepp -parse -nocache [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_hdl_models_arbiter_tb.v:22:16: Syntax error: no viable alternative at input 'module testbench ();\n\nreg clk = 0;\nreg rst = 1;\nreg req3 = 0;\nreg req2 = 0;\nreg req1 = 0;\nreg req0 = 0;\nwire gnt3; \nwire gnt2; \nwire gnt1; \nwire gnt0; \n\n// Clock generator\nalways #1 clk = ~clk;\ninteger file;\n\nalways @(posedge clk)\n $fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0});\n\ninitial begin\n file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!!', file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! ); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_hdl_models_arbiter_tb.v:22:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_hdl_models_arbiter_tb.v:15: Syntax error: mismatched input 'always' expecting , +always #1 clk = ~clk; +^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_hdl_models_arbiter_tb.v:15:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 1 [WARNING] : 0 [ NOTE] : 0 @@ -574,8 +586,11 @@ Processing: -cd opt opt_expr_cmp.v -writepp -parse -nocache -nobuiltin -nonote - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/opt/opt_expr_cmp.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/opt/opt_expr_cmp.v:1:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/opt/opt_expr_cmp.v:2:2: Syntax error: mismatched input 'input' expecting , + input [3:0] a; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/opt/opt_expr_cmp.v:2:2:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -861,8 +876,11 @@ Processing: -cd errors syntax_err02.v -writepp -parse -nocache -nobuiltin -nonot [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err02.v:3:16: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', input integer [3:0]x ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err02.v:3:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err02.v:3:21: Syntax error: extraneous input 'x' expecting ')', + input integer [3:0]x + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err02.v:3:21:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -870,8 +888,14 @@ Processing: -cd errors syntax_err10.v -writepp -parse -nocache -nobuiltin -nonot [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err10.v:2:18: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', parameter integer [2:0]x=0; ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err10.v:2:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err10.v:2:23: Syntax error: missing ';' at 'x', +parameter integer [2:0]x=0; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err10.v:2:23:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err10.v:2:25: Syntax error: mismatched input '0' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, +parameter integer [2:0]x=0; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err10.v:2:25:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -879,8 +903,11 @@ Processing: -cd errors syntax_err05.v -writepp -parse -nocache -nobuiltin -nonot [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err05.v:2: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input x[2:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err05.v:2:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err05.v:2:12: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at ';', +input x[2:0]; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err05.v:2:12:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -896,8 +923,11 @@ Processing: -cd errors syntax_err01.v -writepp -parse -nocache -nobuiltin -nonot [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err01.v:2:8: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', integer [31:0]w; ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err01.v:2:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err01.v:2:14: Syntax error: extraneous input 'w' expecting ';', +integer [31:0]w; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err01.v:2:14:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -983,8 +1013,35 @@ Processing: -cd svinterfaces svinterface_at_top_wrapper.v -writepp -parse -nocac [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:16:2: Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, ); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:16:2:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:26:5: Syntax error: no viable alternative at input 'TopModule u_dut (\n .clk(clk),\n .rst(rst),\n .outOther(outOther),\n .sig(sig),\n .flip(flip),\n .passThrough(passThrough),\n .\', + .\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:26:5:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:20:4: Syntax error: no viable alternative at input '(\n .', + .clk(clk), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:20:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:20:12: Syntax error: extraneous input ')' expecting ',', + .clk(clk), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:20:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:21:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .rst(rst), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:21:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:22:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .outOther(outOther), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:22:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:23:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .sig(sig), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:23:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:24:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .flip(flip), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:24:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:25:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .passThrough(passThrough), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:25:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:26:4: Syntax error: mismatched input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:26:4:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -998,8 +1055,11 @@ Processing: -cd various shregmap.v -writepp -parse -nocache -nobuiltin -nonote - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/various/shregmap.v:15:7: Syntax error: no viable alternative at input 'module $', module $__SHREG_DFF_P_(input C, D, output Q); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/various/shregmap.v:15:7:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/various/shregmap.v:19: Syntax error: mismatched input 'always' expecting , +always @(posedge C) +^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/various/shregmap.v:19:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1055,8 +1115,11 @@ Processing: -cd various constmsk_testmap.v -writepp -parse -nocache -nobuiltin - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/various/constmsk_testmap.v:2:25: Syntax error: no viable alternative at input '(* techmap_celltype = "$reduce_or" *)\nmodule my_opt_reduce_or(..', module my_opt_reduce_or(...); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/various/constmsk_testmap.v:2:25:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/various/constmsk_testmap.v:7:4: Syntax error: mismatched input 'input' expecting , + input [A_WIDTH-1:0] A; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/various/constmsk_testmap.v:7:4:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1163,8 +1226,11 @@ Processing: -cd arch/xilinx macc_tb.v -writepp -parse -nocache -nobuiltin -nonot [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/macc_tb.v:8:1: Syntax error: extraneous input 'output' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, output signed [SIZEOUT-1:0] REF_accum_out, accum_out; ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/macc_tb.v:8:1:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/macc_tb.v:9:1: Syntax error: extraneous input 'output' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + output REF_overflow, overflow; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/macc_tb.v:9:1:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1172,8 +1238,17 @@ Processing: -cd arch/xilinx xilinx_srl.v -writepp -parse -nocache -nobuiltin -no [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/xilinx_srl.v:29:7: Syntax error: no viable alternative at input 'module $', module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/xilinx_srl.v:29:7:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/xilinx_srl.v:29:54: Syntax error: extraneous input 'output' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, +module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/xilinx_srl.v:29:54:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/xilinx_srl.v:29:62: Syntax error: extraneous input ')' expecting ';', +module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/xilinx_srl.v:29:62:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/xilinx_srl.v:36: Syntax error: mismatched input 'always' expecting , +always @(posedge C) +^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/xilinx_srl.v:36:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 4 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1379,8 +1454,23 @@ Processing: -cd rpc design.v -writepp -parse -nocache -nobuiltin -nonote -noinfo [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:7:1: Syntax error: no viable alternative at input 'python_inv #(\n\t .width(4)\n\t) inv (\n\t\t.i(i),\n\t\t.o(o),\n\t)', ); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:7:1:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:3:10: Syntax error: no viable alternative at input '(4', + .width(4) + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:3:10:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:5:2: Syntax error: no viable alternative at input '(\n\t\t.', + .i(i), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:5:2:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:5:6: Syntax error: extraneous input ')' expecting ',', + .i(i), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:5:6:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:6:2: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .o(o), + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:6:2:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:7:1: Syntax error: mismatched input ')' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + ); + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:7:1:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 6 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1388,8 +1478,11 @@ Processing: -cd lut map_not.v -writepp -parse -nocache -nobuiltin -nonote -noinf [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_not.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_not.v:1:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_not.v:2:4: Syntax error: mismatched input 'input' expecting , + input a; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_not.v:2:4:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1397,8 +1490,11 @@ Processing: -cd lut map_xor.v -writepp -parse -nocache -nobuiltin -nonote -noinf [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_xor.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_xor.v:1:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_xor.v:2:4: Syntax error: mismatched input 'input' expecting , + input a, b; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_xor.v:2:4:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1406,8 +1502,11 @@ Processing: -cd lut map_cmp.v -writepp -parse -nocache -nobuiltin -nonote -noinf [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_cmp.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_cmp.v:1:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_cmp.v:3:1: Syntax error: mismatched input 'input' expecting , + input [LUT_WIDTH-1:0] a; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_cmp.v:3:1:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1415,8 +1514,11 @@ Processing: -cd lut map_mux.v -writepp -parse -nocache -nobuiltin -nonote -noinf [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_mux.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_mux.v:1:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_mux.v:2:4: Syntax error: mismatched input 'input' expecting , + input a, b, s; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_mux.v:2:4:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1424,8 +1526,11 @@ Processing: -cd lut map_and.v -writepp -parse -nocache -nobuiltin -nonote -noinf [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_and.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_and.v:1:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_and.v:2:4: Syntax error: mismatched input 'input' expecting , + input a, b; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_and.v:2:4:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1433,8 +1538,11 @@ Processing: -cd lut map_or.v -writepp -parse -nocache -nobuiltin -nonote -noinfo [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_or.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_or.v:1:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_or.v:2:4: Syntax error: mismatched input 'input' expecting , + input a, b; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_or.v:2:4:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1922,8 +2030,11 @@ Processing: -cd svtypes typedef_memory_2.sv -writepp -parse -nocache -nobuiltin [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_memory_2.sv:4:1: Syntax error: extraneous input '(' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, (nibble) mem[0:15]; ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_memory_2.sv:4:1:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_memory_2.sv:4:19: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at ';', + (nibble) mem[0:15]; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_memory_2.sv:4:19:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1931,8 +2042,35 @@ Processing: -cd svtypes typedef_param.sv -writepp -parse -nocache -nobuiltin -no [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:9:9: Syntax error: extraneous input '(' expecting {'interface', 'virtual', 'class', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', DOLLAR_UNIT, 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, typedef (int8_t) char_t; ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:9:9:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:9:16: Syntax error: no viable alternative at input 'int8_t)', + typedef (int8_t) char_t; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:9:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:11:11: Syntax error: extraneous input '(' expecting {'virtual', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', DOLLAR_UNIT, 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + parameter (uint2_t) int2 = 2'b10; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:11:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:11:19: Syntax error: mismatched input ')' expecting ';', + parameter (uint2_t) int2 = 2'b10; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:11:19:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:11:28: Syntax error: mismatched input '2'b10' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + parameter (uint2_t) int2 = 2'b10; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:11:28:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:12:12: Syntax error: extraneous input '(' expecting {'virtual', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', DOLLAR_UNIT, 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + localparam (int4_t) int4 = -1; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:12:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:12:19: Syntax error: mismatched input ')' expecting ';', + localparam (int4_t) int4 = -1; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:12:19:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:12:28: Syntax error: mismatched input '-' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + localparam (int4_t) int4 = -1; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:12:28:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:13:12: Syntax error: extraneous input '(' expecting {'virtual', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', DOLLAR_UNIT, 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + localparam (int8_t) int8 = int4; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:13:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:13:19: Syntax error: mismatched input ')' expecting ';', + localparam (int8_t) int8 = int4; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:13:19:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1940,8 +2078,32 @@ Processing: -cd svtypes typedef_scopes.sv -writepp -parse -nocache -nobuiltin -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:6:1: Syntax error: extraneous input '(' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, (outer_uint4_t) u4_i = 8'hA5; ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:6:1:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:6:15: Syntax error: no viable alternative at input 'outer_uint4_t)', + (outer_uint4_t) u4_i = 8'hA5; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:6:15:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:6:24: Syntax error: mismatched input '8'hA5' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + (outer_uint4_t) u4_i = 8'hA5; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:6:24:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:10:1: Syntax error: extraneous input '(' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + (inner_type) inner_i1 = 8'h5A; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:10:1:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:10:25: Syntax error: mismatched input '8'h5A' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + (inner_type) inner_i1 = 8'h5A; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:10:25:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:15:2: Syntax error: extraneous input '(' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'end', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + (inner_type) inner_gb_i = 8'hA5; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:15:2:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:15:28: Syntax error: mismatched input '8'hA5' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + (inner_type) inner_gb_i = 8'hA5; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:15:28:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:19:1: Syntax error: extraneous input '(' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + (inner_type) inner_i2 = 8'h42; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:19:1:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:19:25: Syntax error: mismatched input '8'h42' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + (inner_type) inner_i2 = 8'h42; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:19:25:. +[ FATAL] : 0 +[ SYNTAX] : 9 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1949,8 +2111,35 @@ Processing: -cd svtypes typedef_simple.sv -writepp -parse -nocache -nobuiltin -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:6:9: Syntax error: extraneous input '(' expecting {'interface', 'virtual', 'class', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', DOLLAR_UNIT, 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, typedef (int8_t) char_t; ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:6:9:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:6:16: Syntax error: no viable alternative at input 'int8_t)', + typedef (int8_t) char_t; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:6:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:8:12: Syntax error: no viable alternative at input '(* keep *) (', + (* keep *) (uint2_t) int2 = 2'b10; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:8:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:8:29: Syntax error: mismatched input '2'b10' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + (* keep *) (uint2_t) int2 = 2'b10; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:8:29:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:9:12: Syntax error: no viable alternative at input '(* keep *) (', + (* keep *) (int4_t) int4 = -1; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:9:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:9:28: Syntax error: mismatched input '-' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + (* keep *) (int4_t) int4 = -1; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:9:28:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:10:12: Syntax error: no viable alternative at input '(* keep *) (', + (* keep *) (int8_t) int8 = int4; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:10:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:10:32: Syntax error: mismatched input ';' expecting '=', + (* keep *) (int8_t) int8 = int4; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:10:32:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:11:12: Syntax error: no viable alternative at input '(* keep *) (', + (* keep *) (char_t) ch = int8; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:11:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:11:30: Syntax error: mismatched input ';' expecting '=', + (* keep *) (char_t) ch = int8; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:11:30:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1967,8 +2156,11 @@ Processing: -cd svtypes typedef_package.sv -writepp -parse -nocache -nobuiltin - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_package.sv:7:12: Syntax error: no viable alternative at input '(* keep *) (', (* keep *) (pkg::uint8_t) a = 8'hAA; ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_package.sv:7:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_package.sv:7:31: Syntax error: mismatched input '8'hAA' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + (* keep *) (pkg::uint8_t) a = 8'hAA; + ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_package.sv:7:31:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -2018,7 +2210,7 @@ Processing: -cd simple defvalue.sv -writepp -parse -nocache -nobuiltin -nonote - [ NOTE] : 0 Processed 281 tests. [ FATAL] : 0 -[ SYNTAX] : 36 +[ SYNTAX] : 100 [ ERROR] : 8 [WARNING] : 215 [ NOTE] : 0 diff --git a/third_party/tests/YosysTests/YosysTests.log b/third_party/tests/YosysTests/YosysTests.log index 3bcb9ef98f..9742d7254d 100644 --- a/third_party/tests/YosysTests/YosysTests.log +++ b/third_party/tests/YosysTests/YosysTests.log @@ -747,8 +747,11 @@ Processing: -cd misc/miter_assert_assume top.v -writepp -parse -nocache -nobuilt [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/miter_assert_assume/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/miter_assert_assume/top.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/miter_assert_assume/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/miter_assert_assume/top.v:37:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1014,8 +1017,11 @@ Processing: -cd misc/splitnets_logic top.v -writepp -parse -nocache -nobuiltin - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/splitnets_logic/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/splitnets_logic/top.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/splitnets_logic/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/splitnets_logic/top.v:37:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1080,8 +1086,11 @@ Processing: -cd misc/fmcombine_assert_assume top.v -writepp -parse -nocache -nob [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/fmcombine_assert_assume/top.v:58:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/fmcombine_assert_assume/top.v:58:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/fmcombine_assert_assume/top.v:65:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/fmcombine_assert_assume/top.v:65:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1221,8 +1230,11 @@ Processing: -cd misc/chformal top.v -writepp -parse -nocache -nobuiltin -nonote [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/chformal/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/chformal/top.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/chformal/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/chformal/top.v:37:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1320,8 +1332,11 @@ Processing: -cd misc/chformal_error top.v -writepp -parse -nocache -nobuiltin -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/chformal_error/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/chformal_error/top.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/chformal_error/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/chformal_error/top.v:37:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1549,8 +1564,11 @@ Processing: -cd frontends/read_aiger top2.v -writepp -parse -nocache -nobuiltin [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/read_aiger/top2.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/read_aiger/top2.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/read_aiger/top2.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/read_aiger/top2.v:37:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1892,8 +1910,11 @@ Processing: -cd frontends/read_verilog_assert top.v -writepp -parse -nocache -no [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/read_verilog_assert/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/read_verilog_assert/top.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/read_verilog_assert/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/read_verilog_assert/top.v:37:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -2109,8 +2130,11 @@ Processing: -cd frontends/verilog_lexer_supply top.v -writepp -parse -nocache -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/verilog_lexer_supply/top.v:90:12: Syntax error: mismatched input ')' expecting ',', buf (supply1) g1 (y, a); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/verilog_lexer_supply/top.v:90:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/verilog_lexer_supply/top.v:91:12: Syntax error: mismatched input ')' expecting ',', +buf (supply0) g2 (y, b); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/verilog_lexer_supply/top.v:91:12:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -2456,8 +2480,11 @@ Processing: -cd frontends/verilog_lexer_assert_assume_restrict top2.v -writepp - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/verilog_lexer_assert_assume_restrict/top2.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/verilog_lexer_assert_assume_restrict/top2.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/verilog_lexer_assert_assume_restrict/top2.v:37:11: Syntax error: extraneous input 'eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/verilog_lexer_assert_assume_restrict/top2.v:37:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -2868,8 +2895,17 @@ Processing: -cd backends/write_xaiger_error top.v -writepp -parse -nocache -nobu [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top.v:37:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top.v:74:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assume(s_eventually too); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top.v:74:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top.v:81:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top.v:81:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 4 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -2877,8 +2913,11 @@ Processing: -cd backends/write_xaiger_error top2.v -writepp -parse -nocache -nob [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top2.v:31:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top2.v:31:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top2.v:38:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top2.v:38:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -3128,8 +3167,11 @@ Processing: -cd backends/write_btor top.v -writepp -parse -nocache -nobuiltin -n [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_btor/top.v:32:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_btor/top.v:32:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_btor/top.v:39:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_btor/top.v:39:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -3614,8 +3656,11 @@ Processing: -cd backends/write_smt2_init_assert top.v -writepp -parse -nocache - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_smt2_init_assert/top.v:32:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_smt2_init_assert/top.v:32:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_smt2_init_assert/top.v:39:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_smt2_init_assert/top.v:39:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -3926,8 +3971,11 @@ Processing: -cd backends/write_intersynth_error top2.v -writepp -parse -nocache [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_intersynth_error/top2.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_intersynth_error/top2.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_intersynth_error/top2.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_intersynth_error/top2.v:37:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -3969,8 +4017,11 @@ Processing: -cd backends/write_aiger top.v -writepp -parse -nocache -nobuiltin - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger/top.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger/top.v:37:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -3995,8 +4046,17 @@ Processing: -cd backends/write_aiger_error top.v -writepp -parse -nocache -nobui [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top.v:37:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top.v:74:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assume(s_eventually too); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top.v:74:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top.v:81:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top.v:81:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 4 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -4004,8 +4064,11 @@ Processing: -cd backends/write_aiger_error top2.v -writepp -parse -nocache -nobu [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top2.v:31:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top2.v:31:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top2.v:38:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top2.v:38:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -4030,8 +4093,11 @@ Processing: -cd backends/write_btor_init_assert top.v -writepp -parse -nocache - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_btor_init_assert/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_btor_init_assert/top.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_btor_init_assert/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_btor_init_assert/top.v:37:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -4161,8 +4227,11 @@ Processing: -cd backends/write_xaiger top.v -writepp -parse -nocache -nobuiltin [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger/top.v:30:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + assert(s_eventually ASSERT); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger/top.v:37:11:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5068,8 +5137,35 @@ Processing: -cd architecture/synth_xilinx_srl sr_fixed_length_other_users_port.v [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:7:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int [width-1:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:7:19:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:10:18: Syntax error: mismatched input '[' expecting ''', + assign int[w][0] = i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:10:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:10:31: Syntax error: mismatched input ';' expecting '=', + assign int[w][0] = i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:10:31:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:45: Syntax error: no viable alternative at input '#~@$_DFFE_PP_#~@r(.C(clk), .D(int[', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:45:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:30: Syntax error: no viable alternative at input '(.', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:30:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:36: Syntax error: extraneous input ')' expecting ',', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:36:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:39:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:41: Syntax error: mismatched input '(' expecting {',', ')'}, + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:41:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:57: Syntax error: no viable alternative at input '(1'b1', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:57:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:70: Syntax error: mismatched input '[' expecting ''', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:70:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5089,8 +5185,35 @@ Processing: -cd architecture/synth_xilinx_srl pos_clk_no_enable_no_init_not_infe [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:6:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int [width-1:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:6:19:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:9:18: Syntax error: mismatched input '[' expecting ''', + assign int[w][0] = i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:9:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:9:31: Syntax error: mismatched input ';' expecting '=', + assign int[w][0] = i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:9:31:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:45: Syntax error: no viable alternative at input '#~@$_DFF_PP0_#~@r(.C(clk), .D(int[', + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:45:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:30: Syntax error: no viable alternative at input '(.', + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:30:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:36: Syntax error: extraneous input ')' expecting ',', + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:36:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:39:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:41: Syntax error: mismatched input '(' expecting {',', ')'}, + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:41:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:58: Syntax error: extraneous input ')' expecting ',', + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:58:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:61: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:61:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5098,8 +5221,26 @@ Processing: -cd architecture/synth_xilinx_srl neg_clk_no_enable_with_init_with_i [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:6:20: Syntax error: no viable alternative at input 'reg [depth-1:0] int', reg [depth-1:0] int [width-1:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:6:20:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:11:23: Syntax error: no viable alternative at input 'int[', + initial int[w][d] <= ~((d+w) % 2); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:11:23:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:14:37: Syntax error: no viable alternative at input 'int[', + always @(negedge clk) int[w] <= i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:14:37:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:15:29: Syntax error: no viable alternative at input 'int[', + assign q[w] = int[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:15:29:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:17:8: Syntax error: rule if_generate_construct failed predicate: _input->LA(1) != ELSE?, + else begin + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:17:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:18:37: Syntax error: no viable alternative at input 'int[', + always @(negedge clk) int[w] <= { int[w][depth-2:0], i[w] }; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:18:37:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:19:29: Syntax error: no viable alternative at input 'int[', + assign q[w] = int[w][depth-1]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:19:29:. +[ FATAL] : 0 +[ SYNTAX] : 7 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5107,8 +5248,35 @@ Processing: -cd architecture/synth_xilinx_srl test21b.v -writepp -parse -nocache [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:3:20: Syntax error: mismatched input 'int' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, reg [depth-1:0] int; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:3:20:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:7:19: Syntax error: no viable alternative at input 'int[', + initial int[d] <= ~(d % 2); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:7:19:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:7:19: Syntax error: extraneous input '[' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + initial int[d] <= ~(d % 2); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:7:19:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:7:21: Syntax error: mismatched input ']' expecting ';', + initial int[d] <= ~(d % 2); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:7:21:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:10:41: Syntax error: no viable alternative at input 'int <=', + always @(negedge clk) if (e) int <= ~^i[width-1:0]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:10:41:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:11:22: Syntax error: no viable alternative at input 'int;', + assign q = int; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:11:22:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:13:4: Syntax error: rule if_generate_construct failed predicate: _input->LA(1) != ELSE?, + else begin + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:13:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:14:41: Syntax error: no viable alternative at input 'int <=', + always @(negedge clk) if (e) int <= { int[depth-2:0], ~^i[width-1:0] }; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:14:41:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:14:41: Syntax error: mismatched input '<=' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + always @(negedge clk) if (e) int <= { int[depth-2:0], ~^i[width-1:0] }; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:14:41:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:14:49: Syntax error: extraneous input '[' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + always @(negedge clk) if (e) int <= { int[depth-2:0], ~^i[width-1:0] }; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:14:49:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5116,8 +5284,35 @@ Processing: -cd architecture/synth_xilinx_srl pos_clk_no_enable_no_init_not_infe [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:6:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int [width-1:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:6:19:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:9:18: Syntax error: mismatched input '[' expecting ''', + assign int[w][0] = i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:9:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:9:31: Syntax error: mismatched input ';' expecting '=', + assign int[w][0] = i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:9:31:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:45: Syntax error: no viable alternative at input '#~@$_DFF_PP0_#~@r(.C(clk), .D(int[', + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:45:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:30: Syntax error: no viable alternative at input '(.', + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:30:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:36: Syntax error: extraneous input ')' expecting ',', + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:36:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:39:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:41: Syntax error: mismatched input '(' expecting {',', ')'}, + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:41:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:58: Syntax error: extraneous input ')' expecting ',', + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:58:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:61: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:61:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5137,8 +5332,29 @@ Processing: -cd architecture/synth_xilinx_srl sr_var_length_other_users_port.v - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:7:20: Syntax error: no viable alternative at input 'reg [depth-1:0] int', reg [depth-1:0] int [width-1:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:7:20:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:12:23: Syntax error: no viable alternative at input 'int[', + initial int[w][d] <= ~((d+w) % 2); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:12:23:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:15:44: Syntax error: no viable alternative at input 'int[', + always @(negedge clk) if (e) int[w] <= i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:15:44:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:16:29: Syntax error: no viable alternative at input 'int[', + assign q[w] = int[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:16:29:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:18:8: Syntax error: rule if_generate_construct failed predicate: _input->LA(1) != ELSE?, + else begin + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:18:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:19:44: Syntax error: no viable alternative at input 'int[', + always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }}; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:19:44:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:20:29: Syntax error: no viable alternative at input 'int[', + assign q[w] = int[w][l]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:20:29:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:23:22: Syntax error: no viable alternative at input 'int[', + assign state = int[0]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:23:22:. +[ FATAL] : 0 +[ SYNTAX] : 8 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5146,8 +5362,35 @@ Processing: -cd architecture/synth_xilinx_srl neg_clk_no_enable_with_init_with_i [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:6:20: Syntax error: no viable alternative at input 'reg [depth-1:0] int', reg [depth-1:0] int [width-1:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:6:20:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:11:23: Syntax error: no viable alternative at input 'int[', + initial int[w][d] <= ~((d+w) % 2); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:11:23:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:14:57: Syntax error: no viable alternative at input 'int[', + always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= a[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:14:57:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:14:70: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'end', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= a[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:14:70:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:15:29: Syntax error: no viable alternative at input 'int[', + assign q[w] = int[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:15:29:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:17:8: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'endgenerate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + else begin + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:17:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:18:57: Syntax error: no viable alternative at input 'int[', + always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= {{ int[w][depth-2:0], i[w] }}; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:18:57:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:18:79: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'end', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= {{ int[w][depth-2:0], i[w] }}; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:18:79:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:19:29: Syntax error: no viable alternative at input 'int[', + assign q[w] = int[w][l]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:19:29:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:21:4: Syntax error: extraneous input 'end' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'endgenerate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + end + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:21:4:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5155,8 +5398,35 @@ Processing: -cd architecture/synth_xilinx_srl pos_clk_no_enable_no_init_not_infe [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:6:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int [width-1:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:6:19:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:9:18: Syntax error: mismatched input '[' expecting ''', + assign int[w][0] = i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:9:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:9:31: Syntax error: mismatched input ';' expecting '=', + assign int[w][0] = i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:9:31:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:45: Syntax error: no viable alternative at input '#~@$_DFFE_PP_#~@r(.C(clk), .D(int[', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:45:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:30: Syntax error: no viable alternative at input '(.', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:30:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:36: Syntax error: extraneous input ')' expecting ',', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:36:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:39:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:41: Syntax error: mismatched input '(' expecting {',', ')'}, + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:41:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:57: Syntax error: no viable alternative at input '(1'b0', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:57:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:70: Syntax error: mismatched input '[' expecting ''', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:70:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5164,8 +5434,29 @@ Processing: -cd architecture/synth_xilinx_srl sr_var_length_other_users_xor.v -w [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:7:20: Syntax error: no viable alternative at input 'reg [depth-1:0] int', reg [depth-1:0] int [width-1:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:7:20:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:12:23: Syntax error: no viable alternative at input 'int[', + initial int[w][d] <= ~((d+w) % 2); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:12:23:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:15:44: Syntax error: no viable alternative at input 'int[', + always @(negedge clk) if (e) int[w] <= i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:15:44:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:16:29: Syntax error: no viable alternative at input 'int[', + assign q[w] = int[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:16:29:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:18:8: Syntax error: rule if_generate_construct failed predicate: _input->LA(1) != ELSE?, + else begin + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:18:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:19:44: Syntax error: no viable alternative at input 'int[', + always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }}; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:19:44:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:20:29: Syntax error: no viable alternative at input 'int[', + assign q[w] = int[w][l]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:20:29:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:23:30: Syntax error: no viable alternative at input '{^int[', + assign state = {depth{^int[0]}}; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:23:30:. +[ FATAL] : 0 +[ SYNTAX] : 8 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5211,8 +5502,35 @@ Processing: -cd architecture/synth_xilinx_srl neg_clk_no_enable_with_init_with_i [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:6:20: Syntax error: no viable alternative at input 'reg [depth-1:0] int', reg [depth-1:0] int [width-1:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:6:20:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:11:23: Syntax error: no viable alternative at input 'int[', + initial int[w][d] <= ~((d+w) % 2); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:11:23:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:14:57: Syntax error: no viable alternative at input 'int[', + always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:14:57:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:14:70: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'end', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:14:70:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:15:29: Syntax error: no viable alternative at input 'int[', + assign q[w] = int[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:15:29:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:17:8: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'endgenerate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + else begin + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:17:8:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:18:57: Syntax error: no viable alternative at input 'int[', + always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= { int[w][depth-2:0], i[w] }; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:18:57:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:18:79: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'end', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= { int[w][depth-2:0], i[w] }; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:18:79:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:19:29: Syntax error: no viable alternative at input 'int[', + assign q[w] = int[w][depth-1]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:19:29:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:21:4: Syntax error: extraneous input 'end' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'endgenerate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + end + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:21:4:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5253,8 +5571,35 @@ Processing: -cd architecture/synth_xilinx_srl sr_fixed_length_other_users_xor.v [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:7:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int [width-1:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:7:19:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:10:18: Syntax error: mismatched input '[' expecting ''', + assign int[w][0] = i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:10:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:10:31: Syntax error: mismatched input ';' expecting '=', + assign int[w][0] = i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:10:31:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:45: Syntax error: no viable alternative at input '#~@$_DFFE_PP_#~@r(.C(clk), .D(int[', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:45:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:30: Syntax error: no viable alternative at input '(.', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:30:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:36: Syntax error: extraneous input ')' expecting ',', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:36:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:39:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:41: Syntax error: mismatched input '(' expecting {',', ')'}, + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:41:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:57: Syntax error: no viable alternative at input '(1'b1', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:57:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:70: Syntax error: mismatched input '[' expecting ''', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:70:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5268,8 +5613,35 @@ Processing: -cd architecture/synth_xilinx_srl test21a.v -writepp -parse -nocache [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:4:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:4:19:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:4:22: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at ';', + wire [depth:0] int; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:4:22:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:5:14: Syntax error: mismatched input '[' expecting ''', + assign int[0] = ^i[width-1:0]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:5:14:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:5:16: Syntax error: mismatched input ']' expecting ':', + assign int[0] = ^i[width-1:0]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:5:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:5:18: Syntax error: extraneous input '=' expecting {'[', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + assign int[0] = ^i[width-1:0]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:5:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:8:45: Syntax error: no viable alternative at input '#~@$_DFFE_PP_#~@r(.C(clk), .D(int[', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:8:45:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:8:30: Syntax error: no viable alternative at input '(.', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:8:30:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:8:36: Syntax error: extraneous input ')' expecting ',', + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:8:36:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:8:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:8:39:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:8:41: Syntax error: mismatched input '(' expecting {',', ')'}, + #~@$_DFFE_PP_#~@r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1])); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:8:41:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5277,8 +5649,23 @@ Processing: -cd architecture/synth_xilinx_srl test20.v -writepp -parse -nocache [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:4:20: Syntax error: no viable alternative at input 'reg [width-1:0] int', reg [width-1:0] int [depth-1:0]; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:4:20:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:9:23: Syntax error: no viable alternative at input 'int[', + initial int[d][w] <= ~((d+w) % 2); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:9:23:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:12:48: Syntax error: no viable alternative at input 'int[', + always @(negedge clk) if (e) int[d][w] <= i[w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:12:48:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:14:12: Syntax error: rule if_generate_construct failed predicate: _input->LA(1) != ELSE?, + else begin + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:14:12:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:15:48: Syntax error: no viable alternative at input 'int[', + always @(negedge clk) if (e) int[d][w] <= int[d-1][w]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:15:48:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:19:18: Syntax error: no viable alternative at input 'int[', + assign z = int[depth-1]; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:19:18:. +[ FATAL] : 0 +[ SYNTAX] : 6 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -5738,8 +6125,35 @@ Processing: -cd bigsim/navre/sim sieve.v -writepp -parse -nocache -nobuiltin -no [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:1:9: Syntax error: mismatched input ']' expecting ':', pmem[ 0] = 16'hc00c; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:1:9:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:1:11: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', +pmem[ 0] = 16'hc00c; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:1:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:2:9: Syntax error: mismatched input ']' expecting ':', +pmem[ 1] = 16'hc01b; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:2:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:2:11: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', +pmem[ 1] = 16'hc01b; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:2:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:3:9: Syntax error: mismatched input ']' expecting ':', +pmem[ 2] = 16'hc01a; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:3:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:3:11: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', +pmem[ 2] = 16'hc01a; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:3:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:4:9: Syntax error: mismatched input ']' expecting ':', +pmem[ 3] = 16'hc019; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:4:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:4:11: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', +pmem[ 3] = 16'hc019; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:4:11:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:5:9: Syntax error: mismatched input ']' expecting ':', +pmem[ 4] = 16'hc018; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:5:9:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:5:11: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', +pmem[ 4] = 16'hc018; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:5:11:. +[ FATAL] : 0 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -6228,8 +6642,11 @@ Processing: -cd regression/issue_00093 top.v -writepp -parse -nocache -nobuiltin [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00093/top.v:1:34: Syntax error: mismatched input '+' expecting {Pound_Pound_delay, Pound_delay, '(', 'type', 'local', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, module top(b);inout b;reg c;assign+0-c=b;endmodule ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00093/top.v:1:34:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00093/top.v:1:40: Syntax error: mismatched input ';' expecting '=', +module top(b);inout b;reg c;assign+0-c=b;endmodule + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00093/top.v:1:40:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -6809,8 +7226,14 @@ Processing: -cd regression/issue_00655/verilog/submodule/test tb_lm32_system.v - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:291:22: Syntax error: no viable alternative at input 'module soc();\n\ninteger i;\n\nreg sys_rst;\nreg sys_clk;\nreg [31:0] interrupt;\n\nreg i_ack;\nwire [31:0] i_adr;\nwire i_cyc;\nwire [31:0] i_dat;\nwire i_stb;\n\nreg d_ack;\nwire [31:0] d_adr;\nwire d_cyc;\nwire [31:0] d_dat_i;\nwire [31:0] d_dat_o;\nwire [3:0] d_sel;\nwire d_stb;\n\nlm32_top lm32(\n\t.clk_i(sys_clk),\n\t.rst_i(sys_rst),\n\n\t.interrupt(interrupt),\n\n\t.I_ACK_I(i_ack),\n\t.I_ADR_O(i_adr),\n\t.I_BTE_O(),\n\t.I_CTI_O(),\n\t.I_CYC_O(i_cyc),\n\t.I_DAT_I(i_dat),\n\t.I_DAT_O(),\n\t.I_ERR_I(1'b0),\n\t.I_LOCK_O(),\n\t.I_RTY_I(1'b0),\n\t.I_SEL_O(),\n\t.I_STB_O(i_stb),\n\t.I_WE_O(),\n\n\t.D_ACK_I(d_ack),\n\t.D_ADR_O(d_adr),\n\t.D_BTE_O(),\n\t.D_CTI_O(),\n\t.D_CYC_O(d_cyc),\n\t.D_DAT_I(d_dat_i),\n\t.D_DAT_O(d_dat_o),\n\t.D_ERR_I(1'b0),\n\t.D_LOCK_O(),\n\t.D_RTY_I(1'b0),\n\t.D_SEL_O(d_sel),\n\t.D_STB_O(d_stb),\n\t.D_WE_O(d_we)\n);\n\n// clock\ninitial sys_clk = 1'b0;\nalways #5 sys_clk = ~sys_clk;\n\n// reset\ninitial begin\n\tsys_rst = 1'b1;\n\t#20\n\tsys_rst = 1'b0;\nend\n\n// memory\nreg [7:0] mem[0:65536];\ninitial begin\n\tfor(i=0;i<65536;i=i+1)\n\t\tmem[i] = 8'b0;\nend\n\nwire [31:0] dmem_dat_i;\nreg [31:0] dmem_dat_o;\nwire [13:0] dmem_adr;\nwire [3:0] dmem_we;\nalways @(posedge sys_clk) begin\n\tif(dmem_we[0]) mem[{dmem_adr, 2'b11}] <= dmem_dat_i[7:0];\n\tif(dmem_we[1]) mem[{dmem_adr, 2'b10}] <= dmem_dat_i[15:8];\n\tif(dmem_we[2]) mem[{dmem_adr, 2'b01}] <= dmem_dat_i[23:16];\n\tif(dmem_we[3]) mem[{dmem_adr, 2'b00}] <= dmem_dat_i[31:24];\n\tdmem_dat_o[7:0] <= mem[{dmem_adr, 2'b11}];\n\tdmem_dat_o[15:8] <= mem[{dmem_adr, 2'b10}];\n\tdmem_dat_o[23:16] <= mem[{dmem_adr, 2'b01}];\n\tdmem_dat_o[31:24] <= mem[{dmem_adr, 2'b00}];\nend\nreg [31:0] pmem_dat_o;\nwire [13:0] pmem_adr;\nalways @(posedge sys_clk) begin\n\tpmem_dat_o[7:0] <= mem[{pmem_adr, 2'b11}];\n\tpmem_dat_o[15:8] <= mem[{pmem_adr, 2'b10}];\n\tpmem_dat_o[23:16] <= mem[{pmem_adr, 2'b01}];\n\tpmem_dat_o[31:24] <= mem[{pmem_adr, 2'b00}];\nend\n\n// uart\nalways @(posedge sys_clk) begin\n\tif(d_cyc & d_stb & d_we & d_ack)\n\t\tif(d_adr == 32'hff000000)\n\t\t\t$write("%c", d_dat_o[7:0]);\nend\n\n// wishbone interface for instruction bus\nalways @(posedge sys_clk) begin\n\tif(sys_rst)\n\t\ti_ack <= 1'b0;\n\telse begin\n\t\ti_ack <= 1'b0;\n\t\tif(i_cyc & i_stb & ~i_ack)\n\t\t\ti_ack <= 1'b1;\n\tend\nend\n\nassign i_dat = pmem_dat_o;\nassign pmem_adr = i_adr[15:2];\n\ntask dump_processor_state;\nbegin\n\t$display("Processor state:");\n\t$display(" PSW=%08x", lm32.cpu.psw);\n\t$display(" IE=%08x IP=%08x IM=%08x",\n\t\tlm32.cpu.interrupt_unit.ie,\n\t\tlm32.cpu.interrupt_unit.ip,\n\t\tlm32.cpu.interrupt_unit.im\n\t);\n\tfor(i=0; i<32; i=i+1) begin\n\t\tif(i%4 == 0)\n\t\t\t$write(" ");\n\t\t$write("r%02d=%08x ", i, lm32.cpu.reg_0.mem[i]);\n\t\tif((i+1)%4 == 0)\n\t\t\t$write("\n");\n\tend\nend\nendtask\n\n// QEMU test core\nreg [15:0] testname_adr;\nreg [8*32:0] testname;\nreg testname_end;\nalways @(posedge sys_clk) begin\n\tif(d_cyc & d_stb & d_we & d_ack)\n\tbegin\n\t\tif(d_adr == 32'hffff0000)\n\t\t\t$finish;\n\t\telse if(d_adr == 32'hffff0004) begin\n\t\t\t// is there any better way to do this?\n\t\t\ttestname_end = 1'b0;\n\t\t\tfor(i=0; i<32; i=i+1) begin\n\t\t\t\ttestname = testname << 8;\n\t\t\t\tif(testname_end == 1'b0) begin\n\t\t\t\t\ttestname[7:0] = mem[testname_adr+i];\n\t\t\t\t\tif(mem[testname_adr+i] == 8'b0)\n\t\t\t\t\t\ttestname_end = 1'b1;\n\t\t\t\tend else\n\t\t\t\t\ttestname[7:0] = 8'b0;\n\t\t\tend\n\t\t\t$display("TC %-32s %s", testname, (|d_dat_o) ? "FAILED" : "OK");\n\t\t\tif(|d_dat_o)\n\t\t\t\tdump_processor_state();\n\t\tend\n\t\telse if(d_adr == 32'hffff0008)\n\t\t\ttestname_adr <= d_dat_o[15:0];\n\tend\nend\n\n// wishbone interface for data bus\nalways @(posedge sys_clk) begin\n\tif(sys_rst)\n\t\td_ack <= 1'b0;\n\telse begin\n\t\td_ack <= 1'b0;\n\t\tif(d_cyc & d_stb & ~d_ack)\n\t\t\td_ack <= 1'b1;\n\tend\nend\n\nassign d_dat_i = dmem_dat_o;\nassign dmem_dat_i = d_dat_o;\nassign dmem_adr = d_adr[15:2];\nassign dmem_we = {4{d_cyc & d_stb & d_we & ~|d_adr[31:16]}} & d_sel;\n\n// interrupts\ninitial interrupt <= 32'b0;\n\n// simulation end request\nalways @(posedge sys_clk) begin\n\tif(d_cyc & d_stb & d_we & d_ack)\n\t\tif(d_adr == 32'hdead0000 && d_dat_o == 32'hbeef)\n\t\t\t$finish;\nend\n\n// traces\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n// dump signals\nreg [256*8:0] vcdfile;\ninitial begin\n\tif($value$plusargs("dump=%s", vcdfile)) begin\n\t\t$dumpfile(vcdfile);\n\t\t$dumpvars(0, soc);\n\tend\nend\n\n// init memory\nreg [256*8:0] prog;\ninitial begin\n\tif(! $value$plusargs("prog=%s", prog)) begin\n\t\t$display("ERROR: please specify +prog=.vh to start.");\n\t\t$finish;\n\tend\nend\n\ninitial $readmemh(prog, mem);\n\n// trace pipeline\nreg [256*8:0] tracefile;\ninteger trace_started;\ninteger trace_enabled;\ninteger cycle;\ninteger tracefd;\ninitial begin\n\tif($value$plusargs("trace=%s", tracefile)) begin\n\t\ttrace_enabled = 1;\n\t\tcycle = 0;\n\t\ttracefd = $fopen(tracefile);\n\t\ttrace_started = 0;\n\tend else\n\t\ttrace_enabled = 0;\nend\n\n\n\nassign icache_ready = SURELOG_MACRO_NOT_DEFINED:TRUE!!!', assign icache_ready = SURELOG_MACRO_NOT_DEFINED:TRUE!!! ; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:291:22:. -[ FATAL] : 0 -[ SYNTAX] : 1 +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:55:13: Syntax error: no viable alternative at input 'lm32_top lm32(', +lm32_top lm32( + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:55:13:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:91: Syntax error: mismatched input 'initial' expecting , +initial sys_clk = 1'b0; +^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:91:0:. +[ FATAL] : 0 +[ SYNTAX] : 3 [ ERROR] : 3 [WARNING] : 0 [ NOTE] : 0 @@ -6849,9 +7272,18 @@ Processing: -cd regression/issue_00655/verilog/submodule/rtl lm32_instruction_un [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:188:22: Syntax error: no viable alternative at input 'module lm32_instruction_unit (\n // ----- Inputs -------\n clk_i,\n rst_i,\n\n\n\n\n\n // From pipeline\n stall_a,\n stall_f,\n stall_d,\n stall_x,\n stall_m,\n valid_f,\n valid_d,\n kill_f,\n branch_predict_taken_d,\n branch_predict_address_d,\n\n\n\n\n exception_m,\n branch_taken_m,\n branch_mispredict_taken_m,\n branch_target_m,\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n // From Wishbone\n i_dat_i,\n i_ack_i,\n i_err_i,\n\n\n\n\n\n\n\n // ----- Outputs -------\n // To pipeline\n pc_f,\n pc_d,\n pc_x,\n pc_m,\n pc_w,\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n // To Wishbone\n i_dat_o,\n i_adr_o,\n i_cyc_o,\n i_sel_o,\n i_stb_o,\n i_we_o,\n i_cti_o,\n i_lock_o,\n i_bte_o,\n\n\n\n\n\n\n bus_error_d,\n\n\n\n\n instruction_d\n );\n\n/////////////////////////////////////////////////////\n// Parameters\n/////////////////////////////////////////////////////\n\nparameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!!', parameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!! ; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:555:22:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:188:22: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'virtual', 'type', 'const', 'local', 'super', '{', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, +parameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!! ; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:555:22:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:196:51: Syntax error: mismatched input '?' expecting ';', +localparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!! -2; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:563:51:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:196:92: Syntax error: mismatched input '-' expecting , +localparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!! -2; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:563:92:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:196: Unknown macro "CLOG2". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 4 [ ERROR] : 4 [WARNING] : 0 [ NOTE] : 0 @@ -6937,8 +7369,14 @@ Processing: -cd regression/issue_00655/verilog/submodule/rtl lm32_cpu.v -writepp [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:191:22: Syntax error: no viable alternative at input 'module lm32_cpu (\n // ----- Inputs -------\n clk_i,\n\n\n\n rst_i,\n\n\n\n\n\n // From external devices\n\n interrupt,\n\n // From user logic\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n // Instruction Wishbone master\n I_DAT_I,\n I_ACK_I,\n I_ERR_I,\n I_RTY_I,\n\n // Data Wishbone master\n D_DAT_I,\n D_ACK_I,\n D_ERR_I,\n D_RTY_I,\n // ----- Outputs -------\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n // Instruction Wishbone master\n I_DAT_O,\n I_ADR_O,\n I_CYC_O,\n I_SEL_O,\n I_STB_O,\n I_WE_O,\n I_CTI_O,\n I_LOCK_O,\n I_BTE_O,\n\n // Data Wishbone master\n D_DAT_O,\n D_ADR_O,\n D_CYC_O,\n D_SEL_O,\n D_STB_O,\n D_WE_O,\n D_CTI_O,\n D_LOCK_O,\n D_BTE_O\n );\n\n/////////////////////////////////////////////////////\n// Parameters\n/////////////////////////////////////////////////////\n\nparameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!!', parameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!! ; // Reset value for EBA CSR ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:558:22:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:191:22: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'virtual', 'type', 'const', 'local', 'super', '{', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, +parameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!! ; // Reset value for EBA CSR + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:558:22:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:245: Syntax error: mismatched input 'input' expecting , +input clk_i; // Clock +^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:612:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 2 [WARNING] : 0 [ NOTE] : 0 @@ -6948,9 +7386,15 @@ Processing: -cd regression/issue_00655/verilog/submodule/rtl lm32_load_store_uni [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:159:57: Syntax error: no viable alternative at input 'module lm32_load_store_unit (\n // ----- Inputs -------\n clk_i,\n rst_i,\n // From pipeline\n stall_a,\n stall_x,\n stall_m,\n kill_m,\n exception_m,\n store_operand_x,\n load_store_address_x,\n load_store_address_m,\n load_store_address_w,\n\n\n\n\n load_x,\n store_x,\n load_q_x,\n store_q_x,\n load_q_m,\n store_q_m,\n sign_extend_x,\n size_x,\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n // From Wishbone\n d_dat_i,\n d_ack_i,\n d_err_i,\n d_rty_i,\n // ----- Outputs -------\n // To pipeline\n\n\n\n\n\n\n\n\n\n\n\n\n load_data_w,\n stall_wb_load,\n\n\n\n\n\n\n // To Wishbone\n d_dat_o,\n d_adr_o,\n d_cyc_o,\n d_sel_o,\n d_stb_o,\n d_we_o,\n d_cti_o,\n d_lock_o,\n d_bte_o\n );\n\n/////////////////////////////////////////////////////\n// Parameters\n/////////////////////////////////////////////////////\n\nparameter associativity = 1; // Associativity of the cache (Number of ways)\nparameter sets = 512; // Number of sets\nparameter bytes_per_line = 16; // Number of bytes per cache line\nparameter base_address = 0; // Base address of cachable memory\nparameter limit = 0; // Limit (highest address) of cachable memory\n\n// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used\nlocalparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!!', localparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!! -2; ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:526:57:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:159:51: Syntax error: mismatched input '?' expecting ';', +localparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!! -2; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:526:51:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:159:92: Syntax error: mismatched input '-' expecting , +localparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!! -2; + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:526:92:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:159: Unknown macro "CLOG2". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 3 [WARNING] : 0 [ NOTE] : 0 @@ -7302,8 +7746,29 @@ Processing: -cd regression/issue_00589 top.v -writepp -parse -nocache -nobuiltin [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:568:14: Syntax error: no viable alternative at input 'corebit_and join', corebit_and join( ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:568:14:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:569:18: Syntax error: extraneous input ')' expecting ',', + .in0(join__in0), + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:569:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:570:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .in1(join__in1), + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:570:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:571:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .out(join__out) + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:571:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:589:14: Syntax error: no viable alternative at input 'corebit_and join', + corebit_and join( + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:589:14:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:590:18: Syntax error: extraneous input ')' expecting ',', + .in0(join__in0), + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:590:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:591:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .in1(join__in1), + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:591:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:592:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + .out(join__out) + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:592:4:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 8 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -7594,8 +8059,35 @@ Processing: -cd regression/issue_00502 top.v -writepp -parse -nocache -nobuiltin [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:38: Syntax error: no viable alternative at input 'MY_AND2 inst_a1 (.A(A), .B(B), .Y( \', MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:38:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:20: Syntax error: no viable alternative at input '(.', + MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:20:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:24: Syntax error: extraneous input ')' expecting ',', + MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:24:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:27: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:27:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:34: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:34:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:36: Syntax error: extraneous input '(' expecting {',', ')'}, + MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:36:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:15:31: Syntax error: no viable alternative at input 'MY_AND2 inst_a2 (.A(C), .B( \', + MY_AND2 inst_a2 (.A(C), .B( \\SUM/N10 ), .Y(Y) ); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:15:31:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:15:20: Syntax error: no viable alternative at input '(.', + MY_AND2 inst_a2 (.A(C), .B( \\SUM/N10 ), .Y(Y) ); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:15:20:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:15:24: Syntax error: extraneous input ')' expecting ',', + MY_AND2 inst_a2 (.A(C), .B( \\SUM/N10 ), .Y(Y) ); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:15:24:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:15:27: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, + MY_AND2 inst_a2 (.A(C), .B( \\SUM/N10 ), .Y(Y) ); + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:15:27:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 10 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -7680,8 +8172,14 @@ Processing: -cd regression/issue_00095 top.v -writepp -parse -nocache -nobuiltin [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00095/top.v:1:21: Syntax error: missing ';' at '=', module top(b);inout b=0==c;assign c=^K;assign c=9^k;integer c#0;endmodule ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00095/top.v:1:21:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00095/top.v:1:22: Syntax error: mismatched input '0' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, +module top(b);inout b=0==c;assign c=^K;assign c=9^k;integer c#0;endmodule + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00095/top.v:1:22:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00095/top.v:1:61: Syntax error: extraneous input '#0' expecting ';', +module top(b);inout b=0==c;assign c=^K;assign c=9^k;integer c#0;endmodule + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00095/top.v:1:61:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -7774,8 +8272,14 @@ Processing: -cd regression/issue_00096 top.v -writepp -parse -nocache -nobuiltin [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00096/top.v:2: Syntax error: no viable alternative at input 'module top(b);integer\ninout', inout b;reg c;assign&0=0;assign 0=0;always ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00096/top.v:2:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00096/top.v:2: Syntax error: extraneous input 'inout' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, +inout b;reg c;assign&0=0;assign 0=0;always +^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00096/top.v:2:0:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00096/top.v:2:14: Syntax error: mismatched input 'assign' expecting , +inout b;reg c;assign&0=0;assign 0=0;always + ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00096/top.v:2:14:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -10459,7 +10963,7 @@ Processing: -cd regression/issue_01329 synchronizer.sv -writepp -parse -nocache [ NOTE] : 0 Processed 1309 tests. [ FATAL] : 0 -[ SYNTAX] : 61 +[ SYNTAX] : 229 [ ERROR] : 38 [WARNING] : 2368 [ NOTE] : 0 diff --git a/third_party/tests/Zachjs/Zachjs.log b/third_party/tests/Zachjs/Zachjs.log index 85768764dd..2d10448c37 100644 --- a/third_party/tests/Zachjs/Zachjs.log +++ b/third_party/tests/Zachjs/Zachjs.log @@ -2,8 +2,11 @@ Processing: -cd resolve +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolv [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/reference.v:4:4: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input [width-1:0] i; ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/resolve/reference.v:4:4:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/reference.v:5:4: Syntax error: extraneous input 'output' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + output [width-1:0] o; + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/resolve/reference.v:5:4:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 2 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -101,8 +104,29 @@ Processing: -cd basic +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:24: Syntax error: no viable alternative at input '$display($time, `', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:24:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:16: Syntax error: mismatched input '(' expecting ';', + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:22: Syntax error: mismatched input ',' expecting ';', + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:22:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:25: Syntax error: mismatched input '" A1 @+ "' expecting Simple_identifier, + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:25:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:43: Syntax error: no viable alternative at input 'a]', + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:43:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:48: Syntax error: no viable alternative at input 'b+:', + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:48:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:52: Syntax error: mismatched input ')' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:52:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:11: Syntax error: mismatched input '111' expecting , +111 $display($time, `" A1 @+ ", out[2+a][1+b+:1]); +^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:51:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 8 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -270,8 +294,14 @@ ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:1:9: No default [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:5:17: Syntax error: no viable alternative at input '$display(`', $display(`FOO ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.v:5:17:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:5:16: Syntax error: mismatched input '(' expecting ';', + $display(`FOO + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.v:5:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:6:8: Syntax error: mismatched input '(' expecting , + ( + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.v:6:8:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 3 [WARNING] : 0 [ NOTE] : 0 @@ -307,10 +337,25 @@ Processing: -cd lib +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ - [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:3:18: Syntax error: no viable alternative at input '$dumpfile(SURELOG_MACRO_NOT_DEFINED:TEST_VCD!!!', $dumpfile(SURELOG_MACRO_NOT_DEFINED:TEST_VCD!!! ); ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:3:18:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:3:17: Syntax error: mismatched input '(' expecting ';', + $dumpfile(SURELOG_MACRO_NOT_DEFINED:TEST_VCD!!! ); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:3:17:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:3:56: Syntax error: extraneous input ')' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + $dumpfile(SURELOG_MACRO_NOT_DEFINED:TEST_VCD!!! ); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:3:56:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:4:21: Syntax error: no viable alternative at input '$dumpvars(1, SURELOG_MACRO_NOT_DEFINED:TEST_TOP!!!', + $dumpvars(1, SURELOG_MACRO_NOT_DEFINED:TEST_TOP!!! ); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:4:21:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:4:17: Syntax error: mismatched input '(' expecting ';', + $dumpvars(1, SURELOG_MACRO_NOT_DEFINED:TEST_TOP!!! ); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:4:17:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:4:59: Syntax error: extraneous input ')' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + $dumpvars(1, SURELOG_MACRO_NOT_DEFINED:TEST_TOP!!! ); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:4:59:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:3: Unknown macro "TEST_VCD". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:4: Unknown macro "TEST_TOP". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 6 [ ERROR] : 4 [WARNING] : 0 [ NOTE] : 0 @@ -596,9 +641,15 @@ Processing: -cd resolve +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolv [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/module.sv:8:17: Syntax error: no viable alternative at input '$display(SURELOG_MACRO_NOT_DEFINED:FANCY_SEEING_YOU!!!', $display(SURELOG_MACRO_NOT_DEFINED:FANCY_SEEING_YOU!!! ); ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/resolve/module.sv:8:17:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/module.sv:8:16: Syntax error: mismatched input '(' expecting ';', + $display(SURELOG_MACRO_NOT_DEFINED:FANCY_SEEING_YOU!!! ); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/resolve/module.sv:8:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/module.sv:8:63: Syntax error: extraneous input ')' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, + $display(SURELOG_MACRO_NOT_DEFINED:FANCY_SEEING_YOU!!! ); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/resolve/module.sv:8:63:. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/module.sv:8: Unknown macro "FANCY_SEEING_YOU". [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 2 [WARNING] : 0 [ NOTE] : 0 @@ -618,8 +669,29 @@ Processing: -cd basic +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:24: Syntax error: no viable alternative at input '$display($time, `', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:24:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:16: Syntax error: mismatched input '(' expecting ';', + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:22: Syntax error: mismatched input ',' expecting ';', + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:22:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:25: Syntax error: mismatched input '" A1 @+ "' expecting Simple_identifier, + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:25:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:43: Syntax error: no viable alternative at input 'a]', + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:43:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:48: Syntax error: no viable alternative at input 'b+:', + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:48:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:52: Syntax error: mismatched input ')' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, + $display($time, `" A1 @+ ", out[1+a][1+b+:1]); + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:52:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:11: Syntax error: mismatched input '111' expecting , +111 $display($time, `" A1 @+ ", out[2+a][1+b+:1]); +^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:50:0:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 8 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -639,8 +711,14 @@ Processing: -cd basic +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/enum.sv:25:13: Syntax error: no viable alternative at input 'enum [', typedef enum [0:0] { ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/enum.sv:25:13:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/enum.sv:25:13: Syntax error: mismatched input '[' expecting {'{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, +typedef enum [0:0] { + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/enum.sv:25:13:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/enum.sv:25:19: Syntax error: mismatched input '{' expecting ';', +typedef enum [0:0] { + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/enum.sv:25:19:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -769,8 +847,14 @@ ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:1:9: No default [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:5:17: Syntax error: no viable alternative at input '$display(`', $display(`FOO ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.sv:5:17:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:5:16: Syntax error: mismatched input '(' expecting ';', + $display(`FOO + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.sv:5:16:. +[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:6:8: Syntax error: mismatched input '(' expecting , + ( + ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.sv:6:8:. [ FATAL] : 0 -[ SYNTAX] : 1 +[ SYNTAX] : 3 [ ERROR] : 3 [WARNING] : 0 [ NOTE] : 0 @@ -931,7 +1015,7 @@ Processing: -cd relong +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve [ NOTE] : 0 Processed 122 tests. [ FATAL] : 0 -[ SYNTAX] : 11 +[ SYNTAX] : 39 [ ERROR] : 28 [WARNING] : 128 [ NOTE] : 0