diff --git a/include/Surelog/ErrorReporting/ErrorDefinition.h b/include/Surelog/ErrorReporting/ErrorDefinition.h index 55f74258b3..117cbc72b3 100644 --- a/include/Surelog/ErrorReporting/ErrorDefinition.h +++ b/include/Surelog/ErrorReporting/ErrorDefinition.h @@ -245,6 +245,7 @@ class ErrorDefinition { ELAB_SYSTEM_ERROR = 547, ELAB_SYSTEM_WARNING = 548, ELAB_SYSTEM_INFO = 549, + ELAB_UNKNOWN_PORT = 550, LIB_FILE_MAPS_TO_MULTIPLE_LIBS = 600, UHDM_UNSUPPORTED_EXPR = 700, UHDM_UNSUPPORTED_STMT = 701, @@ -276,7 +277,8 @@ class ErrorDefinition { UHDM_INVALID_CASE_STMT_VALUE = 727, UHDM_UNSUPPORTED_TYPESPEC = 728, UHDM_UNRESOLVED_PROPERTY = 729, - UHDM_NON_TEMPORAL_SEQUENCE_USE = 730 + UHDM_NON_TEMPORAL_SEQUENCE_USE = 730, + UHDM_NON_POSITIVE_VALUE = 731 }; class ErrorInfo { diff --git a/src/DesignCompile/NetlistElaboration.cpp b/src/DesignCompile/NetlistElaboration.cpp index 7bc41cd1be..77d2feaf19 100644 --- a/src/DesignCompile/NetlistElaboration.cpp +++ b/src/DesignCompile/NetlistElaboration.cpp @@ -807,9 +807,11 @@ bool NetlistElaboration::high_conn_(ModuleInstance* instance) { signals = &comp->getPorts(); } std::map allSignals; + std::map allSignalsConst; if (signals) { for (Signal* s : *signals) { allSignals.emplace(s->getName(), s); + allSignalsConst.emplace(s->getName(), s); } } if ((inst_type == VObjectType::paUdp_instantiation) || @@ -1178,6 +1180,24 @@ bool NetlistElaboration::high_conn_(ModuleInstance* instance) { p = s.MakePort(); ports->push_back(p); p->VpiName(formalName); + fC->populateCoreMembers(formalId, formalId, p); + if (!allSignalsConst.empty()) { + auto found = allSignalsConst.find(p->VpiName()); + if (found == allSignalsConst.end()) { + SymbolTable* symbols = + m_compileDesign->getCompiler()->getSymbolTable(); + ErrorContainer* errors = + m_compileDesign->getCompiler()->getErrorContainer(); + Location loc( + fileSystem->toPathId( + p->VpiFile(), + m_compileDesign->getCompiler()->getSymbolTable()), + p->VpiLineNo(), p->VpiColumnNo(), + symbols->registerSymbol(p->VpiName())); + Error err(ErrorDefinition::ELAB_UNKNOWN_PORT, loc); + errors->addError(err); + } + } } } else { ports = s.MakePortVec(); @@ -1198,6 +1218,20 @@ bool NetlistElaboration::high_conn_(ModuleInstance* instance) { VObjectType::paExpression) { // .p(s) connection by name sigId = tmp; Expression = tmp; + if (!allSignalsConst.empty()) { + auto found = allSignalsConst.find(formalName); + if (found == allSignalsConst.end()) { + SymbolTable* symbols = + m_compileDesign->getCompiler()->getSymbolTable(); + ErrorContainer* errors = + m_compileDesign->getCompiler()->getErrorContainer(); + Location loc(fC->getFileId(formalId), fC->Line(formalId), + fC->Column(formalId), + symbols->registerSymbol(formalName)); + Error err(ErrorDefinition::ELAB_UNKNOWN_PORT, loc); + errors->addError(err); + } + } } } // else .p implicit connection } diff --git a/src/ErrorReporting/ErrorDefinition.cpp b/src/ErrorReporting/ErrorDefinition.cpp index 9aae075363..ee10d9f7e9 100644 --- a/src/ErrorReporting/ErrorDefinition.cpp +++ b/src/ErrorReporting/ErrorDefinition.cpp @@ -426,6 +426,7 @@ bool ErrorDefinition::init() { "Skipping blackboxed instance \"%s\""); rec(ELAB_INVALID_CASE_STMT_VALUE, ERROR, ELAB, "Invalid generate case stmt value"); + rec(ELAB_UNKNOWN_PORT, ERROR, ELAB, "Unknown port \"%s\""); rec(ELAB_SYSTEM_FATAL, FATAL, ELAB, "Fatal elaboration %s"); rec(ELAB_SYSTEM_ERROR, ERROR, ELAB, "Elaboration error %s"); rec(ELAB_SYSTEM_WARNING, WARNING, ELAB, "Elaboration warning %s"); @@ -477,6 +478,8 @@ bool ErrorDefinition::init() { rec(UHDM_UNRESOLVED_PROPERTY, ERROR, UHDM, "Unresolved property \"%s\""); rec(UHDM_NON_TEMPORAL_SEQUENCE_USE, ERROR, UHDM, "Sequence used in non-temporal context \"%s\""); + rec(UHDM_NON_POSITIVE_VALUE, ERROR, UHDM, + "Required positive value (>=1), \"%s\" given"); return true; } diff --git a/tests/BindingPort/BindingPort.log b/tests/BindingPort/BindingPort.log new file mode 100644 index 0000000000..5c853fe7f4 --- /dev/null +++ b/tests/BindingPort/BindingPort.log @@ -0,0 +1,334 @@ +[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/BindingPort/slpp_all/surelog.log". +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/BindingPort/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<47> s<46> l<4:1> el<1:4> +n u<2> t p<11> s<3> l<4:1> el<4:7> +n u<3> t p<11> s<10> l<4:8> el<4:12> +n<> u<4> t p<7> s<6> l<5:5> el<5:10> +n<> u<5> t p<6> l<5:11> el<5:11> +n<> u<6> t p<7> c<5> l<5:11> el<5:11> +n<> u<7> t p<9> c<4> s<8> l<5:5> el<5:10> +n u<8> t p<9> l<5:11> el<5:14> +n<> u<9> t p<10> c<7> l<5:5> el<5:14> +n<> u<10> t p<11> c<9> l<4:12> el<6:2> +n<> u<11> t p<13> c<2> s<12> l<4:1> el<6:3> +n<> u<12> t p<13> l<10:1> el<10:10> +n<> u<13> t p<14> c<11> l<4:1> el<10:10> +n<> u<14> t p<46> c<13> s<27> l<4:1> el<10:10> +n u<15> t p<24> s<16> l<13:1> el<13:7> +n u<16> t p<24> s<23> l<13:8> el<13:23> +n<> u<17> t p<20> s<19> l<14:5> el<14:10> +n<> u<18> t p<19> l<14:11> el<14:11> +n<> u<19> t p<20> c<18> l<14:11> el<14:11> +n<> u<20> t p<22> c<17> s<21> l<14:5> el<14:10> +n u<21> t p<22> l<14:11> el<14:14> +n<> u<22> t p<23> c<20> l<14:5> el<14:14> +n<> u<23> t p<24> c<22> l<13:24> el<16:2> +n<> u<24> t p<26> c<15> s<25> l<13:1> el<16:3> +n<> u<25> t p<26> l<19:1> el<19:10> +n<> u<26> t p<27> c<24> l<13:1> el<19:10> +n<> u<27> t p<46> c<26> s<45> l<13:1> el<19:10> +n u<28> t p<44> s<43> l<22:12> el<22:16> +n u<29> t p<42> s<41> l<22:17> el<22:32> +n u<30> t p<31> l<22:33> el<22:36> +n<> u<31> t p<41> c<30> s<40> l<22:33> el<22:36> +n u<32> t p<39> s<37> l<22:38> el<22:43> +n u<33> t p<34> l<22:44> el<22:47> +n<> u<34> t p<35> c<33> l<22:44> el<22:47> +n<> u<35> t p<36> c<34> l<22:44> el<22:47> +n<> u<36> t p<39> c<35> s<38> l<22:44> el<22:47> +n<> u<37> t p<39> s<36> l<22:43> el<22:44> +n<> u<38> t p<39> l<22:47> el<22:48> +n<> u<39> t p<40> c<32> l<22:37> el<22:48> +n<> u<40> t p<41> c<39> l<22:37> el<22:48> +n<> u<41> t p<42> c<31> l<22:33> el<22:49> +n<> u<42> t p<43> c<29> l<22:17> el<22:50> +n<> u<43> t p<44> c<42> l<22:17> el<22:50> +n<> u<44> t p<45> c<28> l<22:7> el<22:50> +n<> u<45> t p<46> c<44> l<22:7> el<22:50> +n<> u<46> t p<47> c<14> l<4:1> el<22:50> +n<> u<47> t c<1> l<4:1> el<22:50> +AST_DEBUG_END +[WRN:PA0205] ${SURELOG_DIR}/tests/BindingPort/dut.sv:4:1: No timescale set for "UART". +[WRN:PA0205] ${SURELOG_DIR}/tests/BindingPort/dut.sv:13:1: No timescale set for "UART_assertions". +[INF:CP0300] Compilation... +[INF:CP0303] ${SURELOG_DIR}/tests/BindingPort/dut.sv:4:1: Compile module "work@UART". +[INF:CP0303] ${SURELOG_DIR}/tests/BindingPort/dut.sv:13:1: Compile module "work@UART_assertions". +[INF:EL0526] Design Elaboration... +[NTE:EL0503] ${SURELOG_DIR}/tests/BindingPort/dut.sv:4:1: Top level module "work@UART". +[ERR:EL0550] ${SURELOG_DIR}/tests/BindingPort/dut.sv:22:38: Unknown port "state". +[NTE:EL0508] Nb Top level modules: 1. +[NTE:EL0509] Max instance depth: 1. +[NTE:EL0510] Nb instances: 3. +[NTE:EL0511] Nb leaf instances: 2. +[INF:UH0706] Creating UHDM Model... +=== UHDM Object Stats Begin (Non-Elaborated Model) === +design 1 +logic_net 5 +logic_typespec 8 +module_inst 7 +port 5 +ref_obj 7 +ref_typespec 8 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... +=== UHDM Object Stats Begin (Elaborated Model) === +design 1 +logic_net 5 +logic_typespec 8 +module_inst 7 +port 8 +ref_obj 12 +ref_typespec 11 +=== UHDM Object Stats End === +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BindingPort/slpp_all/surelog.uhdm ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/BindingPort/slpp_all/checker/surelog.chk.html ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/BindingPort/slpp_all/surelog.uhdm ... +[INF:UH0711] Decompiling UHDM... +====== UHDM ======= +design: (work@UART) +|vpiElaborated:1 +|vpiName:work@UART +|uhdmallModules: +\_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 + |vpiParent: + \_design: (work@UART) + |vpiFullName:work@UART + |vpiDefName:work@UART + |vpiNet: + \_logic_net: (work@UART.clk), line:5:11, endln:5:14 + |vpiParent: + \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 + |vpiName:clk + |vpiFullName:work@UART.clk + |vpiPort: + \_port: (clk), line:5:11, endln:5:14 + |vpiParent: + \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 + |vpiName:clk + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@UART.clk.clk), line:5:11, endln:5:14 + |vpiParent: + \_port: (clk), line:5:11, endln:5:14 + |vpiName:clk + |vpiFullName:work@UART.clk.clk + |vpiActual: + \_logic_net: (work@UART.clk), line:5:11, endln:5:14 + |vpiTypedef: + \_ref_typespec: (work@UART.clk) + |vpiParent: + \_port: (clk), line:5:11, endln:5:14 + |vpiFullName:work@UART.clk + |vpiActual: + \_logic_typespec: , line:5:11, endln:5:11 +|uhdmallModules: +\_module_inst: work@UART_assertions (work@UART_assertions), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:13:1, endln:19:10 + |vpiParent: + \_design: (work@UART) + |vpiFullName:work@UART_assertions + |vpiDefName:work@UART_assertions + |vpiNet: + \_logic_net: (work@UART_assertions.clk), line:14:11, endln:14:14 + |vpiParent: + \_module_inst: work@UART_assertions (work@UART_assertions), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:13:1, endln:19:10 + |vpiName:clk + |vpiFullName:work@UART_assertions.clk + |vpiPort: + \_port: (clk), line:14:11, endln:14:14 + |vpiParent: + \_module_inst: work@UART_assertions (work@UART_assertions), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:13:1, endln:19:10 + |vpiName:clk + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@UART_assertions.clk.clk), line:14:11, endln:14:14 + |vpiParent: + \_port: (clk), line:14:11, endln:14:14 + |vpiName:clk + |vpiFullName:work@UART_assertions.clk.clk + |vpiActual: + \_logic_net: (work@UART_assertions.clk), line:14:11, endln:14:14 + |vpiTypedef: + \_ref_typespec: (work@UART_assertions.clk) + |vpiParent: + \_port: (clk), line:14:11, endln:14:14 + |vpiFullName:work@UART_assertions.clk + |vpiActual: + \_logic_typespec: , line:14:11, endln:14:11 +|uhdmtopModules: +\_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 + |vpiName:work@UART + |vpiDefName:work@UART + |vpiTop:1 + |vpiNet: + \_logic_net: (work@UART.clk), line:5:11, endln:5:14 + |vpiParent: + \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 + |vpiTypespec: + \_ref_typespec: (work@UART.clk) + |vpiParent: + \_logic_net: (work@UART.clk), line:5:11, endln:5:14 + |vpiFullName:work@UART.clk + |vpiActual: + \_logic_typespec: , line:5:11, endln:5:11 + |vpiName:clk + |vpiFullName:work@UART.clk + |vpiTopModule:1 + |vpiPort: + \_port: (clk), line:5:11, endln:5:14 + |vpiParent: + \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 + |vpiName:clk + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@UART.clk), line:5:11, endln:5:14 + |vpiParent: + \_port: (clk), line:5:11, endln:5:14 + |vpiName:clk + |vpiFullName:work@UART.clk + |vpiActual: + \_logic_net: (work@UART.clk), line:5:11, endln:5:14 + |vpiTypedef: + \_ref_typespec: (work@UART.clk) + |vpiParent: + \_port: (clk), line:5:11, endln:5:14 + |vpiFullName:work@UART.clk + |vpiActual: + \_logic_typespec: , line:5:11, endln:5:11 + |vpiInstance: + \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 + |vpiModule: + \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 + |vpiParent: + \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 + |vpiName:uut + |vpiDefName:work@UART_assertions + |vpiDefFile:${SURELOG_DIR}/tests/BindingPort/dut.sv + |vpiDefLineNo:13 + |vpiNet: + \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 + |vpiParent: + \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 + |vpiTypespec: + \_ref_typespec: (work@UART.uut.clk) + |vpiParent: + \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 + |vpiFullName:work@UART.uut.clk + |vpiActual: + \_logic_typespec: , line:14:11, endln:14:11 + |vpiName:clk + |vpiFullName:work@UART.uut.clk + |vpiInstance: + \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 + |vpiPort: + \_port: (state), line:14:11, endln:14:14 + |vpiParent: + \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 + |vpiName:state + |vpiDirection:1 + |vpiHighConn: + \_ref_obj: (work@UART.uut.state.clk), line:22:44, endln:22:47 + |vpiParent: + \_port: (state), line:14:11, endln:14:14 + |vpiName:clk + |vpiFullName:work@UART.uut.state.clk + |vpiActual: + \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 + |vpiLowConn: + \_ref_obj: (uut.clk), line:22:38, endln:22:43 + |vpiParent: + \_port: (state), line:14:11, endln:14:14 + |vpiName:clk + |vpiFullName:uut.clk + |vpiActual: + \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 + |vpiTypedef: + \_ref_typespec: (work@UART.uut.state) + |vpiParent: + \_port: (state), line:14:11, endln:14:14 + |vpiFullName:work@UART.uut.state + |vpiActual: + \_logic_typespec: , line:14:11, endln:14:11 + |vpiInstance: + \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 + |vpiModule: + \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 + |vpiParent: + \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 + |vpiName:uut + |vpiDefName:work@UART_assertions + |vpiDefFile:${SURELOG_DIR}/tests/BindingPort/dut.sv + |vpiDefLineNo:13 + |vpiNet: + \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 + |vpiParent: + \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 + |vpiTypespec: + \_ref_typespec: (work@UART.uut.clk) + |vpiParent: + \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 + |vpiFullName:work@UART.uut.clk + |vpiActual: + \_logic_typespec: , line:14:11, endln:14:11 + |vpiName:clk + |vpiFullName:work@UART.uut.clk + |vpiInstance: + \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10 + |vpiPort: + \_port: (state), line:14:11, endln:14:14 + |vpiParent: + \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 + |vpiName:state + |vpiDirection:1 + |vpiHighConn: + \_ref_obj: (work@UART.uut.state.clk), line:22:44, endln:22:47 + |vpiParent: + \_port: (state), line:14:11, endln:14:14 + |vpiName:clk + |vpiFullName:work@UART.uut.state.clk + |vpiActual: + \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 + |vpiLowConn: + \_ref_obj: (uut.clk), line:22:38, endln:22:43 + |vpiParent: + \_port: (state), line:14:11, endln:14:14 + |vpiName:clk + |vpiFullName:uut.clk + |vpiActual: + \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 + |vpiTypedef: + \_ref_typespec: (work@UART.uut.state) + |vpiParent: + \_port: (state), line:14:11, endln:14:14 + |vpiFullName:work@UART.uut.state + |vpiActual: + \_logic_typespec: , line:14:11, endln:14:11 + |vpiInstance: + \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50 +\_weaklyReferenced: +\_logic_typespec: , line:5:11, endln:5:11 +\_logic_typespec: , line:5:11, endln:5:11 + |vpiParent: + \_logic_net: (work@UART.clk), line:5:11, endln:5:14 +\_logic_typespec: , line:14:11, endln:14:11 +\_logic_typespec: , line:14:11, endln:14:11 + |vpiParent: + \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 +\_logic_typespec: , line:14:11, endln:14:11 +\_logic_typespec: , line:14:11, endln:14:11 + |vpiParent: + \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14 +\_logic_typespec: , line:5:11, endln:5:11 +\_logic_typespec: , line:14:11, endln:14:11 +=================== +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 1 +[WARNING] : 2 +[ NOTE] : 5 + +============================== Begin RoundTrip Results ============================== +[roundtrip]: ${SURELOG_DIR}/tests/BindingPort/dut.sv | ${SURELOG_DIR}/build/regression/BindingPort/roundtrip/dut_000.sv | 4 | 19 | +============================== End RoundTrip Results ============================== diff --git a/tests/BindingPort/BindingPort.sl b/tests/BindingPort/BindingPort.sl new file mode 100644 index 0000000000..b461620aca --- /dev/null +++ b/tests/BindingPort/BindingPort.sl @@ -0,0 +1 @@ +-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin diff --git a/tests/BindingPort/dut.sv b/tests/BindingPort/dut.sv new file mode 100644 index 0000000000..2babf8cdf7 --- /dev/null +++ b/tests/BindingPort/dut.sv @@ -0,0 +1,22 @@ + + + +module UART( + input clk +); + + + +endmodule + + +module UART_assertions ( + input clk + +); + + +endmodule + + + bind UART UART_assertions uut(.state(clk)); \ No newline at end of file diff --git a/tests/LegalPastFunc/LegalPastFunc.log b/tests/LegalPastFunc/LegalPastFunc.log new file mode 100644 index 0000000000..c41bc0e14b --- /dev/null +++ b/tests/LegalPastFunc/LegalPastFunc.log @@ -0,0 +1,492 @@ +[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/LegalPastFunc/slpp_all/surelog.log". +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<115> s<114> l<1:1> el<1:0> +n u<2> t p<6> s<3> l<1:1> el<1:7> +n u<3> t p<6> s<5> l<1:8> el<1:11> +n<> u<4> t p<5> l<1:12> el<1:12> +n<> u<5> t p<6> c<4> l<1:11> el<1:13> +n<> u<6> t p<112> c<2> s<58> l<1:1> el<1:14> +n u<7> t p<51> s<49> l<3:10> el<3:19> +n<> u<8> t p<13> s<12> l<4:6> el<4:13> +n u<9> t p<10> l<4:14> el<4:17> +n<> u<10> t p<11> c<9> l<4:14> el<4:17> +n<> u<11> t p<12> c<10> l<4:14> el<4:17> +n<> u<12> t p<13> c<11> l<4:14> el<4:17> +n<> u<13> t p<14> c<8> l<4:6> el<4:17> +n<> u<14> t p<49> c<13> s<48> l<4:3> el<4:18> +n<> u<15> t p<22> s<16> l<5:3> el<5:4> +n u<16> t p<22> s<21> l<5:4> el<5:8> +n u<17> t p<18> l<5:9> el<5:12> +n<> u<18> t p<19> c<17> l<5:9> el<5:12> +n<> u<19> t p<20> c<18> l<5:9> el<5:12> +n<> u<20> t p<21> c<19> l<5:9> el<5:12> +n<> u<21> t p<22> c<20> l<5:9> el<5:12> +n<> u<22> t p<23> c<15> l<5:3> el<5:13> +n<> u<23> t p<24> c<22> l<5:3> el<5:13> +n<> u<24> t p<25> c<23> l<5:3> el<5:13> +n<> u<25> t p<26> c<24> l<5:3> el<5:13> +n<> u<26> t p<48> c<25> s<28> l<5:3> el<5:13> +n<##1> u<27> t p<28> l<5:14> el<5:17> +n<> u<28> t p<48> c<27> s<47> l<5:14> el<5:17> +n<> u<29> t p<43> s<30> l<5:18> el<5:19> +n u<30> t p<43> s<42> l<5:19> el<5:23> +n u<31> t p<32> l<5:25> el<5:28> +n<> u<32> t p<33> c<31> l<5:25> el<5:28> +n<> u<33> t p<34> c<32> l<5:25> el<5:28> +n<> u<34> t p<36> c<33> l<5:25> el<5:28> +n<> u<35> t p<36> s<34> l<5:24> el<5:25> +n<> u<36> t p<42> c<35> s<41> l<5:24> el<5:28> +n<0> u<37> t p<38> l<5:29> el<5:30> +n<> u<38> t p<39> c<37> l<5:29> el<5:30> +n<> u<39> t p<40> c<38> l<5:29> el<5:30> +n<> u<40> t p<41> c<39> l<5:29> el<5:30> +n<> u<41> t p<42> c<40> l<5:29> el<5:30> +n<> u<42> t p<43> c<36> l<5:24> el<5:30> +n<> u<43> t p<44> c<29> l<5:18> el<5:31> +n<> u<44> t p<45> c<43> l<5:18> el<5:31> +n<> u<45> t p<46> c<44> l<5:18> el<5:31> +n<> u<46> t p<47> c<45> l<5:18> el<5:31> +n<> u<47> t p<48> c<46> l<5:18> el<5:31> +n<> u<48> t p<49> c<26> l<5:3> el<5:31> +n<> u<49> t p<51> c<14> s<50> l<4:3> el<5:31> +n<> u<50> t p<51> l<6:1> el<6:12> +n<> u<51> t p<52> c<7> l<3:1> el<6:12> +n<> u<52> t p<53> c<51> l<3:1> el<6:12> +n<> u<53> t p<54> c<52> l<3:1> el<6:12> +n<> u<54> t p<55> c<53> l<3:1> el<6:12> +n<> u<55> t p<56> c<54> l<3:1> el<6:12> +n<> u<56> t p<57> c<55> l<3:1> el<6:12> +n<> u<57> t p<58> c<56> l<3:1> el<6:12> +n<> u<58> t p<112> c<57> s<110> l<3:1> el<6:12> +n u<59> t p<103> s<101> l<9:10> el<9:18> +n<> u<60> t p<65> s<64> l<10:6> el<10:13> +n u<61> t p<62> l<10:14> el<10:17> +n<> u<62> t p<63> c<61> l<10:14> el<10:17> +n<> u<63> t p<64> c<62> l<10:14> el<10:17> +n<> u<64> t p<65> c<63> l<10:14> el<10:17> +n<> u<65> t p<66> c<60> l<10:6> el<10:17> +n<> u<66> t p<101> c<65> s<100> l<10:3> el<10:18> +n<> u<67> t p<74> s<68> l<11:3> el<11:4> +n u<68> t p<74> s<73> l<11:4> el<11:8> +n u<69> t p<70> l<11:9> el<11:12> +n<> u<70> t p<71> c<69> l<11:9> el<11:12> +n<> u<71> t p<72> c<70> l<11:9> el<11:12> +n<> u<72> t p<73> c<71> l<11:9> el<11:12> +n<> u<73> t p<74> c<72> l<11:9> el<11:12> +n<> u<74> t p<75> c<67> l<11:3> el<11:13> +n<> u<75> t p<76> c<74> l<11:3> el<11:13> +n<> u<76> t p<77> c<75> l<11:3> el<11:13> +n<> u<77> t p<78> c<76> l<11:3> el<11:13> +n<> u<78> t p<100> c<77> s<80> l<11:3> el<11:13> +n<##1> u<79> t p<80> l<11:14> el<11:17> +n<> u<80> t p<100> c<79> s<99> l<11:14> el<11:17> +n<> u<81> t p<95> s<82> l<11:18> el<11:19> +n u<82> t p<95> s<94> l<11:19> el<11:23> +n u<83> t p<84> l<11:25> el<11:28> +n<> u<84> t p<85> c<83> l<11:25> el<11:28> +n<> u<85> t p<86> c<84> l<11:25> el<11:28> +n<> u<86> t p<88> c<85> l<11:25> el<11:28> +n<> u<87> t p<88> s<86> l<11:24> el<11:25> +n<> u<88> t p<94> c<87> s<93> l<11:24> el<11:28> +n<1> u<89> t p<90> l<11:29> el<11:30> +n<> u<90> t p<91> c<89> l<11:29> el<11:30> +n<> u<91> t p<92> c<90> l<11:29> el<11:30> +n<> u<92> t p<93> c<91> l<11:29> el<11:30> +n<> u<93> t p<94> c<92> l<11:29> el<11:30> +n<> u<94> t p<95> c<88> l<11:24> el<11:30> +n<> u<95> t p<96> c<81> l<11:18> el<11:31> +n<> u<96> t p<97> c<95> l<11:18> el<11:31> +n<> u<97> t p<98> c<96> l<11:18> el<11:31> +n<> u<98> t p<99> c<97> l<11:18> el<11:31> +n<> u<99> t p<100> c<98> l<11:18> el<11:31> +n<> u<100> t p<101> c<78> l<11:3> el<11:31> +n<> u<101> t p<103> c<66> s<102> l<10:3> el<11:31> +n<> u<102> t p<103> l<12:1> el<12:12> +n<> u<103> t p<104> c<59> l<9:1> el<12:12> +n<> u<104> t p<105> c<103> l<9:1> el<12:12> +n<> u<105> t p<106> c<104> l<9:1> el<12:12> +n<> u<106> t p<107> c<105> l<9:1> el<12:12> +n<> u<107> t p<108> c<106> l<9:1> el<12:12> +n<> u<108> t p<109> c<107> l<9:1> el<12:12> +n<> u<109> t p<110> c<108> l<9:1> el<12:12> +n<> u<110> t p<112> c<109> s<111> l<9:1> el<12:12> +n<> u<111> t p<112> l<14:1> el<14:10> +n<> u<112> t p<113> c<6> l<1:1> el<14:10> +n<> u<113> t p<114> c<112> l<1:1> el<14:10> +n<> u<114> t p<115> c<113> l<1:1> el<14:10> +n<> u<115> t c<1> l<1:1> el<15:1> +AST_DEBUG_END +[WRN:PA0205] ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:1:1: No timescale set for "top". +[INF:CP0300] Compilation... +[INF:CP0303] ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:1:1: Compile module "work@top". +[INF:EL0526] Design Elaboration... +[NTE:EL0503] ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:1:1: Top level module "work@top". +[NTE:EL0508] Nb Top level modules: 1. +[NTE:EL0509] Max instance depth: 1. +[NTE:EL0510] Nb instances: 1. +[NTE:EL0511] Nb leaf instances: 1. +[INF:UH0706] Creating UHDM Model... +=== UHDM Object Stats Begin (Non-Elaborated Model) === +clocked_seq 2 +constant 4 +design 1 +logic_net 2 +module_inst 2 +multiclock_sequence_expr 2 +operation 6 +ref_obj 6 +sequence_decl 2 +sys_func_call 4 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... +=== UHDM Object Stats Begin (Elaborated Model) === +clocked_seq 4 +constant 4 +design 1 +logic_net 2 +module_inst 2 +multiclock_sequence_expr 4 +operation 12 +ref_obj 12 +sequence_decl 4 +sys_func_call 8 +=== UHDM Object Stats End === +[ERR:UH0731] ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:5:29: Required positive value (>=1), "0" given. +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/LegalPastFunc/slpp_all/surelog.uhdm ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/LegalPastFunc/slpp_all/checker/surelog.chk.html ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/LegalPastFunc/slpp_all/surelog.uhdm ... +[INF:UH0711] Decompiling UHDM... +====== UHDM ======= +design: (work@top) +|vpiElaborated:1 +|vpiName:work@top +|uhdmallModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LegalPastFunc/dut.sv, line:1:1, endln:14:10 + |vpiParent: + \_design: (work@top) + |vpiFullName:work@top + |vpiSequenceDecl: + \_sequence_decl: (work@top.s_req_bad) + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LegalPastFunc/dut.sv, line:1:1, endln:14:10 + |vpiName:s_req_bad + |vpiFullName:work@top.s_req_bad + |vpiExpr: + \_multiclock_sequence_expr: + |vpiClockedSeq: + \_clocked_seq: + |vpiClockingEvent: + \_operation: , line:4:6, endln:4:17 + |vpiParent: + \_sequence_decl: (work@top.s_req_bad) + |vpiOpType:39 + |vpiOperand: + \_ref_obj: (work@top.s_req_bad.clk), line:4:14, endln:4:17 + |vpiParent: + \_operation: , line:4:6, endln:4:17 + |vpiName:clk + |vpiFullName:work@top.s_req_bad.clk + |vpiActual: + \_logic_net: (work@top.clk), line:4:14, endln:4:17 + |vpiSequenceExpr: + \_operation: , line:5:3, endln:5:31 + |vpiParent: + \_sequence_decl: (work@top.s_req_bad) + |vpiOpType:54 + |vpiOperand: + \_sys_func_call: ($rose), line:5:3, endln:5:13 + |vpiParent: + \_operation: , line:5:3, endln:5:31 + |vpiArgument: + \_ref_obj: (work@top.s_req_bad.req), line:5:9, endln:5:12 + |vpiParent: + \_sys_func_call: ($rose), line:5:3, endln:5:13 + |vpiName:req + |vpiFullName:work@top.s_req_bad.req + |vpiActual: + \_logic_net: (work@top.req), line:5:9, endln:5:12 + |vpiName:$rose + |vpiOperand: + \_constant: , line:5:14, endln:5:17 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiOperand: + \_sys_func_call: ($past), line:5:18, endln:5:31 + |vpiParent: + \_operation: , line:5:3, endln:5:31 + |vpiArgument: + \_operation: , line:5:24, endln:5:28 + |vpiParent: + \_sys_func_call: ($past), line:5:18, endln:5:31 + |vpiOpType:3 + |vpiOperand: + \_ref_obj: (work@top.s_req_bad.req), line:5:25, endln:5:28 + |vpiParent: + \_operation: , line:5:24, endln:5:28 + |vpiName:req + |vpiFullName:work@top.s_req_bad.req + |vpiActual: + \_logic_net: (work@top.req), line:5:9, endln:5:12 + |vpiArgument: + \_constant: , line:5:29, endln:5:30 + |vpiParent: + \_sys_func_call: ($past), line:5:18, endln:5:31 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiName:$past + |vpiSequenceDecl: + \_sequence_decl: (work@top.s_req_ok) + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LegalPastFunc/dut.sv, line:1:1, endln:14:10 + |vpiName:s_req_ok + |vpiFullName:work@top.s_req_ok + |vpiExpr: + \_multiclock_sequence_expr: + |vpiClockedSeq: + \_clocked_seq: + |vpiClockingEvent: + \_operation: , line:10:6, endln:10:17 + |vpiParent: + \_sequence_decl: (work@top.s_req_ok) + |vpiOpType:39 + |vpiOperand: + \_ref_obj: (work@top.s_req_ok.clk), line:10:14, endln:10:17 + |vpiParent: + \_operation: , line:10:6, endln:10:17 + |vpiName:clk + |vpiFullName:work@top.s_req_ok.clk + |vpiActual: + \_logic_net: (work@top.clk), line:4:14, endln:4:17 + |vpiSequenceExpr: + \_operation: , line:11:3, endln:11:31 + |vpiParent: + \_sequence_decl: (work@top.s_req_ok) + |vpiOpType:54 + |vpiOperand: + \_sys_func_call: ($rose), line:11:3, endln:11:13 + |vpiParent: + \_operation: , line:11:3, endln:11:31 + |vpiArgument: + \_ref_obj: (work@top.s_req_ok.req), line:11:9, endln:11:12 + |vpiParent: + \_sys_func_call: ($rose), line:11:3, endln:11:13 + |vpiName:req + |vpiFullName:work@top.s_req_ok.req + |vpiActual: + \_logic_net: (work@top.req), line:5:9, endln:5:12 + |vpiName:$rose + |vpiOperand: + \_constant: , line:11:14, endln:11:17 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiOperand: + \_sys_func_call: ($past), line:11:18, endln:11:31 + |vpiParent: + \_operation: , line:11:3, endln:11:31 + |vpiArgument: + \_operation: , line:11:24, endln:11:28 + |vpiParent: + \_sys_func_call: ($past), line:11:18, endln:11:31 + |vpiOpType:3 + |vpiOperand: + \_ref_obj: (work@top.s_req_ok.req), line:11:25, endln:11:28 + |vpiParent: + \_operation: , line:11:24, endln:11:28 + |vpiName:req + |vpiFullName:work@top.s_req_ok.req + |vpiActual: + \_logic_net: (work@top.req), line:5:9, endln:5:12 + |vpiArgument: + \_constant: , line:11:29, endln:11:30 + |vpiParent: + \_sys_func_call: ($past), line:11:18, endln:11:31 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiName:$past + |vpiDefName:work@top + |vpiNet: + \_logic_net: (work@top.clk), line:4:14, endln:4:17 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LegalPastFunc/dut.sv, line:1:1, endln:14:10 + |vpiName:clk + |vpiFullName:work@top.clk + |vpiNetType:1 + |vpiNet: + \_logic_net: (work@top.req), line:5:9, endln:5:12 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LegalPastFunc/dut.sv, line:1:1, endln:14:10 + |vpiName:req + |vpiFullName:work@top.req + |vpiNetType:1 +|uhdmtopModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LegalPastFunc/dut.sv, line:1:1, endln:14:10 + |vpiName:work@top + |vpiSequenceDecl: + \_sequence_decl: (work@top.s_req_bad) + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LegalPastFunc/dut.sv, line:1:1, endln:14:10 + |vpiName:s_req_bad + |vpiFullName:work@top.s_req_bad + |vpiExpr: + \_multiclock_sequence_expr: + |vpiParent: + \_sequence_decl: (work@top.s_req_bad) + |vpiClockedSeq: + \_clocked_seq: + |vpiParent: + \_multiclock_sequence_expr: + |vpiClockingEvent: + \_operation: , line:4:6, endln:4:17 + |vpiParent: + \_clocked_seq: + |vpiOpType:39 + |vpiOperand: + \_ref_obj: (work@top.s_req_bad.clk), line:4:14, endln:4:17 + |vpiParent: + \_operation: , line:4:6, endln:4:17 + |vpiName:clk + |vpiFullName:work@top.s_req_bad.clk + |vpiActual: + \_logic_net: (work@top.clk), line:4:14, endln:4:17 + |vpiSequenceExpr: + \_operation: , line:5:3, endln:5:31 + |vpiParent: + \_clocked_seq: + |vpiOpType:54 + |vpiOperand: + \_sys_func_call: ($rose), line:5:3, endln:5:13 + |vpiParent: + \_operation: , line:5:3, endln:5:31 + |vpiArgument: + \_ref_obj: (work@top.s_req_bad.req), line:5:9, endln:5:12 + |vpiParent: + \_sys_func_call: ($rose), line:5:3, endln:5:13 + |vpiName:req + |vpiFullName:work@top.s_req_bad.req + |vpiActual: + \_logic_net: (work@top.req), line:5:9, endln:5:12 + |vpiName:$rose + |vpiOperand: + \_constant: , line:5:14, endln:5:17 + |vpiOperand: + \_sys_func_call: ($past), line:5:18, endln:5:31 + |vpiParent: + \_operation: , line:5:3, endln:5:31 + |vpiArgument: + \_operation: , line:5:24, endln:5:28 + |vpiParent: + \_sys_func_call: ($past), line:5:18, endln:5:31 + |vpiOpType:3 + |vpiOperand: + \_ref_obj: (work@top.s_req_bad.req), line:5:25, endln:5:28 + |vpiParent: + \_operation: , line:5:24, endln:5:28 + |vpiName:req + |vpiFullName:work@top.s_req_bad.req + |vpiActual: + \_logic_net: (work@top.req), line:5:9, endln:5:12 + |vpiArgument: + \_constant: , line:5:29, endln:5:30 + |vpiName:$past + |vpiSequenceDecl: + \_sequence_decl: (work@top.s_req_ok) + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LegalPastFunc/dut.sv, line:1:1, endln:14:10 + |vpiName:s_req_ok + |vpiFullName:work@top.s_req_ok + |vpiExpr: + \_multiclock_sequence_expr: + |vpiParent: + \_sequence_decl: (work@top.s_req_ok) + |vpiClockedSeq: + \_clocked_seq: + |vpiParent: + \_multiclock_sequence_expr: + |vpiClockingEvent: + \_operation: , line:10:6, endln:10:17 + |vpiParent: + \_clocked_seq: + |vpiOpType:39 + |vpiOperand: + \_ref_obj: (work@top.s_req_ok.clk), line:10:14, endln:10:17 + |vpiParent: + \_operation: , line:10:6, endln:10:17 + |vpiName:clk + |vpiFullName:work@top.s_req_ok.clk + |vpiActual: + \_logic_net: (work@top.clk), line:4:14, endln:4:17 + |vpiSequenceExpr: + \_operation: , line:11:3, endln:11:31 + |vpiParent: + \_clocked_seq: + |vpiOpType:54 + |vpiOperand: + \_sys_func_call: ($rose), line:11:3, endln:11:13 + |vpiParent: + \_operation: , line:11:3, endln:11:31 + |vpiArgument: + \_ref_obj: (work@top.s_req_ok.req), line:11:9, endln:11:12 + |vpiParent: + \_sys_func_call: ($rose), line:11:3, endln:11:13 + |vpiName:req + |vpiFullName:work@top.s_req_ok.req + |vpiActual: + \_logic_net: (work@top.req), line:5:9, endln:5:12 + |vpiName:$rose + |vpiOperand: + \_constant: , line:11:14, endln:11:17 + |vpiOperand: + \_sys_func_call: ($past), line:11:18, endln:11:31 + |vpiParent: + \_operation: , line:11:3, endln:11:31 + |vpiArgument: + \_operation: , line:11:24, endln:11:28 + |vpiParent: + \_sys_func_call: ($past), line:11:18, endln:11:31 + |vpiOpType:3 + |vpiOperand: + \_ref_obj: (work@top.s_req_ok.req), line:11:25, endln:11:28 + |vpiParent: + \_operation: , line:11:24, endln:11:28 + |vpiName:req + |vpiFullName:work@top.s_req_ok.req + |vpiActual: + \_logic_net: (work@top.req), line:5:9, endln:5:12 + |vpiArgument: + \_constant: , line:11:29, endln:11:30 + |vpiName:$past + |vpiDefName:work@top + |vpiTop:1 + |vpiTopModule:1 +=================== +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 1 +[WARNING] : 1 +[ NOTE] : 5 + +============================== Begin Linting Results ============================== +[LINT]: ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:5:29: Non positive (<1) value, 0 +[LINT]: ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:5:29: Non positive (<1) value, 0 +[LINT]: ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:5:3: Non synthesizable construct, $rose +[LINT]: ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:5:18: Non synthesizable construct, $past +[LINT]: ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:1:1: Non synthesizable construct, +[LINT]: ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:5:3: Non synthesizable construct, $rose +[LINT]: ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:5:18: Non synthesizable construct, $past +[LINT]: ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv:1:1: Non synthesizable construct, work@top +============================== End Linting Results ============================== + +============================== Begin RoundTrip Results ============================== +[roundtrip]: ${SURELOG_DIR}/tests/LegalPastFunc/dut.sv | ${SURELOG_DIR}/build/regression/LegalPastFunc/roundtrip/dut_000.sv | 8 | 14 | +============================== End RoundTrip Results ============================== diff --git a/tests/LegalPastFunc/LegalPastFunc.sl b/tests/LegalPastFunc/LegalPastFunc.sl new file mode 100644 index 0000000000..b461620aca --- /dev/null +++ b/tests/LegalPastFunc/LegalPastFunc.sl @@ -0,0 +1 @@ +-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin diff --git a/tests/LegalPastFunc/dut.sv b/tests/LegalPastFunc/dut.sv new file mode 100644 index 0000000000..2bf4b76507 --- /dev/null +++ b/tests/LegalPastFunc/dut.sv @@ -0,0 +1,14 @@ +module top(); + +sequence s_req_bad; + @ (posedge clk) + $rose(req) ##1 $past(!req,0); +endsequence + + +sequence s_req_ok; + @ (posedge clk) + $rose(req) ##1 $past(!req,1); +endsequence + +endmodule diff --git a/third_party/UHDM b/third_party/UHDM index 7e9ae0f58e..c42e783405 160000 --- a/third_party/UHDM +++ b/third_party/UHDM @@ -1 +1 @@ -Subproject commit 7e9ae0f58ec946c021d0321194b2aa198d7bdaa0 +Subproject commit c42e783405bc4991ea3d9f45053527fd762458f8 diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 46d011a605..d0feefec91 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -77,20 +77,20 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required): CMake that the project does not need compatibility with older versions. --- Configuring done (0.1s) +-- Configuring done (0.0s) -- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -[ 6%] Generating 12_beh_lib.sv -[ 12%] Generating 13_ifu_mem_ctl.sv -[ 18%] Generating 11_ifu_bp_ctl.sv -[ 25%] Generating 10_lsu_bus_intf.sv -[ 31%] Generating 14_mem_lib.sv -[ 37%] Generating 15_exu.sv -[ 43%] Generating 16_dec_decode_ctl.sv +[ 6%] Generating 10_lsu_bus_intf.sv +[ 12%] Generating 11_ifu_bp_ctl.sv +[ 18%] Generating 15_exu.sv +[ 25%] Generating 3_rvjtag_tap.sv +[ 31%] Generating 16_dec_decode_ctl.sv +[ 37%] Generating 13_ifu_mem_ctl.sv +[ 43%] Generating 14_mem_lib.sv [ 50%] Generating 1_lsu_stbuf.sv -[ 56%] Generating 2_ahb_to_axi4.sv -[ 62%] Generating 3_rvjtag_tap.sv -[ 68%] Generating 4_dec_tlu_ctl.sv +[ 62%] Generating 4_dec_tlu_ctl.sv +[ 62%] Generating 2_ahb_to_axi4.sv +[ 68%] Generating 12_beh_lib.sv [ 75%] Generating 5_lsu_bus_buffer.sv [ 81%] Generating 6_dbg.sv [ 87%] Generating 7_axi4_to_ahb.sv diff --git a/third_party/tests/Icarus/Icarus.log b/third_party/tests/Icarus/Icarus.log index 16b73bd420..d734793129 100644 --- a/third_party/tests/Icarus/Icarus.log +++ b/third_party/tests/Icarus/Icarus.log @@ -1271,9 +1271,12 @@ Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -t [ NOTE] : 0 Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns contrib8.2.v -l contrib8.2.v.log [WRN:CP0310] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/contrib8.2.v:51:22: Port "%s" definition missing its direction (input, output, inout). +[ERR:EL0550] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/contrib8.2.v:29:13: Unknown port "a". +[ERR:EL0550] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/contrib8.2.v:30:13: Unknown port "a". +[ERR:EL0550] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/contrib8.2.v:31:13: Unknown port "a". [ FATAL] : 0 [ SYNTAX] : 0 -[ ERROR] : 0 +[ ERROR] : 3 [WARNING] : 1 [ NOTE] : 0 Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns mem2port.v -l mem2port.v.log @@ -4239,7 +4242,7 @@ Processing: -cd contrib +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -ti Processed 697 tests. [ FATAL] : 0 [ SYNTAX] : 9 -[ ERROR] : 12 +[ ERROR] : 15 [WARNING] : 15 [ NOTE] : 0 diff --git a/third_party/tests/Verilator/Verilator.log b/third_party/tests/Verilator/Verilator.log index c4b2d1ec88..995e101611 100644 --- a/third_party/tests/Verilator/Verilator.log +++ b/third_party/tests/Verilator/Verilator.log @@ -2992,9 +2992,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [WARNING] : 0 [ NOTE] : 0 Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_past_bad.v -l t_past_bad.v.log +[ERR:UH0731] ${SURELOG_DIR}/third_party/tests/Verilator/t_past_bad.v:11:20: Required positive value (>=1), "0" given. [ FATAL] : 0 [ SYNTAX] : 0 -[ ERROR] : 0 +[ ERROR] : 1 [WARNING] : 0 [ NOTE] : 0 Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_lint_comb_use.v -l t_lint_comb_use.v.log @@ -5650,6 +5651,6 @@ Processing: -cd t_sv_bus_mux_demux +incdir+. -parse -noelab -nocache -nobuiltin Processed 837 tests. [ FATAL] : 0 [ SYNTAX] : 140 -[ ERROR] : 153 +[ ERROR] : 154 [WARNING] : 43 [ NOTE] : 0 diff --git a/third_party/tests/YosysTests/YosysTests.log b/third_party/tests/YosysTests/YosysTests.log index 9742d7254d..159721fdfb 100644 --- a/third_party/tests/YosysTests/YosysTests.log +++ b/third_party/tests/YosysTests/YosysTests.log @@ -888,9 +888,10 @@ Processing: -cd misc/eval_error top.v -writepp -parse -nocache -nobuiltin -nonot [WARNING] : 0 [ NOTE] : 0 Processing: -cd misc/eval_error top_err_1.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top_err_1.v.log +[ERR:EL0550] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/eval_error/top_err_1.v:20:28: Unknown port "y". [ FATAL] : 0 [ SYNTAX] : 0 -[ ERROR] : 0 +[ ERROR] : 1 [WARNING] : 0 [ NOTE] : 0 Processing: -cd misc/abc9_error top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log @@ -10964,6 +10965,6 @@ Processing: -cd regression/issue_01329 synchronizer.sv -writepp -parse -nocache Processed 1309 tests. [ FATAL] : 0 [ SYNTAX] : 229 -[ ERROR] : 38 +[ ERROR] : 39 [WARNING] : 2368 [ NOTE] : 0