From d54719c5faf47e618d39a5e3de56b30122c5c11e Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Sat, 2 Dec 2023 23:13:25 -0800 Subject: [PATCH 1/2] packed_array_var fix --- src/DesignCompile/CompileType.cpp | 3 ++ tests/FuncStruct/FuncStruct.log | 30 +++++++++---------- third_party/UHDM | 2 +- .../tests/CoresSweRVMP/CoresSweRVMP.log | 10 +++---- .../Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log | 6 ++-- .../Earlgrey_Verilator_01_05_21.log | 6 ++-- .../sim-verilator/Earlgrey_Verilator_0_1.log | 6 ++-- third_party/tests/IncompTitan/IncompTitan.log | 2 +- third_party/tests/Opentitan/Earlgrey.log | 6 ++-- third_party/tests/Opentitan/Opentitan.log | 6 ++-- 10 files changed, 40 insertions(+), 37 deletions(-) diff --git a/src/DesignCompile/CompileType.cpp b/src/DesignCompile/CompileType.cpp index b22a2f255e..e909ca665f 100644 --- a/src/DesignCompile/CompileType.cpp +++ b/src/DesignCompile/CompileType.cpp @@ -144,6 +144,7 @@ variables* CompileHelper::getSimpleVarFromTypespec( case uhdmlogic_typespec: { logic_var* logicv = s.MakeLogic_var(); var = logicv; + if (packedDimensions) { packed_array_var* array = s.MakePacked_array_var(); VectorOfany* vars = s.MakeAnyVec(); @@ -154,11 +155,13 @@ variables* CompileHelper::getSimpleVarFromTypespec( var->VpiParent(array); var = array; } + break; } case uhdmvoid_typespec: { logic_var* logicv = s.MakeLogic_var(); var = logicv; + break; } case uhdmunion_typespec: { UHDM::union_var* unionv = s.MakeUnion_var(); diff --git a/tests/FuncStruct/FuncStruct.log b/tests/FuncStruct/FuncStruct.log index cff29e296a..bc5453a5fb 100644 --- a/tests/FuncStruct/FuncStruct.log +++ b/tests/FuncStruct/FuncStruct.log @@ -246,7 +246,7 @@ AST_DEBUG_END assignment 6 begin 2 bit_select 6 -constant 87 +constant 91 cont_assign 4 design 1 func_call 2 @@ -254,7 +254,7 @@ function 2 import_typespec 1 io_decl 4 logic_net 2 -logic_typespec 30 +logic_typespec 32 logic_var 7 module_inst 6 package 2 @@ -262,16 +262,16 @@ packed_array_typespec 2 packed_array_var 4 param_assign 4 parameter 4 -range 36 +range 38 ref_obj 8 -ref_typespec 42 +ref_typespec 44 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === assignment 12 begin 5 bit_select 10 -constant 87 +constant 91 cont_assign 6 design 1 func_call 2 @@ -279,7 +279,7 @@ function 5 import_typespec 1 io_decl 10 logic_net 2 -logic_typespec 30 +logic_typespec 32 logic_var 13 module_inst 6 package 2 @@ -287,9 +287,9 @@ packed_array_typespec 2 packed_array_var 4 param_assign 4 parameter 4 -range 36 +range 38 ref_obj 15 -ref_typespec 54 +ref_typespec 56 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/FuncStruct/slpp_all/surelog.uhdm ... [INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/FuncStruct/slpp_all/checker/surelog.chk.html ... @@ -869,6 +869,13 @@ design: (work@dut) \_bit_select: (work@dut.w), line:17:26, endln:17:27 |vpiParent: \_func_call: (compress), line:17:15, endln:17:35 + |vpiTypespec: + \_ref_typespec: (work@dut.w) + |vpiParent: + \_bit_select: (work@dut.w), line:17:26, endln:17:27 + |vpiFullName:work@dut.w + |vpiActual: + \_logic_typespec: (sha_word_t), line:3:53, endln:3:63 |vpiName:w |vpiFullName:work@dut.w |vpiIndex: @@ -946,13 +953,6 @@ design: (work@dut) \_logic_var: (work@dut.w) |vpiParent: \_packed_array_var: (work@dut.w), line:14:19, endln:14:20 - |vpiTypespec: - \_ref_typespec: (work@dut.w) - |vpiParent: - \_logic_var: (work@dut.w) - |vpiFullName:work@dut.w - |vpiActual: - \_logic_typespec: (sha_word_t), line:3:53, endln:3:63 |vpiFullName:work@dut.w |vpiVariables: \_packed_array_var: (work@dut.hash), line:15:18, endln:15:22 diff --git a/third_party/UHDM b/third_party/UHDM index 2caa9829bb..7b8baa33da 160000 --- a/third_party/UHDM +++ b/third_party/UHDM @@ -1 +1 @@ -Subproject commit 2caa9829bb0357db7b482a51674692d1225216a3 +Subproject commit 7b8baa33da7a8735c5138f1c961e55409741621f diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 4a5fb76796..8facd57b92 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -77,13 +77,13 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required): CMake that the project does not need compatibility with older versions. --- Configuring done (0.0s) +-- Configuring done (0.1s) -- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess [ 6%] Generating 10_lsu_bus_intf.sv [ 12%] Generating 11_ifu_bp_ctl.sv -[ 18%] Generating 13_ifu_mem_ctl.sv -[ 25%] Generating 12_beh_lib.sv +[ 18%] Generating 12_beh_lib.sv +[ 25%] Generating 13_ifu_mem_ctl.sv [ 31%] Generating 14_mem_lib.sv [ 37%] Generating 15_exu.sv [ 43%] Generating 16_dec_decode_ctl.sv @@ -93,8 +93,8 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required): [ 68%] Generating 4_dec_tlu_ctl.sv [ 75%] Generating 5_lsu_bus_buffer.sv [ 81%] Generating 6_dbg.sv -[ 87%] Generating 8_ifu_aln_ctl.sv -[ 93%] Generating 7_axi4_to_ahb.sv +[ 87%] Generating 7_axi4_to_ahb.sv +[ 93%] Generating 8_ifu_aln_ctl.sv [100%] Generating 9_tb_top.sv [100%] Built target Parse Surelog parsing status: 0 diff --git a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log index 2bb4a6122e..cf7e82c869 100644 --- a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log +++ b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log @@ -6169,7 +6169,7 @@ case_stmt 231 class_defn 8 class_typespec 4 class_var 3 -constant 344034 +constant 344035 cont_assign 19794 design 1 enum_const 2548 @@ -6244,7 +6244,7 @@ case_stmt 614 class_defn 8 class_typespec 4 class_var 3 -constant 348743 +constant 348744 cont_assign 47364 design 1 enum_const 2553 @@ -6289,7 +6289,7 @@ property_spec 4 range 48605 ref_module 1917 ref_obj 389028 -ref_typespec 208060 +ref_typespec 208061 ref_var 80 return_stmt 1419 string_typespec 4099 diff --git a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log index bc1d2b95c7..4057564df7 100644 --- a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log +++ b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log @@ -14342,7 +14342,7 @@ chandle_var 14 class_defn 8 class_typespec 4 class_var 3 -constant 926726 +constant 926727 cont_assign 39267 design 1 enum_const 31253 @@ -14427,7 +14427,7 @@ chandle_var 14 class_defn 8 class_typespec 4 class_var 3 -constant 936086 +constant 936087 cont_assign 147474 design 1 enum_const 31258 @@ -14476,7 +14476,7 @@ port 224742 range 171087 ref_module 5040 ref_obj 1087996 -ref_typespec 796719 +ref_typespec 796720 ref_var 176 return_stmt 15514 string_typespec 37103 diff --git a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log index ccf4793fab..5fe26ff5bf 100644 --- a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log +++ b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log @@ -5824,7 +5824,7 @@ chandle_var 11 class_defn 8 class_typespec 4 class_var 3 -constant 321232 +constant 321233 cont_assign 19205 design 1 enum_const 2446 @@ -5905,7 +5905,7 @@ chandle_var 11 class_defn 8 class_typespec 4 class_var 3 -constant 325987 +constant 325988 cont_assign 43470 design 1 enum_const 2451 @@ -5951,7 +5951,7 @@ port 64704 range 49771 ref_module 1821 ref_obj 371893 -ref_typespec 202182 +ref_typespec 202183 ref_var 82 return_stmt 2045 string_typespec 4158 diff --git a/third_party/tests/IncompTitan/IncompTitan.log b/third_party/tests/IncompTitan/IncompTitan.log index 06c1becb8b..cb4cfd6294 100644 --- a/third_party/tests/IncompTitan/IncompTitan.log +++ b/third_party/tests/IncompTitan/IncompTitan.log @@ -5336,7 +5336,7 @@ case_stmt 117 class_defn 8 class_typespec 4 class_var 3 -constant 403122 +constant 403123 cont_assign 18019 cover 20 design 1 diff --git a/third_party/tests/Opentitan/Earlgrey.log b/third_party/tests/Opentitan/Earlgrey.log index d33c9abf2f..7a751ab1b1 100644 --- a/third_party/tests/Opentitan/Earlgrey.log +++ b/third_party/tests/Opentitan/Earlgrey.log @@ -25175,7 +25175,7 @@ case_stmt 132 class_defn 8 class_typespec 4 class_var 3 -constant 213979 +constant 213980 cont_assign 13781 design 1 enum_const 2016 @@ -25248,7 +25248,7 @@ case_stmt 336 class_defn 8 class_typespec 4 class_var 3 -constant 217424 +constant 217425 cont_assign 30746 design 1 enum_const 2021 @@ -25291,7 +25291,7 @@ property_spec 4 range 36105 ref_module 1426 ref_obj 265401 -ref_typespec 148129 +ref_typespec 148130 ref_var 51 return_stmt 424 string_typespec 2758 diff --git a/third_party/tests/Opentitan/Opentitan.log b/third_party/tests/Opentitan/Opentitan.log index e240eca012..8a930b97ca 100644 --- a/third_party/tests/Opentitan/Opentitan.log +++ b/third_party/tests/Opentitan/Opentitan.log @@ -4190,7 +4190,7 @@ chandle_var 2 class_defn 613 class_typespec 8456 class_var 3308 -constant 248584 +constant 248585 constraint 4 cont_assign 13810 continue_stmt 52 @@ -4307,7 +4307,7 @@ chandle_var 2 class_defn 613 class_typespec 8828 class_var 22226 -constant 252354 +constant 252355 constraint 10 cont_assign 30814 continue_stmt 173 @@ -4378,7 +4378,7 @@ real_typespec 33 real_var 10 ref_module 1427 ref_obj 563093 -ref_typespec 269985 +ref_typespec 269986 ref_var 8711 repeat 207 return_stmt 19839 From 817a850fc03a986683ac8c1975bcdebd8351f416 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Sat, 2 Dec 2023 23:16:37 -0800 Subject: [PATCH 2/2] packed_array_var fix --- .../PackedArrayHighConn.log | 951 ++++++++++++++++++ .../PackedArrayHighConn.sl | 1 + tests/PackedArrayHighConn/dut.sv | 63 ++ 3 files changed, 1015 insertions(+) create mode 100644 tests/PackedArrayHighConn/PackedArrayHighConn.log create mode 100644 tests/PackedArrayHighConn/PackedArrayHighConn.sl create mode 100644 tests/PackedArrayHighConn/dut.sv diff --git a/tests/PackedArrayHighConn/PackedArrayHighConn.log b/tests/PackedArrayHighConn/PackedArrayHighConn.log new file mode 100644 index 0000000000..05606660af --- /dev/null +++ b/tests/PackedArrayHighConn/PackedArrayHighConn.log @@ -0,0 +1,951 @@ +[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/PackedArrayHighConn/slpp_all/surelog.log". +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<168> s<167> l<1:1> el<1:0> +n<> u<2> t p<47> s<3> l<1:1> el<1:8> +n u<3> t p<47> s<27> l<1:9> el<1:29> +n<> u<4> t p<15> s<14> l<2:16> el<2:21> +n<2> u<5> t p<6> l<2:23> el<2:24> +n<> u<6> t p<7> c<5> l<2:23> el<2:24> +n<> u<7> t p<8> c<6> l<2:23> el<2:24> +n<> u<8> t p<13> c<7> s<12> l<2:23> el<2:24> +n<0> u<9> t p<10> l<2:25> el<2:26> +n<> u<10> t p<11> c<9> l<2:25> el<2:26> +n<> u<11> t p<12> c<10> l<2:25> el<2:26> +n<> u<12> t p<13> c<11> l<2:25> el<2:26> +n<> u<13> t p<14> c<8> l<2:23> el<2:26> +n<> u<14> t p<15> c<13> l<2:22> el<2:27> +n<> u<15> t p<22> c<4> s<21> l<2:16> el<2:27> +n u<16> t p<21> s<20> l<3:5> el<3:13> +n<3'h0> u<17> t p<18> l<3:16> el<3:20> +n<> u<18> t p<19> c<17> l<3:16> el<3:20> +n<> u<19> t p<20> c<18> l<3:16> el<3:20> +n<> u<20> t p<21> c<19> l<3:16> el<3:20> +n<> u<21> t p<22> c<16> l<3:5> el<3:20> +n<> u<22> t p<24> c<15> s<23> l<2:11> el<4:4> +n u<23> t p<24> l<4:5> el<4:15> +n<> u<24> t p<25> c<22> l<2:3> el<4:16> +n<> u<25> t p<26> c<24> l<2:3> el<4:16> +n<> u<26> t p<27> c<25> l<2:3> el<4:16> +n<> u<27> t p<47> c<26> s<44> l<2:3> el<4:16> +n<> u<28> t p<39> s<38> l<5:11> el<5:16> +n<7> u<29> t p<30> l<5:18> el<5:19> +n<> u<30> t p<31> c<29> l<5:18> el<5:19> +n<> u<31> t p<32> c<30> l<5:18> el<5:19> +n<> u<32> t p<37> c<31> s<36> l<5:18> el<5:19> +n<0> u<33> t p<34> l<5:20> el<5:21> +n<> u<34> t p<35> c<33> l<5:20> el<5:21> +n<> u<35> t p<36> c<34> l<5:20> el<5:21> +n<> u<36> t p<37> c<35> l<5:20> el<5:21> +n<> u<37> t p<38> c<32> l<5:18> el<5:21> +n<> u<38> t p<39> c<37> l<5:17> el<5:22> +n<> u<39> t p<41> c<28> s<40> l<5:11> el<5:22> +n u<40> t p<41> l<5:23> el<5:32> +n<> u<41> t p<42> c<39> l<5:3> el<5:33> +n<> u<42> t p<43> c<41> l<5:3> el<5:33> +n<> u<43> t p<44> c<42> l<5:3> el<5:33> +n<> u<44> t p<47> c<43> s<46> l<5:3> el<5:33> +n u<45> t p<47> l<6:14> el<6:34> +n<> u<46> t p<47> s<45> l<6:1> el<6:11> +n<> u<47> t p<48> c<2> l<1:1> el<6:34> +n<> u<48> t p<167> c<47> s<67> l<1:1> el<6:34> +n u<49> t p<63> s<50> l<8:1> el<8:7> +n u<50> t p<63> s<53> l<8:8> el<8:24> +n u<51> t p<52> l<9:10> el<9:30> +n<> u<52> t p<53> c<51> l<9:10> el<9:33> +n<> u<53> t p<63> c<52> s<62> l<9:3> el<9:34> +n<> u<54> t p<59> s<58> l<9:36> el<9:41> +n u<55> t p<56> l<9:42> el<9:51> +n<> u<56> t p<57> c<55> l<9:42> el<9:51> +n<> u<57> t p<58> c<56> l<9:42> el<9:51> +n<> u<58> t p<59> c<57> l<9:42> el<9:51> +n<> u<59> t p<61> c<54> s<60> l<9:36> el<9:51> +n u<60> t p<61> l<9:52> el<9:57> +n<> u<61> t p<62> c<59> l<9:36> el<9:57> +n<> u<62> t p<63> c<61> l<9:35> el<9:58> +n<> u<63> t p<66> c<49> s<65> l<8:1> el<9:59> +n u<64> t p<66> l<10:13> el<10:29> +n<> u<65> t p<66> s<64> l<10:1> el<10:10> +n<> u<66> t p<67> c<63> l<8:1> el<10:29> +n<> u<67> t p<167> c<66> s<166> l<8:1> el<10:29> +n u<68> t p<110> s<69> l<12:1> el<12:7> +n u<69> t p<110> s<72> l<12:8> el<12:11> +n u<70> t p<71> l<13:10> el<13:30> +n<> u<71> t p<72> c<70> l<13:10> el<13:33> +n<> u<72> t p<110> c<71> s<107> l<13:3> el<13:34> +n<> u<73> t p<94> s<83> l<13:47> el<13:52> +n<0> u<74> t p<75> l<13:54> el<13:55> +n<> u<75> t p<76> c<74> l<13:54> el<13:55> +n<> u<76> t p<77> c<75> l<13:54> el<13:55> +n<> u<77> t p<82> c<76> s<81> l<13:54> el<13:55> +n<0> u<78> t p<79> l<13:56> el<13:57> +n<> u<79> t p<80> c<78> l<13:56> el<13:57> +n<> u<80> t p<81> c<79> l<13:56> el<13:57> +n<> u<81> t p<82> c<80> l<13:56> el<13:57> +n<> u<82> t p<83> c<77> l<13:54> el<13:57> +n<> u<83> t p<94> c<82> s<93> l<13:53> el<13:58> +n<1> u<84> t p<85> l<13:59> el<13:60> +n<> u<85> t p<86> c<84> l<13:59> el<13:60> +n<> u<86> t p<87> c<85> l<13:59> el<13:60> +n<> u<87> t p<92> c<86> s<91> l<13:59> el<13:60> +n<0> u<88> t p<89> l<13:61> el<13:62> +n<> u<89> t p<90> c<88> l<13:61> el<13:62> +n<> u<90> t p<91> c<89> l<13:61> el<13:62> +n<> u<91> t p<92> c<90> l<13:61> el<13:62> +n<> u<92> t p<93> c<87> l<13:59> el<13:62> +n<> u<93> t p<94> c<92> l<13:58> el<13:63> +n<> u<94> t p<95> c<73> l<13:47> el<13:63> +n<> u<95> t p<105> c<94> s<104> l<13:47> el<13:63> +n u<96> t p<103> s<102> l<13:64> el<13:74> +n<> u<97> t p<98> l<13:77> el<13:79> +n<> u<98> t p<99> c<97> l<13:77> el<13:79> +n<> u<99> t p<100> c<98> l<13:77> el<13:79> +n<> u<100> t p<101> c<99> l<13:77> el<13:79> +n<> u<101> t p<102> c<100> l<13:77> el<13:79> +n<> u<102> t p<103> c<101> l<13:77> el<13:79> +n<> u<103> t p<104> c<96> l<13:64> el<13:79> +n<> u<104> t p<105> c<103> l<13:64> el<13:79> +n<> u<105> t p<106> c<95> l<13:37> el<13:79> +n<> u<106> t p<107> c<105> l<13:37> el<13:79> +n<> u<107> t p<110> c<106> s<109> l<13:35> el<13:80> +n<> u<108> t p<109> l<13:82> el<13:82> +n<> u<109> t p<110> c<108> l<13:81> el<13:83> +n<> u<110> t p<165> c<68> s<133> l<12:1> el<13:84> +n u<111> t p<122> s<121> l<14:3> el<14:12> +n<3> u<112> t p<113> l<14:14> el<14:15> +n<> u<113> t p<114> c<112> l<14:14> el<14:15> +n<> u<114> t p<115> c<113> l<14:14> el<14:15> +n<> u<115> t p<120> c<114> s<119> l<14:14> el<14:15> +n<0> u<116> t p<117> l<14:16> el<14:17> +n<> u<117> t p<118> c<116> l<14:16> el<14:17> +n<> u<118> t p<119> c<117> l<14:16> el<14:17> +n<> u<119> t p<120> c<118> l<14:16> el<14:17> +n<> u<120> t p<121> c<115> l<14:14> el<14:17> +n<> u<121> t p<122> c<120> l<14:13> el<14:18> +n<> u<122> t p<126> c<111> s<125> l<14:3> el<14:18> +n u<123> t p<124> l<14:19> el<14:26> +n<> u<124> t p<125> c<123> l<14:19> el<14:26> +n<> u<125> t p<126> c<124> l<14:19> el<14:26> +n<> u<126> t p<127> c<122> l<14:3> el<14:27> +n<> u<127> t p<128> c<126> l<14:3> el<14:27> +n<> u<128> t p<129> c<127> l<14:3> el<14:27> +n<> u<129> t p<130> c<128> l<14:3> el<14:27> +n<> u<130> t p<131> c<129> l<14:3> el<14:27> +n<> u<131> t p<132> c<130> l<14:3> el<14:27> +n<> u<132> t p<133> c<131> l<14:3> el<14:27> +n<> u<133> t p<165> c<132> s<162> l<14:3> el<14:27> +n u<134> t p<159> s<158> l<15:3> el<15:19> +n u<135> t p<136> l<15:20> el<15:29> +n<> u<136> t p<158> c<135> s<157> l<15:20> el<15:29> +n u<137> t p<156> s<154> l<16:6> el<16:11> +n u<138> t p<151> s<150> l<16:19> el<16:26> +n u<139> t p<146> s<145> l<16:27> el<16:37> +n<0> u<140> t p<141> l<16:38> el<16:39> +n<> u<141> t p<142> c<140> l<16:38> el<16:39> +n<> u<142> t p<143> c<141> l<16:38> el<16:39> +n<> u<143> t p<144> c<142> l<16:38> el<16:39> +n<> u<144> t p<145> c<143> l<16:37> el<16:40> +n<> u<145> t p<151> c<149> l<16:26> el<16:41> +n<> u<151> t p<152> c<138> l<16:19> el<16:41> +n<> u<152> t p<153> c<151> l<16:19> el<16:41> +n<> u<153> t p<156> c<152> s<155> l<16:19> el<16:41> +n<> u<154> t p<156> s<153> l<16:17> el<16:18> +n<> u<155> t p<156> l<16:44> el<16:45> +n<> u<156> t p<157> c<137> l<16:5> el<16:45> +n<> u<157> t p<158> c<156> l<16:5> el<16:45> +n<> u<158> t p<159> c<136> l<15:20> el<17:4> +n<> u<159> t p<160> c<134> l<15:3> el<17:5> +n<> u<160> t p<161> c<159> l<15:3> el<17:5> +n<> u<161> t p<162> c<160> l<15:3> el<17:5> +n<> u<162> t p<165> c<161> s<164> l<15:3> el<17:5> +n u<163> t p<165> l<18:13> el<18:16> +n<> u<164> t p<165> s<163> l<18:1> el<18:10> +n<> u<165> t p<166> c<110> l<12:1> el<18:16> +n<> u<166> t p<167> c<165> l<12:1> el<18:16> +n<> u<167> t p<168> c<48> l<1:1> el<18:16> +n<> u<168> t c<1> l<1:1> el<63:3> +AST_DEBUG_END +[WRN:PA0205] ${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv:1:1: No timescale set for "prim_pad_wrapper_pkg". +[WRN:PA0205] ${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv:8:1: No timescale set for "prim_pad_wrapper". +[WRN:PA0205] ${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv:12:1: No timescale set for "dut". +[INF:CP0300] Compilation... +[INF:CP0301] ${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv:1:1: Compile package "prim_pad_wrapper_pkg". +[INF:CP0303] ${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv:12:1: Compile module "work@dut". +[INF:CP0303] ${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv:8:1: Compile module "work@prim_pad_wrapper". +[INF:EL0526] Design Elaboration... +[NTE:EL0503] ${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv:12:1: Top level module "work@dut". +[NTE:EL0508] Nb Top level modules: 1. +[NTE:EL0509] Max instance depth: 2. +[NTE:EL0510] Nb instances: 2. +[NTE:EL0511] Nb leaf instances: 1. +[INF:UH0706] Creating UHDM Model... +=== UHDM Object Stats Begin (Non-Elaborated Model) === +bit_select 4 +constant 50 +design 1 +enum_const 2 +enum_typespec 2 +import_typespec 2 +logic_net 3 +logic_typespec 14 +logic_var 1 +module_inst 9 +package 2 +packed_array_typespec 2 +packed_array_var 1 +param_assign 2 +parameter 2 +port 3 +range 19 +ref_module 1 +ref_obj 2 +ref_typespec 18 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... +=== UHDM Object Stats Begin (Elaborated Model) === +bit_select 5 +constant 50 +design 1 +enum_const 2 +enum_typespec 2 +import_typespec 2 +logic_net 3 +logic_typespec 14 +logic_var 1 +module_inst 9 +package 2 +packed_array_typespec 2 +packed_array_var 1 +param_assign 2 +parameter 2 +port 4 +range 19 +ref_module 1 +ref_obj 3 +ref_typespec 19 +=== UHDM Object Stats End === +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/PackedArrayHighConn/slpp_all/surelog.uhdm ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/PackedArrayHighConn/slpp_all/checker/surelog.chk.html ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/PackedArrayHighConn/slpp_all/surelog.uhdm ... +[INF:UH0711] Decompiling UHDM... +====== UHDM ======= +design: (work@dut) +|vpiElaborated:1 +|vpiName:work@dut +|uhdmallPackages: +\_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiParent: + \_design: (work@dut) + |vpiName:prim_pad_wrapper_pkg + |vpiFullName:prim_pad_wrapper_pkg:: + |vpiTypedef: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiParent: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiName:prim_pad_wrapper_pkg::pad_pok_t + |vpiInstance: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiRange: + \_range: , line:5:17, endln:5:22 + |vpiParent: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiLeftRange: + \_constant: , line:5:18, endln:5:19 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:20, endln:5:21 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiTypedef: + \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:3, endln:4:16 + |vpiParent: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiName:prim_pad_wrapper_pkg::pad_type_e + |vpiInstance: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiBaseTypespec: + \_ref_typespec: (prim_pad_wrapper_pkg::prim_pad_wrapper_pkg::pad_type_e) + |vpiParent: + \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:3, endln:4:16 + |vpiFullName:prim_pad_wrapper_pkg::prim_pad_wrapper_pkg::pad_type_e + |vpiActual: + \_logic_typespec: , line:2:16, endln:2:27 + |vpiEnumConst: + \_enum_const: (BidirStd), line:3:5, endln:3:20 + |vpiParent: + \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:3, endln:4:16 + |vpiName:BidirStd + |HEX:0 + |vpiDecompile:3'h0 + |vpiSize:3 + |vpiDefName:prim_pad_wrapper_pkg + |vpiEndLabel:prim_pad_wrapper_pkg +|uhdmtopPackages: +\_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiParent: + \_design: (work@dut) + |vpiName:prim_pad_wrapper_pkg + |vpiFullName:prim_pad_wrapper_pkg:: + |vpiTypedef: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiParent: + \_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:8:1, endln:10:29 + |vpiName:prim_pad_wrapper_pkg::pad_pok_t + |vpiInstance: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiRange: + \_range: , line:5:17, endln:5:22 + |vpiParent: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiLeftRange: + \_constant: , line:5:18, endln:5:19 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:20, endln:5:21 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiTypedef: + \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:3, endln:4:16 + |vpiParent: + \_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:8:1, endln:10:29 + |vpiName:prim_pad_wrapper_pkg::pad_type_e + |vpiInstance: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiBaseTypespec: + \_ref_typespec: (work@prim_pad_wrapper.prim_pad_wrapper_pkg::pad_type_e) + |vpiParent: + \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:3, endln:4:16 + |vpiFullName:work@prim_pad_wrapper.prim_pad_wrapper_pkg::pad_type_e + |vpiActual: + \_logic_typespec: , line:2:16, endln:2:27 + |vpiEnumConst: + \_enum_const: (BidirStd), line:3:5, endln:3:20 + |vpiParent: + \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:3, endln:4:16 + |vpiName:BidirStd + |HEX:0 + |vpiDecompile:3'h0 + |vpiSize:3 + |vpiDefName:prim_pad_wrapper_pkg + |vpiTop:1 + |vpiEndLabel:prim_pad_wrapper_pkg +|uhdmallModules: +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:12:1, endln:18:16 + |vpiParent: + \_design: (work@dut) + |vpiFullName:work@dut + |vpiParameter: + \_parameter: (work@dut.DioPadBank), line:13:64, endln:13:74 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:12:1, endln:18:16 + |BIN:0 + |vpiTypespec: + \_ref_typespec: (work@dut.DioPadBank) + |vpiParent: + \_parameter: (work@dut.DioPadBank), line:13:64, endln:13:74 + |vpiFullName:work@dut.DioPadBank + |vpiActual: + \_logic_typespec: , line:13:47, endln:13:63 + |vpiName:DioPadBank + |vpiFullName:work@dut.DioPadBank + |vpiParamAssign: + \_param_assign: , line:13:64, endln:13:79 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:12:1, endln:18:16 + |vpiRhs: + \_constant: , line:13:77, endln:13:79 + |vpiParent: + \_param_assign: , line:13:64, endln:13:79 + |vpiDecompile:'0 + |vpiSize:-1 + |BIN:0 + |vpiTypespec: + \_ref_typespec: (work@dut) + |vpiParent: + \_constant: , line:13:77, endln:13:79 + |vpiFullName:work@dut + |vpiActual: + \_logic_typespec: , line:13:47, endln:13:63 + |vpiConstType:3 + |vpiLhs: + \_parameter: (work@dut.DioPadBank), line:13:64, endln:13:74 + |vpiTypedef: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiTypedef: + \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:3, endln:4:16 + |vpiTypedef: + \_import_typespec: (prim_pad_wrapper_pkg), line:13:10, endln:13:33 + |vpiDefName:work@dut + |vpiNet: + \_logic_net: (work@dut.pad_pok), line:14:19, endln:14:26 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:12:1, endln:18:16 + |vpiTypespec: + \_ref_typespec: (work@dut.pad_pok) + |vpiParent: + \_logic_net: (work@dut.pad_pok), line:14:19, endln:14:26 + |vpiFullName:work@dut.pad_pok + |vpiActual: + \_logic_typespec: , line:14:3, endln:14:18 + |vpiName:pad_pok + |vpiFullName:work@dut.pad_pok + |vpiNetType:36 + |vpiRefModule: + \_ref_module: work@prim_pad_wrapper (u_dio_pad), line:15:20, endln:15:29 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:12:1, endln:18:16 + |vpiName:u_dio_pad + |vpiDefName:work@prim_pad_wrapper + |vpiActual: + \_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:8:1, endln:10:29 + |vpiPort: + \_port: (pok_i), line:16:5, endln:16:45 + |vpiParent: + \_ref_module: work@prim_pad_wrapper (u_dio_pad), line:15:20, endln:15:29 + |vpiName:pok_i + |vpiHighConn: + \_bit_select: (work@dut.u_dio_pad.pad_pok), line:16:27, endln:16:40 + |vpiParent: + \_port: (pok_i), line:16:5, endln:16:45 + |vpiName:pad_pok + |vpiFullName:work@dut.u_dio_pad.pad_pok + |vpiIndex: + \_bit_select: (work@dut.u_dio_pad.pad_pok.DioPadBank), line:16:38, endln:16:39 + |vpiParent: + \_bit_select: (work@dut.u_dio_pad.pad_pok), line:16:27, endln:16:40 + |vpiName:DioPadBank + |vpiFullName:work@dut.u_dio_pad.pad_pok.DioPadBank + |vpiIndex: + \_constant: , line:16:38, endln:16:39 + |vpiParent: + \_bit_select: (work@dut.u_dio_pad.pad_pok.DioPadBank), line:16:38, endln:16:39 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiEndLabel:dut +|uhdmallModules: +\_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:8:1, endln:10:29 + |vpiParent: + \_design: (work@dut) + |vpiFullName:work@prim_pad_wrapper + |vpiTypedef: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiTypedef: + \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:3, endln:4:16 + |vpiTypedef: + \_import_typespec: (prim_pad_wrapper_pkg), line:9:10, endln:9:33 + |vpiDefName:work@prim_pad_wrapper + |vpiNet: + \_logic_net: (work@prim_pad_wrapper.pok_i), line:9:52, endln:9:57 + |vpiParent: + \_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:8:1, endln:10:29 + |vpiName:pok_i + |vpiFullName:work@prim_pad_wrapper.pok_i + |vpiNetType:36 + |vpiPort: + \_port: (pok_i), line:9:52, endln:9:57 + |vpiParent: + \_module_inst: work@prim_pad_wrapper (work@prim_pad_wrapper), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:8:1, endln:10:29 + |vpiName:pok_i + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@prim_pad_wrapper.pok_i.pok_i), line:9:52, endln:9:57 + |vpiParent: + \_port: (pok_i), line:9:52, endln:9:57 + |vpiName:pok_i + |vpiFullName:work@prim_pad_wrapper.pok_i.pok_i + |vpiActual: + \_logic_net: (work@prim_pad_wrapper.pok_i), line:9:52, endln:9:57 + |vpiTypedef: + \_ref_typespec: (work@prim_pad_wrapper.pok_i) + |vpiParent: + \_port: (pok_i), line:9:52, endln:9:57 + |vpiFullName:work@prim_pad_wrapper.pok_i + |vpiActual: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiEndLabel:prim_pad_wrapper +|uhdmtopModules: +\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:12:1, endln:18:16 + |vpiName:work@dut + |vpiVariables: + \_packed_array_var: (work@dut.pad_pok), line:14:19, endln:14:26 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:12:1, endln:18:16 + |vpiTypespec: + \_ref_typespec: (work@dut.pad_pok) + |vpiParent: + \_packed_array_var: (work@dut.pad_pok), line:14:19, endln:14:26 + |vpiFullName:work@dut.pad_pok + |vpiActual: + \_logic_typespec: (pad_pok_t), line:5:11, endln:5:22 + |vpiName:pad_pok + |vpiFullName:work@dut.pad_pok + |vpiVisibility:1 + |vpiRange: + \_range: , line:14:13, endln:14:18 + |vpiParent: + \_packed_array_var: (work@dut.pad_pok), line:14:19, endln:14:26 + |vpiLeftRange: + \_constant: , line:14:14, endln:14:15 + |vpiParent: + \_range: , line:14:13, endln:14:18 + |vpiDecompile:3 + |vpiSize:64 + |UINT:3 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:14:16, endln:14:17 + |vpiParent: + \_range: , line:14:13, endln:14:18 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiElement: + \_logic_var: (work@dut.pad_pok) + |vpiParent: + \_packed_array_var: (work@dut.pad_pok), line:14:19, endln:14:26 + |vpiFullName:work@dut.pad_pok + |vpiParameter: + \_parameter: (work@dut.DioPadBank), line:13:64, endln:13:74 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:12:1, endln:18:16 + |BIN:0 + |vpiTypespec: + \_ref_typespec: (work@dut.DioPadBank) + |vpiParent: + \_parameter: (work@dut.DioPadBank), line:13:64, endln:13:74 + |vpiFullName:work@dut.DioPadBank + |vpiActual: + \_logic_typespec: , line:13:47, endln:13:63 + |vpiName:DioPadBank + |vpiFullName:work@dut.DioPadBank + |vpiParamAssign: + \_param_assign: , line:13:64, endln:13:79 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:12:1, endln:18:16 + |vpiRhs: + \_constant: , line:13:77, endln:13:79 + |vpiDecompile:'0 + |vpiSize:2 + |BIN:0 + |vpiConstType:3 + |vpiLhs: + \_parameter: (work@dut.DioPadBank), line:13:64, endln:13:74 + |vpiTypedef: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiTypedef: + \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:3, endln:4:16 + |vpiTypedef: + \_import_typespec: (prim_pad_wrapper_pkg), line:13:10, endln:13:33 + |vpiDefName:work@dut + |vpiTop:1 + |vpiTopModule:1 + |vpiModule: + \_module_inst: work@prim_pad_wrapper (work@dut.u_dio_pad), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:15:3, endln:17:5 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:12:1, endln:18:16 + |vpiName:u_dio_pad + |vpiFullName:work@dut.u_dio_pad + |vpiTypedef: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiTypedef: + \_enum_typespec: (prim_pad_wrapper_pkg::pad_type_e), line:2:3, endln:4:16 + |vpiTypedef: + \_import_typespec: (prim_pad_wrapper_pkg), line:9:10, endln:9:33 + |vpiDefName:work@prim_pad_wrapper + |vpiDefFile:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv + |vpiDefLineNo:8 + |vpiNet: + \_logic_net: (work@dut.u_dio_pad.pok_i), line:9:52, endln:9:57 + |vpiParent: + \_module_inst: work@prim_pad_wrapper (work@dut.u_dio_pad), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:15:3, endln:17:5 + |vpiTypespec: + \_ref_typespec: (work@dut.u_dio_pad.pok_i) + |vpiParent: + \_logic_net: (work@dut.u_dio_pad.pok_i), line:9:52, endln:9:57 + |vpiFullName:work@dut.u_dio_pad.pok_i + |vpiActual: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiName:pok_i + |vpiFullName:work@dut.u_dio_pad.pok_i + |vpiNetType:36 + |vpiInstance: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:12:1, endln:18:16 + |vpiPort: + \_port: (pok_i), line:9:52, endln:9:57 + |vpiParent: + \_module_inst: work@prim_pad_wrapper (work@dut.u_dio_pad), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:15:3, endln:17:5 + |vpiName:pok_i + |vpiDirection:1 + |vpiHighConn: + \_bit_select: (work@dut.u_dio_pad.pad_pok), line:16:27, endln:16:40 + |vpiParent: + \_port: (pok_i), line:9:52, endln:9:57 + |vpiName:pad_pok + |vpiFullName:work@dut.u_dio_pad.pad_pok + |vpiActual: + \_packed_array_var: (work@dut.pad_pok), line:14:19, endln:14:26 + |vpiIndex: + \_constant: , line:13:77, endln:13:78 + |vpiParent: + \_bit_select: (work@dut.u_dio_pad.pad_pok), line:16:27, endln:16:40 + |vpiDecompile:1'b0 + |vpiSize:1 + |BIN:0 + |vpiConstType:3 + |vpiLowConn: + \_ref_obj: (work@dut.u_dio_pad.pok_i), line:16:6, endln:16:11 + |vpiParent: + \_port: (pok_i), line:9:52, endln:9:57 + |vpiName:pok_i + |vpiFullName:work@dut.u_dio_pad.pok_i + |vpiActual: + \_logic_net: (work@dut.u_dio_pad.pok_i), line:9:52, endln:9:57 + |vpiTypedef: + \_ref_typespec: (work@dut.u_dio_pad.pok_i) + |vpiParent: + \_port: (pok_i), line:9:52, endln:9:57 + |vpiFullName:work@dut.u_dio_pad.pok_i + |vpiActual: + \_logic_typespec: (pad_pok_t), line:5:11, endln:5:22 + |vpiInstance: + \_module_inst: work@prim_pad_wrapper (work@dut.u_dio_pad), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:15:3, endln:17:5 +\_weaklyReferenced: +\_logic_typespec: , line:2:16, endln:2:27 + |vpiInstance: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiRange: + \_range: , line:2:22, endln:2:27 + |vpiParent: + \_logic_typespec: , line:2:16, endln:2:27 + |vpiLeftRange: + \_constant: , line:2:23, endln:2:24 + |vpiParent: + \_range: , line:2:22, endln:2:27 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:2:25, endln:2:26 + |vpiParent: + \_range: , line:2:22, endln:2:27 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:2:16, endln:2:27 + |vpiInstance: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiRange: + \_range: , line:2:22, endln:2:27 + |vpiParent: + \_logic_typespec: , line:2:16, endln:2:27 + |vpiLeftRange: + \_constant: , line:2:23, endln:2:24 + |vpiParent: + \_range: , line:2:22, endln:2:27 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:2:25, endln:2:26 + |vpiParent: + \_range: , line:2:22, endln:2:27 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:13:47, endln:13:63 + |vpiParent: + \_parameter: (work@dut.DioPadBank), line:13:64, endln:13:74 + |vpiRange: + \_range: , line:13:53, endln:13:58 + |vpiParent: + \_logic_typespec: , line:13:47, endln:13:63 + |vpiLeftRange: + \_constant: , line:13:54, endln:13:55 + |vpiParent: + \_range: , line:13:53, endln:13:58 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:13:56, endln:13:57 + |vpiParent: + \_range: , line:13:53, endln:13:58 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiRange: + \_range: , line:13:58, endln:13:63 + |vpiParent: + \_logic_typespec: , line:13:47, endln:13:63 + |vpiLeftRange: + \_constant: , line:13:59, endln:13:60 + |vpiParent: + \_range: , line:13:58, endln:13:63 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:13:61, endln:13:62 + |vpiParent: + \_range: , line:13:58, endln:13:63 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: (pad_pok_t), line:5:11, endln:5:22 + |vpiName:pad_pok_t + |vpiInstance: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiRange: + \_range: , line:5:17, endln:5:22 + |vpiParent: + \_logic_typespec: (pad_pok_t), line:5:11, endln:5:22 + |vpiLeftRange: + \_constant: , line:5:18, endln:5:19 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:20, endln:5:21 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: (pad_pok_t), line:5:11, endln:5:22 + |vpiName:pad_pok_t + |vpiTypedefAlias: + \_ref_typespec: (pad_pok_t) + |vpiParent: + \_logic_typespec: (pad_pok_t), line:5:11, endln:5:22 + |vpiFullName:pad_pok_t + |vpiActual: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiInstance: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiRange: + \_range: , line:5:17, endln:5:22 + |vpiParent: + \_logic_typespec: (pad_pok_t), line:5:11, endln:5:22 + |vpiLeftRange: + \_constant: , line:5:18, endln:5:19 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:20, endln:5:21 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_bit_select: (work@dut.u_dio_pad.pad_pok), line:16:27, endln:16:40 + |vpiParent: + \_port: (pok_i), line:9:52, endln:9:57 + |vpiName:pad_pok + |vpiFullName:work@dut.u_dio_pad.pad_pok + |vpiIndex: + \_constant: , line:13:77, endln:13:78 +\_port: (pok_i), line:9:52, endln:9:57 + |vpiParent: + \_module_inst: work@prim_pad_wrapper (work@dut.u_dio_pad), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:15:3, endln:17:5 + |vpiName:pok_i + |vpiDirection:1 + |vpiHighConn: + \_bit_select: (work@dut.u_dio_pad.pad_pok), line:16:27, endln:16:40 + |vpiLowConn: + \_ref_obj: (work@dut.u_dio_pad.pok_i), line:16:6, endln:16:11 + |vpiParent: + \_port: (pok_i), line:9:52, endln:9:57 + |vpiName:pok_i + |vpiFullName:work@dut.u_dio_pad.pok_i + |vpiActual: + \_logic_net: (work@dut.u_dio_pad.pok_i), line:9:52, endln:9:57 + |vpiTypedef: + \_ref_typespec: (work@dut.u_dio_pad.pok_i) + |vpiParent: + \_port: (pok_i), line:9:52, endln:9:57 + |vpiFullName:work@dut.u_dio_pad.pok_i + |vpiActual: + \_logic_typespec: (pad_pok_t), line:5:11, endln:5:22 +\_logic_typespec: , line:14:3, endln:14:18 + |vpiElemTypespec: + \_ref_typespec: + |vpiParent: + \_logic_typespec: , line:14:3, endln:14:18 + |vpiActual: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiRange: + \_range: , line:14:13, endln:14:18 + |vpiParent: + \_logic_typespec: , line:14:3, endln:14:18 + |vpiLeftRange: + \_constant: , line:14:14, endln:14:15 + |vpiParent: + \_range: , line:14:13, endln:14:18 + |vpiDecompile:3 + |vpiSize:64 + |UINT:3 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:14:16, endln:14:17 + |vpiParent: + \_range: , line:14:13, endln:14:18 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiName:prim_pad_wrapper_pkg::pad_pok_t + |vpiTypedefAlias: + \_ref_typespec: (prim_pad_wrapper_pkg::pad_pok_t) + |vpiParent: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiFullName:prim_pad_wrapper_pkg::pad_pok_t + |vpiActual: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiInstance: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiRange: + \_range: , line:5:17, endln:5:22 + |vpiParent: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiLeftRange: + \_constant: , line:5:18, endln:5:19 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:20, endln:5:21 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiName:prim_pad_wrapper_pkg::pad_pok_t + |vpiTypedefAlias: + \_ref_typespec: (prim_pad_wrapper_pkg::pad_pok_t) + |vpiParent: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiFullName:prim_pad_wrapper_pkg::pad_pok_t + |vpiActual: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiInstance: + \_package: prim_pad_wrapper_pkg (prim_pad_wrapper_pkg::), file:${SURELOG_DIR}/tests/PackedArrayHighConn/dut.sv, line:1:1, endln:6:34 + |vpiRange: + \_range: , line:5:17, endln:5:22 + |vpiParent: + \_logic_typespec: (prim_pad_wrapper_pkg::pad_pok_t), line:5:11, endln:5:22 + |vpiLeftRange: + \_constant: , line:5:18, endln:5:19 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:20, endln:5:21 + |vpiParent: + \_range: , line:5:17, endln:5:22 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:13:47, endln:13:63 + |vpiParent: + \_ref_typespec: (work@dut.DioPadBank) + |vpiRange: + \_range: , line:13:53, endln:13:58 + |vpiParent: + \_logic_typespec: , line:13:47, endln:13:63 + |vpiLeftRange: + \_constant: , line:13:54, endln:13:55 + |vpiParent: + \_range: , line:13:53, endln:13:58 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:13:56, endln:13:57 + |vpiParent: + \_range: , line:13:53, endln:13:58 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiRange: + \_range: , line:13:58, endln:13:63 + |vpiParent: + \_logic_typespec: , line:13:47, endln:13:63 + |vpiLeftRange: + \_constant: , line:13:59, endln:13:60 + |vpiParent: + \_range: , line:13:58, endln:13:63 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:13:61, endln:13:62 + |vpiParent: + \_range: , line:13:58, endln:13:63 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +=================== +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 3 +[ NOTE] : 5 diff --git a/tests/PackedArrayHighConn/PackedArrayHighConn.sl b/tests/PackedArrayHighConn/PackedArrayHighConn.sl new file mode 100644 index 0000000000..b461620aca --- /dev/null +++ b/tests/PackedArrayHighConn/PackedArrayHighConn.sl @@ -0,0 +1 @@ +-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin diff --git a/tests/PackedArrayHighConn/dut.sv b/tests/PackedArrayHighConn/dut.sv new file mode 100644 index 0000000000..4424da244d --- /dev/null +++ b/tests/PackedArrayHighConn/dut.sv @@ -0,0 +1,63 @@ +package prim_pad_wrapper_pkg; + typedef enum logic [2:0] { + BidirStd = 3'h0 + } pad_type_e; + typedef logic [7:0] pad_pok_t; +endpackage : prim_pad_wrapper_pkg + +module prim_pad_wrapper + import prim_pad_wrapper_pkg::*; (input pad_pok_t pok_i); +endmodule : prim_pad_wrapper + +module dut + import prim_pad_wrapper_pkg::*; #(parameter logic [0:0][1:0] DioPadBank = '0) (); + pad_pok_t [3:0] pad_pok; + prim_pad_wrapper u_dio_pad ( + .pok_i ( pad_pok[DioPadBank[0]] ) + ); +endmodule : dut + + +/* +module dut ( + // input logic [3:0] a, + // input logic [3:0] b, + // output logic [1:0][3:0] out +); + + // typedef logic [3:0] logic4; + + logic [1:0] vector2x4; + + // logic4 [1:0] vector2x4; + // assign vector2x4[0] = a; + // assign vector2x4[1] = b; + + // assign out = vector2x4; + +endmodule +*/ + +/* +module top(output logic [9:0] o); + typedef struct packed { + logic [9:0] min_v; + } filter_ctl_t; + + filter_ctl_t [1:0] a = '{10'd15, 10'd0}; + assign o = a[1]; +endmodule +*/ + + +/* + +package pack_pkg; +typedef enum logic { fOO } foo; +endpackage + +module dut(input pack_pkg::foo [1:0] inp[2], output pack_pkg::foo [1:0] out[2]); +assign out = inp; +endmodule + +*/ \ No newline at end of file