diff --git a/design/el2_mem.sv b/design/el2_mem.sv index ba6b9c4072c..c2ca1cdcd3a 100644 --- a/design/el2_mem.sv +++ b/design/el2_mem.sv @@ -62,8 +62,8 @@ import el2_pkg::*; input logic ic_rd_en, input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic ic_sel_premux_data, // Premux data sel - input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, - input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, + // input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, + // input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC input logic [70:0] ic_debug_wr_data, // Debug wr cache. @@ -83,7 +83,8 @@ import el2_pkg::*; output logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit, output logic ic_tag_perr, // Icache Tag parity error - el2_mem_if.veer_sram_src mem_export, + el2_mem_if.veer_sram_src mem_export, + el2_mem_if.veer_icache_src icache_export, input logic scan_mode @@ -95,6 +96,7 @@ import el2_pkg::*; el2_mem_if mem_export_local (); assign mem_export .clk = clk; + assign icache_export .clk = clk; assign mem_export_local.clk = clk; assign mem_export .iccm_clken = mem_export_local.iccm_clken; @@ -114,13 +116,19 @@ import el2_pkg::*; assign mem_export_local.dccm_bank_ecc = mem_export .dccm_bank_ecc; // icache data - assign mem_export .icache_bank_way_clken = mem_export_local.icache_bank_way_clken; - assign mem_export .icache_b_sb_wren = mem_export_local.icache_b_sb_wren; - assign mem_export_local.icache_wb_dout = mem_export.icache_wb_dout; + assign icache_export .icache_bank_way_clken = mem_export_local.icache_bank_way_clken; + assign icache_export .icache_b_sb_wren = mem_export_local.icache_b_sb_wren; + assign icache_export .icache_sb_wr_data = mem_export_local.icache_sb_wr_data; + assign icache_export .icache_bank_wr_data = mem_export_local.icache_bank_wr_data; + assign icache_export .icache_rw_addr_bank_q = mem_export_local.icache_rw_addr_bank_q; + assign mem_export_local.icache_wb_dout = icache_export.icache_wb_dout; + assign mem_export_local.icache_wb_dout_ecc_bank = icache_export.icache_wb_dout_ecc_bank; // icache tag - assign mem_export .icache_tag_clken = mem_export_local.icache_tag_clken; - assign mem_export .icache_tag_data_raw = mem_export_local.icache_tag_data_raw; - + assign icache_export .icache_tag_clken = mem_export_local.icache_tag_clken; + assign icache_export .icache_tag_data_raw = mem_export_local.icache_tag_data_raw; + assign icache_export .icache_tag_wren_q = mem_export_local.icache_tag_wren_q; + assign icache_export .icache_tag_wr_data = mem_export_local.icache_tag_wr_data; + assign icache_export .icache_tag_rw_addr_q = mem_export_local.icache_tag_rw_addr_q; assign mem_export_local.clk = clk; // TODO assign all signals from modport veer_icache_src (lib/el2_mem_if.sv) @@ -140,7 +148,7 @@ import el2_pkg::*; if ( pt.ICACHE_ENABLE ) begin: icache el2_ifu_ic_mem #(.pt(pt)) icm ( .clk_override(icm_clk_override), - .icache_export(mem_export_local.veer_icache) + .icache_export(mem_export_local.veer_icache), .* ); end diff --git a/design/el2_veer_wrapper.sv b/design/el2_veer_wrapper.sv index 1199f03d286..81d99a4c1d4 100644 --- a/design/el2_veer_wrapper.sv +++ b/design/el2_veer_wrapper.sv @@ -393,9 +393,8 @@ import el2_pkg::*; // input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, // ICache export interfaces - el2_mem_if.veer_icache el2_icache_export, + el2_mem_if.veer_icache_src el2_icache_export, - input logic timer_int, input logic soft_int, input logic [pt.PIC_TOTAL_INT:1] extintsrc_req, diff --git a/design/ifu/el2_ifu_ic_mem.sv b/design/ifu/el2_ifu_ic_mem.sv index b741ece5034..c56463ff73e 100644 --- a/design/ifu/el2_ifu_ic_mem.sv +++ b/design/ifu/el2_ifu_ic_mem.sv @@ -200,7 +200,11 @@ import el2_pkg::*; // Expose the ICACHE DATA signals outside of the core. always_comb begin icache_export.icache_bank_way_clken = ic_bank_way_clken; - icache_export.icache_b_sb_ren = ic_b_sb_ren; + icache_export.icache_b_sb_wren = ic_b_sb_wren; + icache_export.icache_sb_wr_data = ic_sb_wr_data; + icache_export.icache_bank_wr_data = ic_bank_wr_data; + icache_export.icache_rw_addr_bank_q = ic_rw_addr_bank_q; + wb_dout_ecc_bank = icache_export.icache_wb_dout_ecc_bank; wb_dout = icache_export.icache_wb_dout; end @@ -273,17 +277,17 @@ import el2_pkg::*; .Q (wb_dout_pre_up[i][k]), \ .CLK (clk), \ .ROP ( ), \ - .TEST1(ic_data_ext_in_pkt[i][k].TEST1), \ - .RME(ic_data_ext_in_pkt[i][k].RME), \ - .RM(ic_data_ext_in_pkt[i][k].RM), \ + .TEST1(), \ + .RME(), \ + .RM(), \ \ - .LS(ic_data_ext_in_pkt[i][k].LS), \ - .DS(ic_data_ext_in_pkt[i][k].DS), \ - .SD(ic_data_ext_in_pkt[i][k].SD), \ + .LS(), \ + .DS(), \ + .SD(), \ \ - .TEST_RNM(ic_data_ext_in_pkt[i][k].TEST_RNM), \ - .BC1(ic_data_ext_in_pkt[i][k].BC1), \ - .BC2(ic_data_ext_in_pkt[i][k].BC2) \ + .TEST_RNM(), \ + .BC1(), \ + .BC2() \ ); \ if (pt.ICACHE_BYPASS_ENABLE == 1) begin \ assign wrptr_in_up[i][k] = (wrptr_up[i][k] == (pt.ICACHE_NUM_BYPASS-1)) ? '0 : (wrptr_up[i][k] + 1'd1); \ @@ -425,17 +429,17 @@ if (pt.ICACHE_BYPASS_ENABLE == 1) begin \ .Q (wb_packeddout_pre[k]), \ .ME (|ic_bank_way_clken_final[k]), \ .ROP ( ), \ - .TEST1 (ic_data_ext_in_pkt[0][k].TEST1), \ - .RME (ic_data_ext_in_pkt[0][k].RME), \ - .RM (ic_data_ext_in_pkt[0][k].RM), \ + .TEST1 (), \ + .RME (), \ + .RM (), \ \ - .LS (ic_data_ext_in_pkt[0][k].LS), \ - .DS (ic_data_ext_in_pkt[0][k].DS), \ - .SD (ic_data_ext_in_pkt[0][k].SD), \ + .LS (), \ + .DS (), \ + .SD (), \ \ - .TEST_RNM (ic_data_ext_in_pkt[0][k].TEST_RNM), \ - .BC1 (ic_data_ext_in_pkt[0][k].BC1), \ - .BC2 (ic_data_ext_in_pkt[0][k].BC2) \ + .TEST_RNM (), \ + .BC1 (), \ + .BC2 () \ ); \ \ if (pt.ICACHE_BYPASS_ENABLE == 1) begin \ @@ -867,12 +871,13 @@ import el2_pkg::*; logic ic_rd_en_ff; logic ic_tag_parity; - - // TODO Do we need to move this to a GENVAR block and iterate over banks, assign them with indexing? // Expose the ICACHE TAG signals outside of the core. always_comb begin - icache_export.icache_tag_clken = ic_tag_clken; - icache_export.icache_tag_data_raw = ic_tag_data_raw; + icache_export.icache_tag_clken = ic_tag_clken; + icache_export.icache_tag_data_raw = ic_tag_data_raw; + icache_export.icache_tag_wren_q = ic_tag_wren_q; + icache_export.icache_tag_wr_data = ic_tag_wr_data; + icache_export.icache_tag_rw_addr_q = ic_rw_addr_q; end assign ic_tag_wren [pt.ICACHE_NUM_WAYS-1:0] = ic_wr_en[pt.ICACHE_NUM_WAYS-1:0] & {pt.ICACHE_NUM_WAYS{(ic_rw_addr[pt.ICACHE_BEAT_ADDR_HI:4] == {pt.ICACHE_BEAT_BITS-1{1'b1}})}} ; @@ -991,17 +996,17 @@ end // block: OTHERS .CLK (clk), \ .ROP ( ), \ \ - .TEST1(ic_tag_ext_in_pkt[i].TEST1), \ - .RME(ic_tag_ext_in_pkt[i].RME), \ - .RM(ic_tag_ext_in_pkt[i].RM), \ + .TEST1(), \ + .RME(), \ + .RM(), \ \ - .LS(ic_tag_ext_in_pkt[i].LS), \ - .DS(ic_tag_ext_in_pkt[i].DS), \ - .SD(ic_tag_ext_in_pkt[i].SD), \ + .LS(), \ + .DS(), \ + .SD(), \ \ - .TEST_RNM(ic_tag_ext_in_pkt[i].TEST_RNM), \ - .BC1(ic_tag_ext_in_pkt[i].BC1), \ - .BC2(ic_tag_ext_in_pkt[i].BC2) \ + .TEST_RNM(), \ + .BC1(), \ + .BC2() \ \ ); \ \ @@ -1195,17 +1200,17 @@ end // block: OTHERS .CLK (clk), \ .ROP ( ), \ \ - .TEST1 (ic_tag_ext_in_pkt[0].TEST1), \ - .RME (ic_tag_ext_in_pkt[0].RME), \ - .RM (ic_tag_ext_in_pkt[0].RM), \ + .TEST1 (), \ + .RME (), \ + .RM (), \ \ - .LS (ic_tag_ext_in_pkt[0].LS), \ - .DS (ic_tag_ext_in_pkt[0].DS), \ - .SD (ic_tag_ext_in_pkt[0].SD), \ + .LS (), \ + .DS (), \ + .SD (), \ \ - .TEST_RNM (ic_tag_ext_in_pkt[0].TEST_RNM), \ - .BC1 (ic_tag_ext_in_pkt[0].BC1), \ - .BC2 (ic_tag_ext_in_pkt[0].BC2) \ + .TEST_RNM (), \ + .BC1 (), \ + .BC2 () \ \ ); \ \ diff --git a/design/lib/el2_mem_if.sv b/design/lib/el2_mem_if.sv index 35c4a2b7e13..cb6b64d1672 100644 --- a/design/lib/el2_mem_if.sv +++ b/design/lib/el2_mem_if.sv @@ -52,15 +52,21 @@ interface el2_mem_if #( ////////////////////////////////////////// // ICACHE DATA - logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_bank_way_clken; // (ic_bank_way_clken) - logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_b_sb_wren; //bank x ways (ic_b_sb_wren) - logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] icache_rw_addr_bank_q; // (ic_rw_addr_bank_q) - logic [pt.ICACHE_BANKS_WAY-1:0][70:0] icache_bank_wr_data; // (ic_bank_wr_data) - logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0] icache_wb_dout; // ways x bank (wb_dout) + logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_b_sb_wren; + logic [pt.ICACHE_BANKS_WAY-1:0][70:0] icache_sb_wr_data; + logic [pt.ICACHE_BANKS_WAY-1:0][70:0] icache_bank_wr_data; + logic [pt.ICACHE_BANKS_WAY-1:0][70:0] icache_wb_dout_ecc_bank; + logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_bank_way_clken; + logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] icache_rw_addr_bank_q; + logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0] icache_wb_dout; + ////////////////////////////////////////// // ICACHE TAG logic [pt.ICACHE_NUM_WAYS-1:0] icache_tag_clken; // (ic_tag_clken) + logic [pt.ICACHE_NUM_WAYS-1:0] icache_tag_wren_q; + logic [25:0] icache_tag_wr_data ; + logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO] icache_tag_rw_addr_q; logic [pt.ICACHE_NUM_WAYS-1:0] [25:0] icache_tag_data_raw; // (ic_tag_data_raw) ////////////////////////////////////////// @@ -100,13 +106,21 @@ interface el2_mem_if #( ); modport veer_icache( - input clk; - // TODO decide which signals exactly to export + input clk, + // data + output icache_bank_way_clken, icache_b_sb_wren, icache_sb_wr_data, icache_bank_wr_data, icache_rw_addr_bank_q, + input icache_wb_dout_ecc_bank, icache_wb_dout, + // tag + output icache_tag_clken, icache_tag_data_raw, icache_tag_wren_q, icache_tag_wr_data, icache_tag_rw_addr_q + ); + + modport veer_icache_src( + output clk, // data - output icache_bank_way_clken, icache_b_sb_wren; - input icache_wb_dout; + output icache_bank_way_clken, icache_b_sb_wren, icache_sb_wr_data, icache_bank_wr_data, icache_rw_addr_bank_q, + input icache_wb_dout_ecc_bank, icache_wb_dout, // tag - output icache_tag_clken, icache_tag_data_raw; + output icache_tag_clken, icache_tag_data_raw, icache_tag_wren_q, icache_tag_wr_data, icache_tag_rw_addr_q ); endinterface diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 594bedc77fe..14b78f0eee0 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -1292,6 +1292,19 @@ veer_wrapper rvtop_wrapper ( .dccm_bank_dout (el2_mem_export.dccm_bank_dout), .dccm_bank_ecc (el2_mem_export.dccm_bank_ecc), + .icache_bank_way_clken (el2_mem_export.icache_bank_way_clken), + .icache_b_sb_wren (el2_mem_export.icache_b_sb_wren), + .icache_sb_wr_data (el2_mem_export.icache_sb_wr_data), + .icache_bank_wr_data (el2_mem_export.icache_bank_wr_data), + .icache_rw_addr_bank_q (el2_mem_export.icache_rw_addr_bank_q), + .icache_wb_dout_ecc_bank (el2_mem_export.icache_wb_dout_ecc_bank), + .icache_wb_dout (el2_mem_export.icache_wb_dout), + .icache_tag_clken (el2_mem_export.icache_tag_clken), + .icache_tag_data_raw (el2_mem_export.icache_tag_data_raw), + .icache_tag_wren_q (el2_mem_export.icache_tag_wren_q), + .icache_tag_wr_data (el2_mem_export.icache_tag_wr_data), + .icache_tag_rw_addr_q (el2_mem_export.icache_tag_rw_addr_q), + .iccm_ecc_single_error (), .iccm_ecc_double_error (), .dccm_ecc_single_error (), diff --git a/testbench/veer_wrapper.sv b/testbench/veer_wrapper.sv index 706b5967a38..4b7ea1eb87a 100644 --- a/testbench/veer_wrapper.sv +++ b/testbench/veer_wrapper.sv @@ -329,14 +329,20 @@ module veer_wrapper // ICache Export Interface // ICache Data - output logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_bank_way_clken; - output logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_b_sb_wren; - input logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0] icache_wb_dout; + output logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_b_sb_wren, + output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] icache_sb_wr_data, + output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] icache_bank_wr_data, + output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] icache_wb_dout_ecc_bank, + output logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_bank_way_clken, + input logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] icache_rw_addr_bank_q, + input logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0] icache_wb_dout, // ICache Tag - output logic [pt.ICACHE_NUM_WAYS-1:0] icache_tag_clken; - output logic [pt.ICACHE_NUM_WAYS-1:0] [25:0] icache_tag_data_raw; - + output logic [pt.ICACHE_NUM_WAYS-1:0] icache_tag_clken, + output logic [pt.ICACHE_NUM_WAYS-1:0] icache_tag_wren_q, + output logic [25:0] icache_tag_wr_data, + output logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO] icache_tag_rw_addr_q, + output logic [pt.ICACHE_NUM_WAYS-1:0] [25:0] icache_tag_data_raw, // ICCM/DCCM ECC status output logic iccm_ecc_single_error, @@ -398,7 +404,7 @@ module veer_wrapper el2_veer_wrapper rvtop ( .el2_mem_export(mem_export.veer_sram_src), - .el2_icache_export(mem_export.veer_icache) + .el2_icache_export(mem_export.veer_icache), .dmi_core_enable(dmi_core_enable), .dmi_active(dmi_active), .*