From 79765ce8d8b03f963719ef18212d756d6b7b0761 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Tue, 12 Nov 2024 17:28:34 +0100 Subject: [PATCH] export icache signals --- design/el2_mem.sv | 10 +++++++++- design/el2_veer_wrapper.sv | 2 +- design/ifu/el2_ifu_ic_mem.sv | 24 ++++++++++++++++++++++-- design/lib/el2_mem_if.sv | 23 +++++++++++++++++++---- testbench/veer_wrapper.sv | 18 ++++++++++++++++++ 5 files changed, 69 insertions(+), 8 deletions(-) diff --git a/design/el2_mem.sv b/design/el2_mem.sv index e6b65c0a549..ba6b9c4072c 100644 --- a/design/el2_mem.sv +++ b/design/el2_mem.sv @@ -84,7 +84,6 @@ import el2_pkg::*; output logic ic_tag_perr, // Icache Tag parity error el2_mem_if.veer_sram_src mem_export, - el2_mem_if.veer_icache_src icache_export, input logic scan_mode @@ -114,6 +113,15 @@ import el2_pkg::*; assign mem_export_local.dccm_bank_dout = mem_export .dccm_bank_dout; assign mem_export_local.dccm_bank_ecc = mem_export .dccm_bank_ecc; + // icache data + assign mem_export .icache_bank_way_clken = mem_export_local.icache_bank_way_clken; + assign mem_export .icache_b_sb_wren = mem_export_local.icache_b_sb_wren; + assign mem_export_local.icache_wb_dout = mem_export.icache_wb_dout; + // icache tag + assign mem_export .icache_tag_clken = mem_export_local.icache_tag_clken; + assign mem_export .icache_tag_data_raw = mem_export_local.icache_tag_data_raw; + + assign mem_export_local.clk = clk; // TODO assign all signals from modport veer_icache_src (lib/el2_mem_if.sv) diff --git a/design/el2_veer_wrapper.sv b/design/el2_veer_wrapper.sv index e94f93cbb03..1199f03d286 100644 --- a/design/el2_veer_wrapper.sv +++ b/design/el2_veer_wrapper.sv @@ -393,7 +393,7 @@ import el2_pkg::*; // input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, // ICache export interfaces - el2_mem_if.veer_icache_src el2_icache_export, + el2_mem_if.veer_icache el2_icache_export, input logic timer_int, diff --git a/design/ifu/el2_ifu_ic_mem.sv b/design/ifu/el2_ifu_ic_mem.sv index 6f80aa00740..b741ece5034 100644 --- a/design/ifu/el2_ifu_ic_mem.sv +++ b/design/ifu/el2_ifu_ic_mem.sv @@ -66,6 +66,7 @@ import el2_pkg::*; EL2_IC_TAG #(.pt(pt)) ic_tag_inst ( .*, + .icache_export(icache_export), .ic_wr_en (ic_wr_en[pt.ICACHE_NUM_WAYS-1:0]), .ic_debug_addr(ic_debug_addr[pt.ICACHE_INDEX_HI:3]), .ic_rw_addr (ic_rw_addr[31:3]) @@ -74,6 +75,7 @@ import el2_pkg::*; EL2_IC_DATA #(.pt(pt)) ic_data_inst ( .*, + .icache_export(icache_export), .ic_wr_en (ic_wr_en[pt.ICACHE_NUM_WAYS-1:0]), .ic_debug_addr(ic_debug_addr[pt.ICACHE_INDEX_HI:3]), .ic_rw_addr (ic_rw_addr[31:1]) @@ -115,7 +117,8 @@ import el2_pkg::*; input logic ic_sel_premux_data, // Select the pre_muxed data input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit, - input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc + // input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc + el2_mem_if.veer_icache icache_export, input logic scan_mode ) ; @@ -192,6 +195,15 @@ import el2_pkg::*; //----------------------------------------------------------- // ----------- Logic section starts here -------------------- //----------------------------------------------------------- + + // TODO do we need to move this to a GENVAR block and iterate over banks, assign them with indexing? + // Expose the ICACHE DATA signals outside of the core. + always_comb begin + icache_export.icache_bank_way_clken = ic_bank_way_clken; + icache_export.icache_b_sb_ren = ic_b_sb_ren; + wb_dout = icache_export.icache_wb_dout; + end + assign ic_debug_rd_way_en[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{ic_debug_rd_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ; assign ic_debug_wr_way_en[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{ic_debug_wr_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ; @@ -820,7 +832,8 @@ import el2_pkg::*; input logic ic_debug_wr_en, // Icache debug wr input logic ic_debug_tag_array, // Debug tag array input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. - input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, + // input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, + el2_mem_if.veer_icache icache_export, output logic [25:0] ictag_debug_rd_data, input logic [70:0] ic_debug_wr_data, // Debug wr cache. @@ -855,6 +868,13 @@ import el2_pkg::*; logic ic_tag_parity; + // TODO Do we need to move this to a GENVAR block and iterate over banks, assign them with indexing? + // Expose the ICACHE TAG signals outside of the core. + always_comb begin + icache_export.icache_tag_clken = ic_tag_clken; + icache_export.icache_tag_data_raw = ic_tag_data_raw; + end + assign ic_tag_wren [pt.ICACHE_NUM_WAYS-1:0] = ic_wr_en[pt.ICACHE_NUM_WAYS-1:0] & {pt.ICACHE_NUM_WAYS{(ic_rw_addr[pt.ICACHE_BEAT_ADDR_HI:4] == {pt.ICACHE_BEAT_BITS-1{1'b1}})}} ; assign ic_tag_clken[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{ic_rd_en | clk_override}} | ic_wr_en[pt.ICACHE_NUM_WAYS-1:0] | ic_debug_wr_way_en[pt.ICACHE_NUM_WAYS-1:0] | ic_debug_rd_way_en[pt.ICACHE_NUM_WAYS-1:0]; diff --git a/design/lib/el2_mem_if.sv b/design/lib/el2_mem_if.sv index 45910660c0d..35c4a2b7e13 100644 --- a/design/lib/el2_mem_if.sv +++ b/design/lib/el2_mem_if.sv @@ -50,6 +50,18 @@ interface el2_mem_if #( logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout; logic [pt.DCCM_NUM_BANKS-1:0][ DCCM_ECC_WIDTH-1:0] dccm_bank_ecc; + ////////////////////////////////////////// + // ICACHE DATA + logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_bank_way_clken; // (ic_bank_way_clken) + logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_b_sb_wren; //bank x ways (ic_b_sb_wren) + logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] icache_rw_addr_bank_q; // (ic_rw_addr_bank_q) + logic [pt.ICACHE_BANKS_WAY-1:0][70:0] icache_bank_wr_data; // (ic_bank_wr_data) + logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0] icache_wb_dout; // ways x bank (wb_dout) + + ////////////////////////////////////////// + // ICACHE TAG + logic [pt.ICACHE_NUM_WAYS-1:0] icache_tag_clken; // (ic_tag_clken) + logic [pt.ICACHE_NUM_WAYS-1:0] [25:0] icache_tag_data_raw; // (ic_tag_data_raw) ////////////////////////////////////////// // MODPORTS @@ -88,10 +100,13 @@ interface el2_mem_if #( ); modport veer_icache( - input clk; - ); - modport veer_icache_src( - input clk; + input clk; + // TODO decide which signals exactly to export + // data + output icache_bank_way_clken, icache_b_sb_wren; + input icache_wb_dout; + // tag + output icache_tag_clken, icache_tag_data_raw; ); endinterface diff --git a/testbench/veer_wrapper.sv b/testbench/veer_wrapper.sv index 2a3dcfa7ba8..706b5967a38 100644 --- a/testbench/veer_wrapper.sv +++ b/testbench/veer_wrapper.sv @@ -327,6 +327,17 @@ module veer_wrapper input logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout, input logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-pt.DCCM_DATA_WIDTH-1:0] dccm_bank_ecc, + // ICache Export Interface + // ICache Data + output logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_bank_way_clken; + output logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] icache_b_sb_wren; + input logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0] icache_wb_dout; + + // ICache Tag + output logic [pt.ICACHE_NUM_WAYS-1:0] icache_tag_clken; + output logic [pt.ICACHE_NUM_WAYS-1:0] [25:0] icache_tag_data_raw; + + // ICCM/DCCM ECC status output logic iccm_ecc_single_error, output logic iccm_ecc_double_error, @@ -378,9 +389,16 @@ module veer_wrapper assign iccm_bank_wr_ecc = mem_export.iccm_bank_wr_ecc; assign mem_export.iccm_bank_dout = iccm_bank_dout; assign mem_export.iccm_bank_ecc = iccm_bank_ecc; + // ICache Data + assign icache_bank_way_clken = mem_export.icache_bank_way_clken; + assign icache_b_sb_wren = mem_export.icache_b_sb_wren; + assign mem_export.icache_wb_dout = icache_wb_dout; + // ICache Tag + assign icache_tag_clken = mem_export.icache_tag_clken; el2_veer_wrapper rvtop ( .el2_mem_export(mem_export.veer_sram_src), + .el2_icache_export(mem_export.veer_icache) .dmi_core_enable(dmi_core_enable), .dmi_active(dmi_active), .*