From e6e2ec6363e36d047ebf5a129fe3b10d74c10418 Mon Sep 17 00:00:00 2001 From: Tomasz Michalak Date: Fri, 11 Oct 2024 08:13:50 +0200 Subject: [PATCH 01/11] docs: Pin Sphinx to 8.0.2 --- docs/requirements.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/requirements.txt b/docs/requirements.txt index a0532a9296e..d02c5cf6b0f 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1 +1,2 @@ +Sphinx==8.0.2 https://github.com/antmicro/antmicro-sphinx-utils/archive/main.zip From b3728443b0b4f5b1825f3fb75dd53d57244df2c4 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Wed, 9 Oct 2024 19:59:58 +0200 Subject: [PATCH 02/11] update ci to use docker image --- .github/workflows/build-verilator.yml | 77 ------------------- .github/workflows/ci.yml | 24 ------ .github/workflows/get-renode.yml | 57 -------------- .github/workflows/test-openocd.yml | 32 +------- .github/workflows/test-regression.yml | 21 ++---- .github/workflows/test-renode.yml | 25 +------ .github/workflows/test-riscof.yml | 39 +++------- .github/workflows/test-riscv-dv.yml | 98 +++---------------------- .github/workflows/test-uarch.yml | 38 ++++------ .github/workflows/test-uvm.yml | 19 +---- .github/workflows/test-verification.yml | 39 ++++------ 11 files changed, 63 insertions(+), 406 deletions(-) delete mode 100644 .github/workflows/build-verilator.yml delete mode 100644 .github/workflows/get-renode.yml diff --git a/.github/workflows/build-verilator.yml b/.github/workflows/build-verilator.yml deleted file mode 100644 index daa2432dff0..00000000000 --- a/.github/workflows/build-verilator.yml +++ /dev/null @@ -1,77 +0,0 @@ -name: Verilator Build - -on: - workflow_call: - -jobs: - verilator: - name: Build Verilator - runs-on: ubuntu-latest - strategy: - matrix: - include: - - version: v5.024 - repo: verilator/verilator - commit: v5.024 - - version: uvm - repo: verilator/verilator - commit: 7ca2d6470a - env: - TOOL_NAME: verilator - TOOL_VERSION: ${{ matrix.version }} - TOOL_REPO: ${{ matrix.repo }} - TOOL_COMMIT: ${{ matrix.commit }} - DEBIAN_FRONTEND: "noninteractive" - - steps: - - name: Setup Cache Metadata - id: cache_metadata - run: | - cache_date=$(date +"%Y_%m_%d") - cache_name=cache_${{ env.TOOL_NAME }}_${{ env.TOOL_VERSION }}_${{ env.TOOL_COMMIT }} - echo "Cache date: "$cache_date - echo "Cache name: "$cache_name - echo "cache_date=$cache_date" >> "$GITHUB_ENV" - echo "cache_name=$cache_name" >> "$GITHUB_ENV" - - - name: Setup cache - uses: actions/cache@v3 - id: cache - timeout-minutes: 60 - with: - path: | - /opt/verilator - /opt/verilator/.cache - key: ${{ env.cache_name }}_${{ env.cache_date }} - restore-keys: ${{ env.cache_name }}_ - - - name: Install prerequisities - if: ${{ steps.cache.outputs.cache-hit != 'true' }} - run: | - sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ - autoconf automake autotools-dev \ - bc bison build-essential \ - ccache curl \ - flex \ - gawk git gperf \ - help2man \ - libexpat-dev libfl-dev libfl2 libgmp-dev \ - libmpc-dev libmpfr-dev libtool \ - ninja-build \ - patchutils python3 python3-pip \ - texinfo \ - zlib1g zlib1g-dev - - - name: Build Verilator - if: ${{ steps.cache.outputs.cache-hit != 'true' }} - run: | - export CCACHE_DIR=/opt/verilator/.cache - ccache --show-config | grep cache_dir - git clone https://github.com/${{ env.TOOL_REPO }} verilator - pushd verilator - git checkout ${{ env.TOOL_COMMIT }} - autoconf - ./configure --prefix=/opt/verilator - make -j `nproc` - make install - popd diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 4d44639cdc3..0b05b76b673 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -8,60 +8,36 @@ on: jobs: - Build-Verilator: - name: Build-Verilator - uses: ./.github/workflows/build-verilator.yml - - Build-Spike: - name: Build-Spike - uses: ./.github/workflows/build-spike.yml - - Get-Renode: - name: Get-Renode - uses: ./.github/workflows/get-renode.yml - - Build-OpenOCD: - name: Build-OpenOCD - uses: ./.github/workflows/build-openocd.yml - Test-Regression: name: Test-Regression - needs: [Build-Verilator] uses: ./.github/workflows/test-regression.yml Test-Verification: name: Test-Verification - needs: [Build-Verilator] uses: ./.github/workflows/test-verification.yml Test-Microarchitectural: name: Test-Microarchitectural - needs: [Build-Verilator] uses: ./.github/workflows/test-uarch.yml Test-RISCV-DV: name: Test-RISCV-DV - needs: [Build-Verilator, Build-Spike, Get-Renode] uses: ./.github/workflows/test-riscv-dv.yml Test-RISCOF: name: Test-RISCOF - needs: [Build-Verilator, Build-Spike] uses: ./.github/workflows/test-riscof.yml Test-UVM: name: Test-UVM - needs: [Build-Verilator] uses: ./.github/workflows/test-uvm.yml Test-Renode: name: Test-Renode - needs: [Get-Renode] uses: ./.github/workflows/test-renode.yml Test-OpenOCD: name: Test-OpenOCD - needs: [Build-Verilator, Build-OpenOCD] uses: ./.github/workflows/test-openocd.yml Report-Coverage: diff --git a/.github/workflows/get-renode.yml b/.github/workflows/get-renode.yml deleted file mode 100644 index 57c7beeaf41..00000000000 --- a/.github/workflows/get-renode.yml +++ /dev/null @@ -1,57 +0,0 @@ -name: Get Renode - -on: - workflow_call: - -jobs: - -#--------------# -# Renode -#--------------# - renode: - name: Get Renode - runs-on: ubuntu-latest - env: - TOOL_NAME: renode - TOOL_VERSION: 1.15.3+20240924gitc7bc336bb - DEBIAN_FRONTEND: "noninteractive" - - steps: - - name: Setup Cache Metadata - id: cache_metadata - run: | - cache_date=$(date +"%Y_%m_%d") - cache_name=cache_${{ env.TOOL_NAME }}_${{ env.TOOL_VERSION }} - echo "Cache date: "$cache_date - echo "Cache name: "$cache_name - echo "cache_date=$cache_date" >> "$GITHUB_ENV" - echo "cache_name=$cache_name" >> "$GITHUB_ENV" - - - name: Setup cache - uses: actions/cache@v3 - id: cache - timeout-minutes: 60 - with: - path: | - /opt/renode - key: ${{ env.cache_name }}_${{ env.cache_date }} - restore-keys: ${{ env.cache_name }}_ - - - name: Get Renode - if: ${{ steps.cache.outputs.cache-hit != 'true' }} - run: | - wget https://builds.renode.io/renode-${{ env.TOOL_VERSION}}.linux-portable.tar.gz - - - name: Rename the archive - if: ${{ steps.cache.outputs.cache-hit != 'true' }} - run: | - mv ${{ github.workspace }}/renode-*.tar.gz ${{ github.workspace }}/renode.tar.gz - - - name: Unpack binaries - if: ${{ steps.cache.outputs.cache-hit != 'true' }} - run: | - pushd /opt - mv ${{ github.workspace }}/renode.tar.gz . - mkdir -p renode - tar -zxvf renode.tar.gz --strip-components=1 -C renode/ - popd diff --git a/.github/workflows/test-openocd.yml b/.github/workflows/test-openocd.yml index b86675aefa8..fa64af13ae8 100644 --- a/.github/workflows/test-openocd.yml +++ b/.github/workflows/test-openocd.yml @@ -8,6 +8,7 @@ jobs: tests: name: Run OpenOCD tests runs-on: ubuntu-latest + container: ghcr.io/antmicro/cores-veer-el2:latest strategy: fail-fast: false matrix: @@ -16,7 +17,6 @@ jobs: env: DEBIAN_FRONTEND: "noninteractive" CCACHE_DIR: "/opt/openocd-tests/.cache/" - VERILATOR_VERSION: v5.024 steps: - name: Install utils @@ -31,46 +31,20 @@ jobs: run: | date=$(date +"%Y_%m_%d") time=$(date +"%Y%m%d_%H%M%S_%N") - cache_verilator_restore_key=cache_verilator_ - cache_verilator_key=${cache_verilator_restore_key}${{ env.VERILATOR_VERSION }}_${{ env.VERILATOR_COMMIT }} - cache_openocd_restore_key=cache_openocd_ - cache_openocd_key=${cache_openocd_restore_key} cache_test_restore_key=${{ matrix.coverage }}_ cache_test_key=${cache_test_restore_key}${time} echo "date=$date" | tee -a "$GITHUB_ENV" echo "time=$time" | tee -a "$GITHUB_ENV" - echo "cache_verilator_restore_key=$cache_verilator_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_verilator_key=$cache_verilator_key" | tee -a "$GITHUB_ENV" - echo "cache_openocd_restore_key=$cache_openocd_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_openocd_key=$cache_openocd_key" | tee -a "$GITHUB_ENV" echo "cache_test_restore_key=$cache_test_restore_key" | tee -a "$GITHUB_ENV" echo "cache_test_key=$cache_test_key" | tee -a "$GITHUB_ENV" - - name: Restore Verilator cache - id: cache-verilator-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/verilator - /opt/verilator/.cache - key: ${{ env.cache_verilator_key }} - - - name: Restore OpenOCD cache - id: cache-openocd-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/openocd - /opt/openocd/.cache - key: ${{ env.cache_openocd_key }} - restore-keys: ${{ env.cache_openocd_restore_key }} - - name: Setup repository uses: actions/checkout@v3 with: submodules: recursive - name: install SiteSpawner package + shell: bash run: | python3 -m venv .venv .venv/bin/python3 -m pip install tools/SiteSpawner @@ -79,6 +53,7 @@ jobs: python3 -m pip install tools/SiteSpawner - name: Build verilated simulation + shell: bash run: | export PATH=/opt/verilator/bin:/opt/openocd/bin:$PATH export RV_ROOT=$(pwd) @@ -91,6 +66,7 @@ jobs: -f ${RV_ROOT}/testbench/openocd_scripts/jtag_cg.tcl - name: Prepare coverage data + shell: bash run: | export PATH=/opt/verilator/bin:$PATH export RV_ROOT=$(pwd) diff --git a/.github/workflows/test-regression.yml b/.github/workflows/test-regression.yml index 905331d13b9..0264c2d0bd5 100644 --- a/.github/workflows/test-regression.yml +++ b/.github/workflows/test-regression.yml @@ -8,6 +8,7 @@ jobs: regression-tests: name: Regression tests runs-on: ubuntu-latest + container: ghcr.io/antmicro/cores-veer-el2:latest strategy: matrix: bus: ["axi", "ahb"] @@ -21,7 +22,6 @@ jobs: env: DEBIAN_FRONTEND: "noninteractive" CCACHE_DIR: "/opt/regression/.cache/" - VERILATOR_VERSION: v5.024 steps: - name: Install utils @@ -37,28 +37,14 @@ jobs: run: | date=$(date +"%Y_%m_%d") time=$(date +"%Y%m%d_%H%M%S_%N") - cache_verilator_restore_key=cache_verilator_ - cache_verilator_key=${cache_verilator_restore_key}${{ env.VERILATOR_VERSION }}_${{ env.VERILATOR_COMMIT }} cache_test_restore_key=${{ matrix.test }}_${{ matrix.coverage }}_ cache_test_key=${cache_test_restore_key}${time} echo "date=$date" | tee -a "$GITHUB_ENV" echo "time=$time" | tee -a "$GITHUB_ENV" - echo "cache_verilator_restore_key=$cache_verilator_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_verilator_key=$cache_verilator_key" | tee -a "$GITHUB_ENV" echo "cache_test_restore_key=$cache_test_restore_key" | tee -a "$GITHUB_ENV" echo "cache_test_key=$cache_test_key" | tee -a "$GITHUB_ENV" - - - name: Restore verilator cache - id: cache-verilator-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/verilator - /opt/verilator/.cache - key: ${{ env.cache_verilator_key }} - - name: Setup tests cache uses: actions/cache@v3 id: cache-test-setup @@ -74,6 +60,7 @@ jobs: submodules: recursive - name: install SiteSpawner package + shell: bash run: | python3 -m venv .venv .venv/bin/python3 -m pip install tools/SiteSpawner @@ -82,6 +69,7 @@ jobs: python3 -m pip install tools/SiteSpawner - name: Setup environment + shell: bash run: | echo "/opt/verilator/bin" >> $GITHUB_PATH RV_ROOT=`pwd` @@ -92,13 +80,16 @@ jobs: echo "TEST_PATH=$TEST_PATH" >> $GITHUB_ENV - name: Run tests + shell: bash run: | export PATH=/opt/verilator/bin:$PATH export RV_ROOT=`pwd` .github/scripts/run_regression_test.sh $TEST_PATH ${{ matrix.bus }} ${{ matrix.test}} ${{ matrix.coverage }} ${{ matrix.priv }} - name: Prepare coverage data + shell: bash run: | + source .venv/bin/activate sis -d convert --dat-dir ${TEST_PATH}/ mkdir -p results mv ${TEST_PATH}/coverage.info \ diff --git a/.github/workflows/test-renode.yml b/.github/workflows/test-renode.yml index 159e394ee4f..fad11edf576 100644 --- a/.github/workflows/test-renode.yml +++ b/.github/workflows/test-renode.yml @@ -6,10 +6,10 @@ on: jobs: tests: runs-on: ubuntu-latest + container: ghcr.io/antmicro/cores-veer-el2:latest strategy: fail-fast: false env: - RENODE_VERSION: latest DEBIAN_FRONTEND: "noninteractive" steps: - name: Clone repository @@ -17,29 +17,6 @@ jobs: with: submodules: recursive - - name: Setup Cache Metadata - id: cache_metadata - run: | - date=$(date +"%Y_%m_%d") - time=$(date +"%Y%m%d_%H%M%S_%N") - cache_renode_restore_key=cache_renode_ - cache_renode_key=${cache_renode_restore_key}${{ env.RENODE_VERSION }} - - echo "date=$date" | tee -a "$GITHUB_ENV" - echo "time=$time" | tee -a "$GITHUB_ENV" - echo "cache_renode_restore_key=$cache_renode_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_renode_key=$cache_renode_key" | tee -a "$GITHUB_ENV" - - - name: Restore Renode cache - id: cache-renode-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/renode - key: ${{ env.cache_renode_key }} - restore-keys: ${{ env.cache_renode_restore_key }} - fail-on-cache-miss: true - - name: Install dependencies run: | sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ diff --git a/.github/workflows/test-riscof.yml b/.github/workflows/test-riscof.yml index cf41ee62984..9d262df12a1 100644 --- a/.github/workflows/test-riscof.yml +++ b/.github/workflows/test-riscof.yml @@ -8,6 +8,7 @@ jobs: tests: name: Run RISCOF tests runs-on: ubuntu-latest + container: ghcr.io/antmicro/cores-veer-el2:latest strategy: fail-fast: false matrix: @@ -16,8 +17,6 @@ jobs: env: DEBIAN_FRONTEND: "noninteractive" CCACHE_DIR: "/opt/riscof/.cache/" - VERILATOR_VERSION: v5.024 - SPIKE_VERSION: d70ea67d steps: - name: Install utils @@ -32,40 +31,13 @@ jobs: run: | date=$(date +"%Y_%m_%d") time=$(date +"%Y%m%d_%H%M%S_%N") - cache_verilator_restore_key=cache_verilator_ - cache_verilator_key=${cache_verilator_restore_key}${{ env.VERILATOR_VERSION }}_${{ env.VERILATOR_COMMIT }} - cache_spike_restore_key=cache_spike_ - cache_spike_key=${cache_spike_restore_key}${{ env.SPIKE_VERSION }} cache_test_restore_key=${{ matrix.test }}_${{ matrix.coverage }}_ cache_test_key=${cache_test_restore_key}${time} echo "date=$date" | tee -a "$GITHUB_ENV" echo "time=$time" | tee -a "$GITHUB_ENV" - echo "cache_verilator_restore_key=$cache_verilator_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_verilator_key=$cache_verilator_key" | tee -a "$GITHUB_ENV" - echo "cache_spike_restore_key=$cache_spike_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_spike_key=$cache_spike_key" | tee -a "$GITHUB_ENV" echo "cache_test_restore_key=$cache_test_restore_key" | tee -a "$GITHUB_ENV" echo "cache_test_key=$cache_test_key" | tee -a "$GITHUB_ENV" - - name: Restore Verilator cache - id: cache-verilator-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/verilator - /opt/verilator/.cache - key: ${{ env.cache_verilator_key }} - - - name: Restore Spike cache - id: cache-spike-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/spike - /opt/spike/.cache - key: ${{ env.cache_spike_key }} - restore-keys: ${{ env.cache_spike_restore_key }} - - name: Setup tests cache uses: actions/cache@v3 id: cache-test-setup @@ -96,6 +68,7 @@ jobs: submodules: recursive - name: install SiteSpawner package + shell: bash run: | python3 -m venv .venv .venv/bin/python3 -m pip install tools/SiteSpawner @@ -108,6 +81,7 @@ jobs: pip3 install git+https://github.com/riscv/riscof@a25e315 - name: Clone tests + shell: bash run: | mkdir -p riscof pushd riscof @@ -118,6 +92,7 @@ jobs: popd - name: Configure RISCOF + shell: bash run: | pushd riscof # Copy RISCOF configuration @@ -129,6 +104,7 @@ jobs: popd - name: Build VeeR model + shell: bash run: | export PATH=/opt/verilator/bin:$PATH export RV_ROOT=`pwd` @@ -142,6 +118,7 @@ jobs: popd - name: Run tests, collect coverage + shell: bash run: | export PATH=/opt/verilator/bin:/opt/spike/bin:$PATH pushd riscof @@ -151,6 +128,7 @@ jobs: popd - name: Prepare coverage data + shell: bash run: | export PATH=/opt/verilator/bin:$PATH sis -d convert --dat-dir riscof/coverage/ @@ -158,8 +136,9 @@ jobs: riscof/coverage/coverage_riscof_${{matrix.priv}}_${{ matrix.coverage }}.info - name: Prepare report + shell: bash run: | - PYTEST_STYLE_SRC_DIR=${{ github.workspace }}/.github/scripts/pytest/ + PYTEST_STYLE_SRC_DIR=$(pwd)/.github/scripts/pytest/ PYTEST_CSS=${PYTEST_STYLE_SRC_DIR}/css/styles.css pushd riscof/riscof_work bash ${PYTEST_STYLE_SRC_DIR}/style_pytest_report.sh ${PYTEST_STYLE_SRC_DIR} . report.html diff --git a/.github/workflows/test-riscv-dv.yml b/.github/workflows/test-riscv-dv.yml index fae8f5b9fc9..16afe199f1b 100644 --- a/.github/workflows/test-riscv-dv.yml +++ b/.github/workflows/test-riscv-dv.yml @@ -71,6 +71,7 @@ jobs: - name: Generate code (pyflow) if: steps.cache-code.outputs.cache-hit != 'true' && matrix.version == 'pyflow' + shell: bash run: | export RV_ROOT=`realpath .` pushd tools/riscv-dv @@ -97,6 +98,7 @@ jobs: run-tests: name: Run RISC-V DV tests runs-on: ubuntu-latest + container: ghcr.io/antmicro/cores-veer-el2:latest needs: [ generate-config, generate-code ] strategy: fail-fast: false @@ -127,9 +129,6 @@ jobs: env: DEBIAN_FRONTEND: "noninteractive" CCACHE_DIR: "/opt/riscv-dv/.cache/" - VERILATOR_VERSION: v5.024 - SPIKE_VERSION: d70ea67d - RENODE_VERSION: latest CACHE_HASH: ${{ needs.generate-config.outputs.hash }} steps: @@ -143,6 +142,7 @@ jobs: # As of July 9th, 2024 `ubuntu:latest` comes with riscv64-unknown-elf-gcc # 10.0.2. We need a newer version for bitmanip extension support. - name: Install cross-compiler + shell: bash run: | echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ @@ -154,66 +154,23 @@ jobs: run: | date=$(date +"%Y_%m_%d") time=$(date +"%Y%m%d_%H%M%S_%N") - cache_verilator_restore_key=cache_verilator_ - cache_verilator_key=${cache_verilator_restore_key}${{ env.VERILATOR_VERSION }}_${{ env.VERILATOR_COMMIT }} - cache_spike_restore_key=cache_spike_ - cache_spike_key=${cache_spike_restore_key}${{ env.SPIKE_VERSION }} - cache_renode_restore_key=cache_renode_ - cache_renode_key=${cache_renode_restore_key}${{ env.RENODE_VERSION }} cache_test_restore_key=${{ matrix.test }}_${{ matrix.coverage }}_ cache_test_key=${cache_test_restore_key}${time} cache_code=cache_${{ matrix.test }}_${{ matrix.version }} echo "date=$date" | tee -a "$GITHUB_ENV" echo "time=$time" | tee -a "$GITHUB_ENV" - echo "cache_verilator_restore_key=$cache_verilator_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_verilator_key=$cache_verilator_key" | tee -a "$GITHUB_ENV" - echo "cache_spike_restore_key=$cache_spike_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_spike_key=$cache_spike_key" | tee -a "$GITHUB_ENV" - echo "cache_renode_restore_key=$cache_renode_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_renode_key=$cache_renode_key" | tee -a "$GITHUB_ENV" echo "cache_test_restore_key=$cache_test_restore_key" | tee -a "$GITHUB_ENV" echo "cache_test_key=$cache_test_key" | tee -a "$GITHUB_ENV" echo "cache_code=${cache_code}_${{ env.CACHE_HASH }}" | tee -a "$GITHUB_ENV" - - name: Restore verilator cache - id: cache-verilator-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/verilator - /opt/verilator/.cache - key: ${{ env.cache_verilator_key }} - restore-keys: ${{ env.cache_verilator_restore_key }} - fail-on-cache-miss: true - - - name: Restore Spike cache - id: cache-spike-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/spike - /opt/spike/.cache - key: ${{ env.cache_spike_key }} - restore-keys: ${{ env.cache_spike_restore_key }} - fail-on-cache-miss: true - - - name: Restore Renode cache - id: cache-renode-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/renode - key: ${{ env.cache_renode_key }} - restore-keys: ${{ env.cache_renode_restore_key }} - fail-on-cache-miss: true - - name: Setup repository uses: actions/checkout@v3 with: submodules: recursive - name: install SiteSpawner package + shell: bash run: | python3 -m venv .venv .venv/bin/python3 -m pip install tools/SiteSpawner @@ -240,17 +197,16 @@ jobs: key: cache_tests_${{ steps.cache_timestamp.outputs.time }} restore-keys: cache_tests_ - - name: Cache Code Restore - uses: actions/cache/restore@v3 - id: cache-code-restore - timeout-minutes: 60 + - name: Download Code Artifact + uses: actions/download-artifact@v3 with: - path: tools/riscv-dv/work/test_${{ matrix.test }}/asm_test - key: ${{ env.cache_code }} - fail-on-cache-miss: true + name: riscv-dv_generated_code_${{ matrix.version }} + path: tools/riscv-dv/work/ - name: Run test + shell: bash run: | + ls tools/riscv-dv/work export PATH=/opt/verilator/bin:$PATH export RV_ROOT=`realpath .` export RISCV_GCC=riscv64-unknown-elf-gcc @@ -313,8 +269,6 @@ jobs: env: DEBIAN_FRONTEND: "noninteractive" CCACHE_DIR: "/opt/riscv-dv/.cache/" - VERILATOR_VERSION: v5.024 - SPIKE_VERSION: d70ea67d GHA_EXTERNAL_DISK: additional-tools GHA_SA: gh-sa-veer-uploader CACHE_HASH: ${{ needs.generate-config.outputs.hash }} @@ -336,48 +290,16 @@ jobs: run: | date=$(date +"%Y_%m_%d") time=$(date +"%Y%m%d_%H%M%S_%N") - cache_verilator_restore_key=cache_verilator_ - cache_verilator_key=${cache_verilator_restore_key}${{ env.VERILATOR_VERSION }} - cache_spike_restore_key=cache_spike_ - cache_spike_key=${cache_spike_restore_key}${{ env.SPIKE_VERSION }} - cache_renode_restore_key=cache_renode_ - cache_renode_key=${cache_renode_restore_key}${{ env.RENODE_VERSION }} cache_test_restore_key=${{ matrix.test }}_${{ matrix.coverage }}_ cache_test_key=${cache_test_restore_key}${time} cache_code=cache_${{ matrix.test }}_${{ matrix.version }} echo "date=$date" | tee -a "$GITHUB_ENV" echo "time=$time" | tee -a "$GITHUB_ENV" - echo "cache_verilator_restore_key=$cache_verilator_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_verilator_key=$cache_verilator_key" | tee -a "$GITHUB_ENV" - echo "cache_spike_restore_key=$cache_spike_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_spike_key=$cache_spike_key" | tee -a "$GITHUB_ENV" - echo "cache_renode_restore_key=$cache_renode_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_renode_key=$cache_renode_key" | tee -a "$GITHUB_ENV" echo "cache_test_restore_key=$cache_test_restore_key" | tee -a "$GITHUB_ENV" echo "cache_test_key=$cache_test_key" | tee -a "$GITHUB_ENV" echo "cache_code=${cache_code}_${{ env.CACHE_HASH }}" | tee -a "$GITHUB_ENV" - - name: Restore verilator cache - id: cache-verilator-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/verilator - /opt/verilator/.cache - key: ${{ env.cache_verilator_key }} - restore-keys: ${{ env.cache_verilator_restore_key }} - - - name: Restore Spike cache - id: cache-spike-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/spike - /opt/spike/.cache - key: ${{ env.cache_spike_key }} - restore-keys: ${{ env.cache_spike_restore_key }} - - name: Cache Code Restore uses: actions/cache/restore@v3 id: cache-code-restore diff --git a/.github/workflows/test-uarch.yml b/.github/workflows/test-uarch.yml index 1b1f5ca56ba..a6844d6036e 100644 --- a/.github/workflows/test-uarch.yml +++ b/.github/workflows/test-uarch.yml @@ -3,13 +3,11 @@ name: VeeR-EL2 Microarchitectural tests on: workflow_call: -env: - VERILATOR_VERSION: v5.024 - jobs: lint: name: Lint microarchitectural tests runs-on: ubuntu-latest + container: ghcr.io/antmicro/cores-veer-el2:latest steps: - name: Setup repository uses: actions/checkout@v3 @@ -17,6 +15,7 @@ jobs: submodules: recursive - name: Setup environment + shell: bash run: | RV_ROOT=`pwd` echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV @@ -26,15 +25,20 @@ jobs: TEST_PATH=$RV_ROOT/verification/block echo "TEST_PATH=$TEST_PATH" >> $GITHUB_ENV - pip3 install nox + python3 -m venv .venv + source .venv/bin/activate + python3 -m pip install nox - name: Lint + shell: bash run: | + source .venv/bin/activate pushd ${TEST_PATH} nox -s test_lint popd tests: name: Microarchitectural tests runs-on: ubuntu-latest + container: ghcr.io/antmicro/cores-veer-el2:latest strategy: matrix: test: @@ -56,7 +60,6 @@ jobs: - "block/lsu_tl" env: CCACHE_DIR: "/opt/verification/.cache/" - VERILATOR_VERSION: v5.024 DEBIAN_FRONTEND: "noninteractive" steps: - name: Setup repository @@ -65,39 +68,27 @@ jobs: submodules: recursive - name: install SiteSpawner package + shell: bash run: | python3 -m venv .venv - .venv/bin/python3 -m pip install tools/SiteSpawner source .venv/bin/activate - echo "PATH=$PATH" >> $GITHUB_ENV python3 -m pip install tools/SiteSpawner + python3 -m pip install meson nox - name: Setup Cache Metadata id: cache_metadata + shell: bash run: | date=$(date +"%Y_%m_%d") time=$(date +"%Y%m%d_%H%M%S_%N") - cache_verilator_restore_key=cache_verilator_ - cache_verilator_key=${cache_verilator_restore_key}${{ env.VERILATOR_VERSION }}_${{ env.VERILATOR_COMMIT }} cache_test_restore_key=uarch_${{ matrix.test }}_${{ matrix.coverage }}_ cache_test_key=${cache_test_restore_key}${time} echo "date=$date" | tee -a "$GITHUB_ENV" echo "time=$time" | tee -a "$GITHUB_ENV" - echo "cache_verilator_restore_key=$cache_verilator_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_verilator_key=$cache_verilator_key" | tee -a "$GITHUB_ENV" echo "cache_test_restore_key=$cache_test_restore_key" | tee -a "$GITHUB_ENV" echo "cache_test_key=$cache_test_key" | tee -a "$GITHUB_ENV" - - name: Restore verilator cache - id: cache-verilator-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/verilator - /opt/verilator/.cache - key: ${{ env.cache_verilator_key }} - - name: Setup tests cache uses: actions/cache@v3 id: cache-test-setup @@ -125,6 +116,7 @@ jobs: sudo cpanm Bit::Vector - name: Setup environment + shell: bash run: | echo "/opt/verilator/bin" >> $GITHUB_PATH RV_ROOT=`pwd` @@ -143,17 +135,19 @@ jobs: # Fix random generator seed echo "RANDOM_SEED=1377424946" >> $GITHUB_ENV - pip3 install meson nox - - name: Run ${{ matrix.test }} + shell: bash run: | + source .venv/bin/activate pushd ${TEST_PATH} nox -s ${TEST_NAME}_verify popd - name: Prepare coverage data + shell: bash run: | export PATH=/opt/verilator/bin:$PATH + source .venv/bin/activate sis -d convert --dat-dir ${TEST_PATH}/${TEST_NAME}/ mkdir -p results mv ${TEST_PATH}/${TEST_NAME}/*.info results/ diff --git a/.github/workflows/test-uvm.yml b/.github/workflows/test-uvm.yml index dda98a5d8bb..5d089b67d24 100644 --- a/.github/workflows/test-uvm.yml +++ b/.github/workflows/test-uvm.yml @@ -7,10 +7,9 @@ jobs: tests: name: UVM tests runs-on: ubuntu-latest + container: ghcr.io/antmicro/cores-veer-el2:latest env: CCACHE_DIR: "/opt/uvm/.cache/" - VERILATOR_VERSION: uvm - VERILATOR_COMMIT: 7ca2d6470a DEBIAN_FRONTEND: "noninteractive" steps: - name: Setup repository @@ -23,28 +22,14 @@ jobs: run: | date=$(date +"%Y_%m_%d") time=$(date +"%Y%m%d_%H%M%S_%N") - cache_verilator_restore_key=cache_verilator_ - cache_verilator_key=${cache_verilator_restore_key}${{ env.VERILATOR_VERSION }}_${{ env.VERILATOR_COMMIT }} cache_test_restore_key=${{ matrix.test }}_${{ matrix.coverage }}_ cache_test_key=${cache_test_restore_key}${time} echo "date=$date" | tee -a "$GITHUB_ENV" echo "time=$time" | tee -a "$GITHUB_ENV" - echo "cache_verilator_restore_key=$cache_verilator_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_verilator_key=$cache_verilator_key" | tee -a "$GITHUB_ENV" echo "cache_test_restore_key=$cache_test_restore_key" | tee -a "$GITHUB_ENV" echo "cache_test_key=$cache_test_key" | tee -a "$GITHUB_ENV" - - - name: Restore verilator cache - id: cache-verilator-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/verilator - /opt/verilator/.cache - key: ${{ env.cache_verilator_key }} - - name: Setup tests cache uses: actions/cache@v3 id: cache-test-setup @@ -62,7 +47,7 @@ jobs: - name: Setup environment run: | - echo "/opt/verilator/bin" >> $GITHUB_PATH + echo "/opt/verilator_uvm/bin" >> $GITHUB_PATH RV_ROOT=`pwd` echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV PYTHONUNBUFFERED=1 diff --git a/.github/workflows/test-verification.yml b/.github/workflows/test-verification.yml index 252e2bcd867..e13d95d364b 100644 --- a/.github/workflows/test-verification.yml +++ b/.github/workflows/test-verification.yml @@ -3,21 +3,18 @@ name: VeeR-EL2 verification on: workflow_call: -env: - VERILATOR_VERSION: v5.024 - jobs: tests: name: Verification tests runs-on: ubuntu-latest + container: ghcr.io/antmicro/cores-veer-el2:latest strategy: matrix: test: ["test_pyuvm"] coverage: ["all", "branch", "toggle"] #TODO: add functional coverage env: - CCACHE_DIR: "/opt/verification/.cache/" - VERILATOR_VERSION: v5.024 DEBIAN_FRONTEND: "noninteractive" + CCACHE_DIR: "/opt/regression/.cache/" steps: - name: Setup repository uses: actions/checkout@v3 @@ -25,40 +22,26 @@ jobs: submodules: recursive - name: install SiteSpawner package + shell: bash run: | python3 -m venv .venv - .venv/bin/python3 -m pip install tools/SiteSpawner source .venv/bin/activate - echo "PATH=$PATH" >> $GITHUB_ENV python3 -m pip install tools/SiteSpawner - name: Setup Cache Metadata id: cache_metadata + shell: bash run: | date=$(date +"%Y_%m_%d") time=$(date +"%Y%m%d_%H%M%S_%N") - cache_verilator_restore_key=cache_verilator_ - cache_verilator_key=${cache_verilator_restore_key}${{ env.VERILATOR_VERSION }}_${{ env.VERILATOR_COMMIT }} cache_test_restore_key=${{ matrix.test }}_${{ matrix.coverage }}_ cache_test_key=${cache_test_restore_key}${time} echo "date=$date" | tee -a "$GITHUB_ENV" echo "time=$time" | tee -a "$GITHUB_ENV" - echo "cache_verilator_restore_key=$cache_verilator_restore_key" | tee -a "$GITHUB_ENV" - echo "cache_verilator_key=$cache_verilator_key" | tee -a "$GITHUB_ENV" echo "cache_test_restore_key=$cache_test_restore_key" | tee -a "$GITHUB_ENV" echo "cache_test_key=$cache_test_key" | tee -a "$GITHUB_ENV" - - - name: Restore verilator cache - id: cache-verilator-restore - uses: actions/cache/restore@v3 - with: - path: | - /opt/verilator - /opt/verilator/.cache - key: ${{ env.cache_verilator_key }} - - name: Setup tests cache uses: actions/cache@v3 id: cache-test-setup @@ -86,6 +69,7 @@ jobs: sudo cpanm Bit::Vector - name: Setup environment + shell: bash run: | echo "/opt/verilator/bin" >> $GITHUB_PATH RV_ROOT=`pwd` @@ -95,11 +79,14 @@ jobs: TEST_PATH=$RV_ROOT/verification/top/${{ matrix.test }} echo "TEST_PATH=$TEST_PATH" >> $GITHUB_ENV + - name: Run ${{ matrix.test }} + shell: bash run: | + source .venv/bin/activate pip3 install meson pip3 install -r $RV_ROOT/verification/top/requirements.txt - PYTEST_STYLE_SRC_DIR=${{ github.workspace }}/.github/scripts/pytest/ + PYTEST_STYLE_SRC_DIR=$RV_ROOT/.github/scripts/pytest/ PYTEST_CSS=${PYTEST_STYLE_SRC_DIR}/css/styles.css HTML_FILE=${{ matrix.test }}_${{ matrix.COVERAGE }}.html pushd ${TEST_PATH} @@ -108,18 +95,22 @@ jobs: popd - name: Prepare pytest-html data + shell: bash run: | - pushd ${{ github.workspace }} + source .venv/bin/activate + pushd $RV_ROOT WEBPAGE_DIR=webpage_${{ matrix.test }}_${{ matrix.COVERAGE }} mkdir -p $WEBPAGE_DIR mv ${TEST_PATH}/${{ matrix.test }}_${{ matrix.COVERAGE }}.html $WEBPAGE_DIR mv ${TEST_PATH}/assets $WEBPAGE_DIR - JS_SCRIPT_DIR=${{ github.workspace }}/.github/scripts/pytest/script + JS_SCRIPT_DIR=$RV_ROOT/.github/scripts/pytest/script mv $JS_SCRIPT_DIR $WEBPAGE_DIR popd - name: Prepare coverage data + shell: bash run: | + source .venv/bin/activate export PATH=/opt/verilator/bin:$PATH sis -d convert --dat-dir ${TEST_PATH} mkdir -p results From e1ef54f07da7d4121c903e1f6eb6a26120a66d38 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Tue, 1 Oct 2024 14:11:39 +0200 Subject: [PATCH 03/11] test the debug module with GDB Signed-off-by: Wojciech Sipak --- .github/scripts/breakpoint.gdb | 29 ++++ .github/scripts/breakpoint.sh | 25 ++++ .github/scripts/breakpoint_golden.txt | 1 + .github/scripts/dump_and_compare.sh | 28 ++++ .github/scripts/dump_registers.gdb | 24 ++++ .github/scripts/gdb_test.sh | 115 +++++++++++++++ .github/scripts/mem_access.gdb | 135 ++++++++++++++++++ .github/scripts/mem_access.sh | 27 ++++ .github/scripts/mem_access_golden.txt | 3 + .../openocd/board/caliptra-verilator-rst.cfg | 5 + .../openocd/board/caliptra-verilator.cfg | 5 + .github/scripts/openocd/sim-jtagdpi.cfg | 11 ++ .github/scripts/openocd/veer-el2-rst.cfg | 29 ++++ .github/scripts/openocd/veer-el2.cfg | 26 ++++ .github/scripts/peripheral_access.gdb | 44 ++++++ .github/scripts/peripheral_access.sh | 25 ++++ .github/scripts/peripheral_access.tcl | 68 +++++++++ .github/scripts/peripheral_access_golden.txt | 9 ++ .github/scripts/regdump_golden.txt | 28 ++++ .github/workflows/build-openocd.yml | 2 +- .github/workflows/test-openocd.yml | 71 +++++++++ 21 files changed, 709 insertions(+), 1 deletion(-) create mode 100644 .github/scripts/breakpoint.gdb create mode 100755 .github/scripts/breakpoint.sh create mode 100644 .github/scripts/breakpoint_golden.txt create mode 100755 .github/scripts/dump_and_compare.sh create mode 100644 .github/scripts/dump_registers.gdb create mode 100755 .github/scripts/gdb_test.sh create mode 100644 .github/scripts/mem_access.gdb create mode 100755 .github/scripts/mem_access.sh create mode 100644 .github/scripts/mem_access_golden.txt create mode 100644 .github/scripts/openocd/board/caliptra-verilator-rst.cfg create mode 100644 .github/scripts/openocd/board/caliptra-verilator.cfg create mode 100644 .github/scripts/openocd/sim-jtagdpi.cfg create mode 100644 .github/scripts/openocd/veer-el2-rst.cfg create mode 100644 .github/scripts/openocd/veer-el2.cfg create mode 100644 .github/scripts/peripheral_access.gdb create mode 100755 .github/scripts/peripheral_access.sh create mode 100644 .github/scripts/peripheral_access.tcl create mode 100644 .github/scripts/peripheral_access_golden.txt create mode 100644 .github/scripts/regdump_golden.txt diff --git a/.github/scripts/breakpoint.gdb b/.github/scripts/breakpoint.gdb new file mode 100644 index 00000000000..0da002f6ed0 --- /dev/null +++ b/.github/scripts/breakpoint.gdb @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +echo Connecting to OpenOCD...\n +set architecture riscv:rv32 +set remotetimeout 30 +target extended-remote :3333 + +echo Connected, waiting...\n +shell sleep 5s + +echo Setting Breakpoint 1...\n +hbreak *0x1c + +echo Continuing...\n +continue + +delete diff --git a/.github/scripts/breakpoint.sh b/.github/scripts/breakpoint.sh new file mode 100755 index 00000000000..2ad16bc9da5 --- /dev/null +++ b/.github/scripts/breakpoint.sh @@ -0,0 +1,25 @@ +#!/bin/bash +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +set -ex + +# Invoke GDB +${GCC_PREFIX}-gdb -n --batch -x breakpoint.gdb >gdb.log +# Parse the log +cat gdb.log | grep 'Breakpoint 1,' >breakpoint.txt + +# Compare the dumps +diff -E -y breakpoint.txt breakpoint_golden.txt || true + diff --git a/.github/scripts/breakpoint_golden.txt b/.github/scripts/breakpoint_golden.txt new file mode 100644 index 00000000000..eeb5ad39723 --- /dev/null +++ b/.github/scripts/breakpoint_golden.txt @@ -0,0 +1 @@ +Breakpoint 1, 0x0000001c in ?? () diff --git a/.github/scripts/dump_and_compare.sh b/.github/scripts/dump_and_compare.sh new file mode 100755 index 00000000000..354dedd67dd --- /dev/null +++ b/.github/scripts/dump_and_compare.sh @@ -0,0 +1,28 @@ +#!/bin/bash +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +set -ex + +# Invoke GDB and dump core registers +${GCC_PREFIX}-gdb -n --batch -x dump_registers.gdb >gdb.log +# Parse the log, extract register values. Skip those which change as the +# program executes since we don't know at which point we tap in. +cat gdb.log | grep -E '^ra |^sp |^gp |^tp |^t[01256] |^s[0-9]+ |^a[0-9]+ |^\$[0-9]+' >regdump.txt + +# Compare the dumps +# TODO this temporarily exits with success just to allow collecting coverage data +# without considering the truthness of register values. +diff -E -y regdump_golden.txt regdump.txt || true + diff --git a/.github/scripts/dump_registers.gdb b/.github/scripts/dump_registers.gdb new file mode 100644 index 00000000000..6e491afd504 --- /dev/null +++ b/.github/scripts/dump_registers.gdb @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +echo Connecting to OpenOCD...\n +set architecture riscv:rv32 +set remotetimeout 30 +target extended-remote :3333 + +echo Connected, waiting...\n +shell sleep 30s + +echo Dumping registers...\n +info registers diff --git a/.github/scripts/gdb_test.sh b/.github/scripts/gdb_test.sh new file mode 100755 index 00000000000..bfe5f78f29d --- /dev/null +++ b/.github/scripts/gdb_test.sh @@ -0,0 +1,115 @@ +#!/bin/bash +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# This script runs Verilator RTL simulation and OpenOCD in background, invokes +# the supplied test command and shuts everything down. + +SIM_LOG=`realpath sim.log` +OPENOCD_LOG=`realpath openocd.log` +GCC_PREFIX=riscv64-unknown-elf + +# Ensure that RISC-V toolchain is installed +if ! which ${GCC_PREFIX}-gcc >/dev/null; then + GCC_PREFIX=riscv32-unknown-elf +fi +if ! which ${GCC_PREFIX}-gcc >/dev/null; then + echo "RISC-V toolchain not found, please refer to https://github.com/chipsalliance/caliptra-rtl?tab=readme-ov-file#riscv-toolchain-installation for more details." + exit 1 +fi +export GCC_PREFIX + +set +e + +if [ "$#" -lt 1 ]; then + echo "Usage: gdb_test.sh [args ...]" + exit 1 +fi + +# Utils +source `dirname ${BASH_SOURCE[0]}`/utils.sh + +terminate_all () { + terminate ${OPENOCD_PID} + echo "waiting for the simulation to end: $SIM_PID" + wait ${SIM_PID} + # terminate ${SIM_PID} +} + +print_logs () { + echo -e "${COLOR_WHITE}======== Simulation log ========${COLOR_OFF}" + cat ${SIM_LOG} || true + echo -e "${COLOR_WHITE}======== OpenOCD log ========${COLOR_OFF}" + cat ${OPENOCD_LOG} || true +} + +echo -e "${COLOR_WHITE}======== Launching interactive simulation ========${COLOR_OFF}" + +# Start the simulation +echo -e "Starting simulation..." +./obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 & +SIM_PID=$! + +# Wait +wait_for_phrase "${SIM_LOG}" "Start of sim" +# TODO handle proper string in the output instead of waiting +sleep 10s +retcode=$? +if [ $retcode -ne 0 ]; then + echo -e "${COLOR_RED}Failed to start the simulation: $retcode ${COLOR_OFF}" + print_logs + terminate_all; exit -1 +fi +echo -e "Simulation running and ready (pid=${SIM_PID})" + +# Launch OpenOCD +echo -e "Launching OpenOCD..." +cd ${RV_ROOT}/.github/scripts/openocd && openocd --debug --file board/caliptra-verilator.cfg >"${OPENOCD_LOG}" 2>&1 & +OPENOCD_PID=$! + +# Wait +wait_for_phrase "${OPENOCD_LOG}" "Listening on port 3333 for gdb connections" +if [ $? -ne 0 ]; then + echo -e "${COLOR_RED}Failed to start OpenOCD!${COLOR_OFF}" + print_logs + terminate_all; exit -1 +fi +echo -e "OpenOCD running and ready (pid=${OPENOCD_PID})" + +# Wait a bit +sleep 1s + +# Run the test +echo -e "${COLOR_WHITE}======== Running test '$@' ========${COLOR_OFF}" + +bash -c "$(printf ' %q' "$@")" +EXITCODE=$? + +if [ ${EXITCODE} -eq 0 ]; then + echo -e "${COLOR_GREEN}[PASSED]${COLOR_OFF}" +else + echo -e "${COLOR_RED}[FAILED]${COLOR_OFF}" +fi + +sleep 1s + +# Terminate +echo -e "${COLOR_WHITE}Terminating...${COLOR_OFF}" +terminate_all + +# Display logs +print_logs + +# Honor the exitcode +exit ${EXITCODE} diff --git a/.github/scripts/mem_access.gdb b/.github/scripts/mem_access.gdb new file mode 100644 index 00000000000..ad57ad63271 --- /dev/null +++ b/.github/scripts/mem_access.gdb @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +echo Connecting to OpenOCD...\n +set architecture riscv:rv32 +set remotetimeout 30 +target extended-remote :3333 + +echo Connected, waiting...\n +shell sleep 5s + +echo Accessing DCCM...\n +set *(0x00080000) = 0x01234567 +set *(0x00080004) = 0x89ABCDEF +set *(0x00080008) = 0x55555555 +set *(0x0008000C) = 0xAAAAAAAA +print/x *0x00080000@4 + +# TODO why does the default configuration for iccm (0xe000000) differ from the documentation (0x40000)? +echo Accessing ICCM...\n +set *(0x0e000000) = 0x01234567 +set *(0x0e000004) = 0x89ABCDEF +set *(0x0e000008) = 0x55555555 +set *(0x0e00000C) = 0xAAAAAAAA +print/x *0x00e00000@4 + +echo Accessing region at 0x20000000...\n +set *(0x20000000) = 0x01234567 +set *(0x20000004) = 0x89ABCDEF +set *(0x20000008) = 0x55555555 +set *(0x2000000C) = 0xAAAAAAAA +print/x *0x20000000@4 + +echo Accessing region at 0x30000000...\n +set *(0x30000000) = 0x01234567 +set *(0x30000004) = 0x89ABCDEF +set *(0x30000008) = 0x55555555 +set *(0x3000000C) = 0xAAAAAAAA +print/x *0x30000000@4 + +echo Accessing region at 0x40000000...\n +set *(0x40000000) = 0x01234567 +set *(0x40000004) = 0x89ABCDEF +set *(0x40000008) = 0x55555555 +set *(0x4000000C) = 0xAAAAAAAA +print/x *0x40000000@4 + +echo Accessing region at 0x50000000...\n +set *(0x50000000) = 0x01234567 +set *(0x50000004) = 0x89ABCDEF +set *(0x50000008) = 0x55555555 +set *(0x5000000C) = 0xAAAAAAAA +print/x *0x50000000@4 + +echo Accessing region at 0x60000000...\n +set *(0x60000000) = 0x01234567 +set *(0x60000004) = 0x89ABCDEF +set *(0x60000008) = 0x55555555 +set *(0x6000000C) = 0xAAAAAAAA +print/x *0x60000000@4 + +echo Accessing region at 0x70000000...\n +set *(0x70000000) = 0x01234567 +set *(0x70000004) = 0x89ABCDEF +set *(0x70000008) = 0x55555555 +set *(0x7000000C) = 0xAAAAAAAA +print/x *0x70000000@4 + +echo Accessing region at 0x80000000...\n +set *(0x80000000) = 0x01234567 +set *(0x80000004) = 0x89ABCDEF +set *(0x80000008) = 0x55555555 +set *(0x8000000C) = 0xAAAAAAAA +print/x *0x80000000@4 + +echo Accessing region at 0x90000000...\n +set *(0x90000000) = 0x01234567 +set *(0x90000004) = 0x89ABCDEF +set *(0x90000008) = 0x55555555 +set *(0x9000000C) = 0xAAAAAAAA +print/x *0x90000000@4 + +echo Accessing region at 0xa0000000...\n +set *(0xa0000000) = 0x01234567 +set *(0xa0000004) = 0x89ABCDEF +set *(0xa0000008) = 0x55555555 +set *(0xa000000C) = 0xAAAAAAAA +print/x *0xa0000000@4 + +echo Accessing region at 0xb0000000...\n +set *(0xb0000000) = 0x01234567 +set *(0xb0000004) = 0x89ABCDEF +set *(0xb0000008) = 0x55555555 +set *(0xb000000C) = 0xAAAAAAAA +print/x *0xb0000000@4 + +echo Accessing region at 0xc0000000...\n +set *(0xc0000000) = 0x01234567 +set *(0xc0000004) = 0x89ABCDEF +set *(0xc0000008) = 0x55555555 +set *(0xc000000C) = 0xAAAAAAAA +print/x *0xc0000000@4 + +echo Accessing region at 0xd0000000...\n +set *(0xd0000000) = 0x01234567 +set *(0xd0000004) = 0x89ABCDEF +set *(0xd0000008) = 0x55555555 +set *(0xd000000C) = 0xAAAAAAAA +print/x *0xd0000000@4 + +echo Accessing region at 0xe0000000...\n +set *(0xe0000000) = 0x01234567 +set *(0xe0000004) = 0x89ABCDEF +set *(0xe0000008) = 0x55555555 +set *(0xe000000C) = 0xAAAAAAAA +print/x *0xe0000000@4 + +echo Accessing region at 0xf0000000...\n +set *(0xf0000000) = 0x01234567 +set *(0xf0000004) = 0x89ABCDEF +set *(0xf0000008) = 0x55555555 +set *(0xf000000C) = 0xAAAAAAAA +print/x *0xf0000000@4 + diff --git a/.github/scripts/mem_access.sh b/.github/scripts/mem_access.sh new file mode 100755 index 00000000000..bc4cabdc193 --- /dev/null +++ b/.github/scripts/mem_access.sh @@ -0,0 +1,27 @@ +#!/bin/bash +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +set -ex + +# Invoke GDB +${GCC_PREFIX}-gdb -n --batch -x mem_access.gdb >gdb.log +# Parse the log +cat gdb.log | grep -E '^\$[0-9]+' >out.txt + +# Compare the dumps +# TODO this temporarily exits with success just to allow collecting coverage data +# without considering the truthness of reported values. +diff -E -y mem_access_golden.txt out.txt || true + diff --git a/.github/scripts/mem_access_golden.txt b/.github/scripts/mem_access_golden.txt new file mode 100644 index 00000000000..1f6b009253f --- /dev/null +++ b/.github/scripts/mem_access_golden.txt @@ -0,0 +1,3 @@ +$1 = {0xcafebaba, 0xdeadbeef, 0xfeedbaca, 0xa5a5a5a5} +$2 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa} +$3 = {0xaaaab0b7, 0xaaa08093, 0x7c009073, 0x90734191, 0x50b77f91, 0x80931234, 0xf1376780, 0x7111abcd} diff --git a/.github/scripts/openocd/board/caliptra-verilator-rst.cfg b/.github/scripts/openocd/board/caliptra-verilator-rst.cfg new file mode 100644 index 00000000000..a8bfb01c331 --- /dev/null +++ b/.github/scripts/openocd/board/caliptra-verilator-rst.cfg @@ -0,0 +1,5 @@ +source [find sim-jtagdpi.cfg] +source [find veer-el2-rst.cfg] + +# Increase timeouts in simulation +riscv set_command_timeout_sec 300 diff --git a/.github/scripts/openocd/board/caliptra-verilator.cfg b/.github/scripts/openocd/board/caliptra-verilator.cfg new file mode 100644 index 00000000000..95a8d0144f1 --- /dev/null +++ b/.github/scripts/openocd/board/caliptra-verilator.cfg @@ -0,0 +1,5 @@ +source [find sim-jtagdpi.cfg] +source [find veer-el2.cfg] + +# Increase timeouts in simulation +riscv set_command_timeout_sec 300 diff --git a/.github/scripts/openocd/sim-jtagdpi.cfg b/.github/scripts/openocd/sim-jtagdpi.cfg new file mode 100644 index 00000000000..7d43a4ad5e3 --- /dev/null +++ b/.github/scripts/openocd/sim-jtagdpi.cfg @@ -0,0 +1,11 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket +# speaking the remote_bitbang protocol. The adapter is implemented as +# SystemVerilog DPI module. + +adapter driver remote_bitbang +remote_bitbang port 5000 +remote_bitbang host localhost diff --git a/.github/scripts/openocd/veer-el2-rst.cfg b/.github/scripts/openocd/veer-el2-rst.cfg new file mode 100644 index 00000000000..c90f24266da --- /dev/null +++ b/.github/scripts/openocd/veer-el2-rst.cfg @@ -0,0 +1,29 @@ +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME riscv +} + +jtag newtap $_CHIPNAME tap -irlen 5 +set _TARGETNAME $_CHIPNAME.tap +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread + +# Configure work area in on-chip SRAM +$_TARGETNAME.0 configure -work-area-phys 0x50001000 -work-area-size 0x1000 -work-area-backup 0 + +# Mem access mode +riscv set_mem_access sysbus + +# The following commands disable target examination and set explicitly the +# core parameters read from CSRs. These required a modified version of +# OpenOCD from https://github.com/antmicro/openocd/tree/riscv-nohalt +riscv set_nohalt on +riscv set_xlen 32 +riscv set_misa 0x40001104 + +# Be verbose about GDB errors +gdb_report_data_abort enable +gdb_report_register_access_error enable + +# Always use hardware breakpoints. +gdb_breakpoint_override hard diff --git a/.github/scripts/openocd/veer-el2.cfg b/.github/scripts/openocd/veer-el2.cfg new file mode 100644 index 00000000000..735923890a8 --- /dev/null +++ b/.github/scripts/openocd/veer-el2.cfg @@ -0,0 +1,26 @@ +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME riscv +} + +jtag newtap $_CHIPNAME tap -irlen 5 +set _TARGETNAME $_CHIPNAME.tap +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread + +# Configure work area in on-chip SRAM +$_TARGETNAME.0 configure -work-area-phys 0x50001000 -work-area-size 0x1000 -work-area-backup 0 + +$_TARGETNAME.0 configure -event gdb-detach { + resume +} + +# Mem access mode +riscv set_mem_access abstract + +# Be verbose about GDB errors +gdb_report_data_abort enable +gdb_report_register_access_error enable + +# Always use hardware breakpoints. +gdb_breakpoint_override hard diff --git a/.github/scripts/peripheral_access.gdb b/.github/scripts/peripheral_access.gdb new file mode 100644 index 00000000000..473466eebd7 --- /dev/null +++ b/.github/scripts/peripheral_access.gdb @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +echo Connecting to OpenOCD...\n +set architecture riscv:rv32 +set remotetimeout 30 +target extended-remote :3333 + +echo Connected, waiting...\n +shell sleep 5s + +echo Accessing ECC...\n +print/x *0x10008000@2 +print/x *0x10008008@2 + +echo Accessing HMAC...\n +print/x *0x10010000@2 +print/x *0x10010008@2 + +echo Accessing SHA512...\n +print/x *0x10020000@2 +print/x *0x10020008@2 + +echo Accessing SHA256...\n +print/x *0x10028000@2 +print/x *0x10028008@2 + +echo Writing and reading DOE IV...\n +set *(0x10000000) = 0xCAFEBABA +set *(0x10000004) = 0xDEADBEEF +set *(0x10000008) = 0xD0ED0E00 +print/x *0x10000000@3 + diff --git a/.github/scripts/peripheral_access.sh b/.github/scripts/peripheral_access.sh new file mode 100755 index 00000000000..2db9a2f2bb8 --- /dev/null +++ b/.github/scripts/peripheral_access.sh @@ -0,0 +1,25 @@ +#!/bin/bash +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +set -ex + +# Invoke GDB +${GCC_PREFIX}-gdb -n --batch -x peripheral_access.gdb >gdb.log +# Parse the log +cat gdb.log | grep -E '^\$[0-9]+' >peripheral_access.txt + +# Compare the dumps +diff -E -y peripheral_access_golden.txt peripheral_access.txt || true + diff --git a/.github/scripts/peripheral_access.tcl b/.github/scripts/peripheral_access.tcl new file mode 100644 index 00000000000..98d31ff9fae --- /dev/null +++ b/.github/scripts/peripheral_access.tcl @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +init + +set script_dir [file dirname [info script]] +source [file join $script_dir common.tcl] + +# Manually read dmstatus and check if the core is actually held in external +# reset. In the expected state bits anyunavail allrunning anyrunning allhalted +# and anyhalted should be cleared. +set val [riscv dmi_read $dmstatus_addr] +puts "dmstatus: $val" + +if { ($val & 0x00000F00) != 0 } { + echo "The core is not held in reset!" + shutdown error +} + +echo "Accessing ECC..." +set golden { 0x63707365 0x38342d33 0x3030312e 0x0 } +set actual [ read_memory 0x10008000 32 4 phys ] +if {[compare $actual $golden] != 0} { + shutdown error +} + +echo "Accessing HMAC..." +set golden { 0x6163686d 0x61327368 0x3030322e 0x0 } +set actual [ read_memory 0x10010000 32 4 phys ] +if {[compare $actual $golden] != 0} { + shutdown error +} + +echo "Accessing SHA512..." +set golden { 0x61327368 0x31322d35 0x3830302e 0x0 } +set actual [ read_memory 0x10020000 32 4 phys ] +if {[compare $actual $golden] != 0} { + shutdown error +} + +echo "Accessing SHA256..." +set golden { 0x61327368 0x35362d32 0x3830312e 0x0 } +set actual [ read_memory 0x10028000 32 4 phys ] +if {[compare $actual $golden] != 0} { + shutdown error +} + +echo "Writing and reading DOE IV..." +set golden { 0xCAFEBABA 0xDEADBEEF 0xD0ED0E00 } +write_memory 0x10000000 32 $golden phys +set actual [ read_memory 0x10000000 32 3 phys ] +if {[compare $actual $golden] != 0} { + shutdown error +} + +# Success +shutdown diff --git a/.github/scripts/peripheral_access_golden.txt b/.github/scripts/peripheral_access_golden.txt new file mode 100644 index 00000000000..292097533fc --- /dev/null +++ b/.github/scripts/peripheral_access_golden.txt @@ -0,0 +1,9 @@ +$1 = {0x63707365, 0x38342d33} +$2 = {0x3030312e, 0x0} +$3 = {0x6163686d, 0x61327368} +$4 = {0x3030322e, 0x0} +$5 = {0x61327368, 0x31322d35} +$6 = {0x3830302e, 0x0} +$7 = {0x61327368, 0x35362d32} +$8 = {0x3830312e, 0x0} +$9 = {0xcafebaba, 0xdeadbeef, 0xd0ed0e00} diff --git a/.github/scripts/regdump_golden.txt b/.github/scripts/regdump_golden.txt new file mode 100644 index 00000000000..b1913bb9d73 --- /dev/null +++ b/.github/scripts/regdump_golden.txt @@ -0,0 +1,28 @@ +ra 0x12345678 0x12345678 +sp 0xabcdef00 0xabcdef00 +gp 0xcafebaba 0xcafebaba +tp 0xdeadbeef 0xdeadbeef +t0 0x5050505 84215045 +t1 0xa0a0a0a0 -1600085856 +t2 0xff00ff 16711935 +s1 0xfeedabed -17978387 +a0 0x0 0 +a1 0x0 0 +a2 0x0 0 +a3 0x0 0 +a4 0x0 0 +a5 0x0 0 +a6 0x0 0 +a7 0x0 0 +s2 0x0 0 +s3 0x0 0 +s4 0x0 0 +s5 0x0 0 +s6 0x0 0 +s7 0x0 0 +s8 0x0 0 +s9 0x0 0 +s10 0x0 0 +s11 0x0 0 +t5 0x0 0 +t6 0x0 0 diff --git a/.github/workflows/build-openocd.yml b/.github/workflows/build-openocd.yml index ee7e43a6f9e..54f6b1390c9 100644 --- a/.github/workflows/build-openocd.yml +++ b/.github/workflows/build-openocd.yml @@ -11,7 +11,7 @@ jobs: # A custom fork is needed to allow bypassing core examination and accessing # peripherals regardless of core state. OPENOCD_REPO: https://github.com/antmicro/openocd - OPENOCD_VERSION: riscv-nohalt + OPENOCD_VERSION: riscv-nohalt-change-module steps: - name: Setup Cache Metadata diff --git a/.github/workflows/test-openocd.yml b/.github/workflows/test-openocd.yml index fa64af13ae8..c18cd5e98b2 100644 --- a/.github/workflows/test-openocd.yml +++ b/.github/workflows/test-openocd.yml @@ -25,6 +25,9 @@ jobs: cpanminus ccache ninja-build gcc-riscv64-unknown-elf pip3 install meson sudo cpanm Bit::Vector + wget https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.09.03/riscv64-elf-ubuntu-22.04-gcc-nightly-2024.09.03-nightly.tar.gz + tar -xzf riscv64-elf-ubuntu-22.04-gcc-nightly-2024.09.03-nightly.tar.gz + mv riscv /opt/ - name: Setup Cache Metadata id: cache_metadata @@ -64,6 +67,62 @@ jobs: ${RV_ROOT}/.github/scripts/openocd_test.sh \ -f ${RV_ROOT}/testbench/openocd_scripts/verilator-rst.cfg \ -f ${RV_ROOT}/testbench/openocd_scripts/jtag_cg.tcl + pkill openocd || true + + - name: Test with GDB-test (register access) + run: | + # TODO GDB is in /opt/riscv and a separate toolchain is installed with apt. Make this better. + export PATH=/opt/riscv/bin:/opt/verilator/bin:/opt/openocd/bin:$PATH + export RV_ROOT=$(pwd) + mkdir reg_test + make -C reg_test -f ${RV_ROOT}/tools/Makefile verilator-build program.hex TEST=infinite_loop \ + CONF_PARAMS="-set build_${{ matrix.bus }} -set openocd_test" COVERAGE=${{ matrix.coverage }} + cd reg_test + ${RV_ROOT}/.github/scripts/gdb_test.sh \ + /bin/bash -c 'cd ${RV_ROOT}/.github/scripts && ./dump_and_compare.sh' || true + pkill openocd || true + + - name: Test with GDB-test (memory access) + run: | + # TODO GDB is in /opt/riscv and a separate toolchain is installed with apt. Make this better. + export PATH=/opt/riscv/bin:/opt/verilator/bin:/opt/openocd/bin:$PATH + export RV_ROOT=$(pwd) + mkdir mem_test + make -C mem_test -f ${RV_ROOT}/tools/Makefile verilator-build program.hex TEST=infinite_loop \ + CONF_PARAMS="-set build_${{ matrix.bus }} -set openocd_test" COVERAGE=${{ matrix.coverage }} + cd mem_test + ${RV_ROOT}/.github/scripts/gdb_test.sh \ + /bin/bash -c 'cd ${RV_ROOT}/.github/scripts && ./mem_access.sh' || true + pkill openocd || true + + - name: Test with GDB-test (peripheral access) + run: | + # TODO REMOVE THIS TEST, as we aim to target all possible memory regions in the test above this, + # and there are no actual peripherals in the tesbench. + + # TODO GDB is in /opt/riscv and a separate toolchain is installed with apt. Make this better. + export PATH=/opt/riscv/bin:/opt/verilator/bin:/opt/openocd/bin:$PATH + export RV_ROOT=$(pwd) + mkdir periph_test + make -C periph_test -f ${RV_ROOT}/tools/Makefile verilator-build program.hex TEST=infinite_loop \ + CONF_PARAMS="-set build_${{ matrix.bus }} -set openocd_test" COVERAGE=${{ matrix.coverage }} + cd periph_test + ${RV_ROOT}/.github/scripts/gdb_test.sh \ + /bin/bash -c 'cd ${RV_ROOT}/.github/scripts && ./peripheral_access.sh' || true + pkill openocd || true + + - name: Test with GDB-test (breakpoints) + run: | + # TODO GDB is in /opt/riscv and a separate toolchain is installed with apt. Make this better. + export PATH=/opt/riscv/bin:/opt/verilator/bin:/opt/openocd/bin:$PATH + export RV_ROOT=$(pwd) + mkdir breakpoint_test + make -C breakpoint_test -f ${RV_ROOT}/tools/Makefile verilator-build program.hex TEST=infinite_loop \ + CONF_PARAMS="-set build_${{ matrix.bus }} -set openocd_test" COVERAGE=${{ matrix.coverage }} + cd breakpoint_test + ${RV_ROOT}/.github/scripts/gdb_test.sh \ + /bin/bash -c 'cd ${RV_ROOT}/.github/scripts && ./breakpoint.sh' || true + pkill openocd || true - name: Prepare coverage data shell: bash @@ -71,9 +130,21 @@ jobs: export PATH=/opt/verilator/bin:$PATH export RV_ROOT=$(pwd) sis -d convert --dat-dir ${RV_ROOT}/run + sis -d convert --dat-dir ${RV_ROOT}/reg_test + sis -d convert --dat-dir ${RV_ROOT}/mem_test + sis -d convert --dat-dir ${RV_ROOT}/periph_test + sis -d convert --dat-dir ${RV_ROOT}/breakpoint_test mkdir -p results mv ${RV_ROOT}/run/coverage.info \ results/coverage_openocd_${{ matrix.bus }}_${{ matrix.coverage }}.info + mv ${RV_ROOT}/reg_test/coverage.info \ + results/coverage_openocd_reg_test_${{ matrix.bus }}_${{ matrix.coverage }}.info + mv ${RV_ROOT}/mem_test/coverage.info \ + results/coverage_openocd__mem_test_${{ matrix.bus }}_${{ matrix.coverage }}.info + mv ${RV_ROOT}/periph_test/coverage.info \ + results/coverage_openocd_periph_test_${{ matrix.bus }}_${{ matrix.coverage }}.info + mv ${RV_ROOT}/breakpoint_test/coverage.info \ + results/coverage_openocd_breakpoint_test_${{ matrix.bus }}_${{ matrix.coverage }}.info - name: Pack artifacts if: always() From f476e33ca4b629e77b9daa7033a83f57c7e53ec3 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Mon, 7 Oct 2024 13:31:05 +0200 Subject: [PATCH 04/11] verif: add no-table flags to all the tests Signed-off-by: Karol Gugala --- tools/Makefile | 2 +- tools/riscv-dv/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/Makefile b/tools/Makefile index f3e78b95327..09e7924a080 100755 --- a/tools/Makefile +++ b/tools/Makefile @@ -175,7 +175,7 @@ verilator-build: ${TBFILES} ${BUILD_DIR}/defines.h $(TB_VERILATOR_SRCS) $(VERILATOR) --cc -CFLAGS "${CFLAGS}" $(defines) \ $(includes) -I${RV_ROOT}/testbench -f ${RV_ROOT}/testbench/flist \ $(VERILATOR_SKIP_WARNINGS) ${TBFILES} --top-module tb_top \ - -exe $(TB_VERILATOR_SRCS) --autoflush --timing $(VERILATOR_DEBUG) $(VERILATOR_COVERAGE) + -exe $(TB_VERILATOR_SRCS) --autoflush --timing $(VERILATOR_DEBUG) $(VERILATOR_COVERAGE) -fno-table cp ${RV_ROOT}/testbench/test_tb_top.cpp obj_dir/ $(MAKE) -e -C obj_dir/ -f Vtb_top.mk $(VERILATOR_MAKE_FLAGS) touch verilator-build diff --git a/tools/riscv-dv/Makefile b/tools/riscv-dv/Makefile index 7ba8abac2a5..70c00c61c0a 100644 --- a/tools/riscv-dv/Makefile +++ b/tools/riscv-dv/Makefile @@ -118,7 +118,7 @@ $(WORK_DIR)/verilator/Vtb_top.mk: $(WORK_DIR)/defines.h $(VERILATOR) --cc -CFLAGS $(VERILATOR_CFLAGS) $(VERILATOR_INC) \ $(HDL_FILES) -f $(RV_ROOT)/testbench/flist --top-module tb_top \ -exe $(VERILATOR_EXE) -Wno-WIDTH -Wno-UNOPTFLAT $(VERILATOR_NOIMPLICIT) --autoflush \ - --timing $(VERILATOR_COVERAGE) \ + --timing $(VERILATOR_COVERAGE) -fno-table \ -Mdir $(WORK_DIR)/verilator $(WORK_DIR)/verilator/Vtb_top: $(WORK_DIR)/verilator/Vtb_top.mk From bd93c80994727ec54539f41c62bb003f5f62bd9f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ob=C5=82onczek?= Date: Tue, 2 Jul 2024 19:03:34 +0200 Subject: [PATCH 05/11] Add tests for exceptions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Obłonczek Co-authored-by: Karol Gugala --- .github/workflows/test-regression.yml | 6 +- testbench/asm/common.s | 75 +++++++++++++++ testbench/asm/dbus_nonblocking_load_error.s | 16 ++++ testbench/asm/dbus_store_error.s | 18 ++++ .../asm/dside_access_across_region_boundary.s | 22 +++++ .../dside_access_region_prediction_error.s | 25 +++++ ...core_local_access_unmapped_address_error.s | 22 +++++ testbench/asm/dside_pic_access_error.s | 22 +++++ ...aligned_access_to_non_idempotent_address.s | 24 +++++ testbench/asm/ebreak_ecall.s | 18 ++++ testbench/asm/illegal_instruction.s | 11 +++ testbench/asm/internal_timer_ints.s | 28 ++++++ testbench/asm/interrupts.ld | 1 + .../iside_core_local_unmapped_address_error.s | 13 +++ testbench/asm/iside_fetch_precise_bus_error.s | 16 ++++ testbench/asm/lsu_trigger_hit.s | 18 ++++ testbench/asm/machine_external_ints.s | 30 ++++++ testbench/asm/machine_external_vec_ints.s | 90 ++++++++++++++++++ testbench/asm/nmi_pin_assertion.s | 14 +++ testbench/asm/tb.h | 9 ++ testbench/tb_top.sv | 95 +++++++++++++++++-- tools/Makefile | 2 +- 22 files changed, 565 insertions(+), 10 deletions(-) create mode 100644 testbench/asm/common.s create mode 100644 testbench/asm/dbus_nonblocking_load_error.s create mode 100644 testbench/asm/dbus_store_error.s create mode 100644 testbench/asm/dside_access_across_region_boundary.s create mode 100644 testbench/asm/dside_access_region_prediction_error.s create mode 100644 testbench/asm/dside_core_local_access_unmapped_address_error.s create mode 100644 testbench/asm/dside_pic_access_error.s create mode 100644 testbench/asm/dside_size_misaligned_access_to_non_idempotent_address.s create mode 100644 testbench/asm/ebreak_ecall.s create mode 100644 testbench/asm/illegal_instruction.s create mode 100644 testbench/asm/internal_timer_ints.s create mode 120000 testbench/asm/interrupts.ld create mode 100644 testbench/asm/iside_core_local_unmapped_address_error.s create mode 100644 testbench/asm/iside_fetch_precise_bus_error.s create mode 100644 testbench/asm/lsu_trigger_hit.s create mode 100644 testbench/asm/machine_external_ints.s create mode 100644 testbench/asm/machine_external_vec_ints.s create mode 100644 testbench/asm/nmi_pin_assertion.s create mode 100644 testbench/asm/tb.h diff --git a/.github/workflows/test-regression.yml b/.github/workflows/test-regression.yml index 0264c2d0bd5..d350d747de5 100644 --- a/.github/workflows/test-regression.yml +++ b/.github/workflows/test-regression.yml @@ -13,7 +13,11 @@ jobs: matrix: bus: ["axi", "ahb"] test: ["hello_world", "hello_world_dccm", "hello_world_iccm", "cmark", "cmark_dccm", "cmark_iccm", "dhry", "ecc", - "csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp"] + "csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp", + "machine_external_ints", "dbus_store_error", "lsu_trigger_hit", "machine_external_vec_ints", "dside_pic_access_error", + "iside_fetch_precise_bus_error", "dside_access_region_prediction_error", "cmark", "iside_core_local_unmapped_address_error", + "dside_access_across_region_boundary", "nmi_pin_assertion", "dside_size_misaligned_access_to_non_idempotent_address", + "dside_core_local_access_unmapped_address_error", "dbus_nonblocking_load_error", "internal_timer_ints", "ebreak_ecall", "illegal_instruction"] coverage: ["all", "branch", "toggle"] #TODO: add functional coverage priv: ["0", "1"] exclude: diff --git a/testbench/asm/common.s b/testbench/asm/common.s new file mode 100644 index 00000000000..b7d4308c884 --- /dev/null +++ b/testbench/asm/common.s @@ -0,0 +1,75 @@ +#include "defines.h" +#include "tb.h" + +.section .text +.global _start +_start: + // Clear minstret + csrw minstret, zero + csrw minstreth, zero + + // Enable Caches in MRAC + li x2, 0x5f555555 + csrw 0x7c0, x2 + + // global interrupt enable + csrr x2, mstatus + ori x2, x2, 0x8 + csrw mstatus, x2 + + // set up mtvec + la x2, exc_int_handler + csrw mtvec, x2 + + // Set up NMI handler address + li x3, STDOUT + ori x2, x2, LOAD_NMI_ADDR + sw x2, 0(x3) + + j main + +// Write 0xff to STDOUT for TB to terminate test. +_finish: + li x3, STDOUT + addi x5, x0, 0xff + sb x5, 0(x3) + beq x0, x0, _finish +.rept 100 + nop +.endr + +// handler must be aligned to 256 bytes since it has to fit +// in the upper 24 bits of nmi handler address set testbench command +.balign 256 +exc_int_handler: + // disable all interrupt sources + csrw mie, zero + // reenable signaling of NMIs for subsequent NMIs + csrw 0xBC0, zero // mdeau + // compare CSRs with expected values + csrr x2, mcause + bne x2, x4, fail + csrr x2, 0x7FF // mscause + bne x2, x5, fail + // set mepc to return from the test once we leave the handler + la x2, ok + csrw mepc, x2 + mret + +// used for making sure we fail if we didn't jump to the exception/NMI handler +fail_if_not_serviced: +.rept 15 + nop +.endr + // fail if interrupt didn't get serviced + j fail + +fail: + // write 0x01 to STDOUT for TB to fail the test + li x3, STDOUT + addi x5, x0, 0x01 + sb x5, 0(x3) + j fail + +ok: + ret \ No newline at end of file diff --git a/testbench/asm/dbus_nonblocking_load_error.s b/testbench/asm/dbus_nonblocking_load_error.s new file mode 100644 index 00000000000..0284a3b7f8b --- /dev/null +++ b/testbench/asm/dbus_nonblocking_load_error.s @@ -0,0 +1,16 @@ +#include "common.s" + +dbus_nonblocking_load_error: + li x4, 0xF0000001 + li x5, 0x0 + // trigger bus fault at next load + li x2, TRIGGER_DBUS_FAULT + li x3, STDOUT + sw x2, 0(x3) + // bus fault is triggered on this instruction + lw x2, 0(zero) + j fail_if_not_serviced + +main: + call dbus_nonblocking_load_error + j _finish \ No newline at end of file diff --git a/testbench/asm/dbus_store_error.s b/testbench/asm/dbus_store_error.s new file mode 100644 index 00000000000..31bea2b11cc --- /dev/null +++ b/testbench/asm/dbus_store_error.s @@ -0,0 +1,18 @@ +#include "common.s" + +dbus_store_error: + li x4, 0xF0000000 + li x5, 0x0 + // address of some data that resides in memory (and not in iccm/dccm) + lw x6, _start + // trigger bus fault at next store + li x2, TRIGGER_DBUS_FAULT + li x3, STDOUT + sw x2, 0(x3) + // bus fault is triggered on this instruction + sw x2, 0(x6) + j fail_if_not_serviced + +main: + call dbus_store_error + j _finish diff --git a/testbench/asm/dside_access_across_region_boundary.s b/testbench/asm/dside_access_across_region_boundary.s new file mode 100644 index 00000000000..cdb50dc24ff --- /dev/null +++ b/testbench/asm/dside_access_across_region_boundary.s @@ -0,0 +1,22 @@ +#include "common.s" + +dside_load_across_region_boundary: + li x4, 0x4 + li x5, 0x2 + // load from across region boundary + li x2, 0xe0000000-2 + lw x2, 0(x2) + j fail_if_not_serviced + +dside_store_across_region_boundary: + li x4, 0x6 + li x5, 0x2 + // store across region boundary + li x2, 0xe0000000-2 + sw x2, 0(x2) + j fail_if_not_serviced + +main: + call dside_load_across_region_boundary + call dside_store_across_region_boundary + j _finish \ No newline at end of file diff --git a/testbench/asm/dside_access_region_prediction_error.s b/testbench/asm/dside_access_region_prediction_error.s new file mode 100644 index 00000000000..c2789988daa --- /dev/null +++ b/testbench/asm/dside_access_region_prediction_error.s @@ -0,0 +1,25 @@ +#include "common.s" + +dside_load_region_prediction_error: + li x4, 0x5 + li x5, 0x5 + // this assumes that RV_PIC_BASE_ADDR is as high in the region + // as realistically allowed, e.g. 0xffff8000, this allows us + // to construct an address that will overflow to another region + // when offset is used in an 'lw' instruction: 0xfffffffc + 0x4 + li x2, RV_PIC_BASE_ADDR + 0x7ffc + lw x2, 0x4(x2) + j fail_if_not_serviced + +dside_store_region_prediction_error: + li x4, 0x7 + li x5, 0x5 + // same as in load region prediction error + li x2, RV_PIC_BASE_ADDR + 0x7ffc + sw x2, 0x4(x2) + j fail_if_not_serviced + +main: + call dside_load_region_prediction_error + call dside_store_region_prediction_error + j _finish \ No newline at end of file diff --git a/testbench/asm/dside_core_local_access_unmapped_address_error.s b/testbench/asm/dside_core_local_access_unmapped_address_error.s new file mode 100644 index 00000000000..cc18dfc515c --- /dev/null +++ b/testbench/asm/dside_core_local_access_unmapped_address_error.s @@ -0,0 +1,22 @@ +#include "common.s" + +dside_core_local_load_unmapped_address_error: + li x4, 0x5 + li x5, 0x2 + // load from DCCM upper boundary (this also triggers unmapped address error) + li x2, RV_DCCM_EADR - 1 + lw x2, 0(x2) + j fail_if_not_serviced + +dside_core_local_store_unmapped_address_error: + li x4, 0x7 + li x5, 0x2 + // store to DCCM upper boundary (this also triggers unmapped address error) + li x2, RV_DCCM_EADR - 1 + sw x2, 0(x2) + j fail_if_not_serviced + +main: + call dside_core_local_load_unmapped_address_error + call dside_core_local_store_unmapped_address_error + j _finish \ No newline at end of file diff --git a/testbench/asm/dside_pic_access_error.s b/testbench/asm/dside_pic_access_error.s new file mode 100644 index 00000000000..e1bf17e77de --- /dev/null +++ b/testbench/asm/dside_pic_access_error.s @@ -0,0 +1,22 @@ +#include "common.s" + +dside_pic_load_access_error: + li x4, 0x5 + li x5, 0x6 + // perform not word-sized load from PIC + li x2, RV_PIC_BASE_ADDR + lb x2, 0(x2) + j fail_if_not_serviced + +dside_pic_store_access_error: + li x4, 0x7 + li x5, 0x6 + // perform not word-sized store to PIC + li x2, RV_PIC_BASE_ADDR + sb x2, 0(x2) + j fail_if_not_serviced + +main: + call dside_pic_load_access_error + call dside_pic_store_access_error + j _finish \ No newline at end of file diff --git a/testbench/asm/dside_size_misaligned_access_to_non_idempotent_address.s b/testbench/asm/dside_size_misaligned_access_to_non_idempotent_address.s new file mode 100644 index 00000000000..a39be24b31e --- /dev/null +++ b/testbench/asm/dside_size_misaligned_access_to_non_idempotent_address.s @@ -0,0 +1,24 @@ +#include "common.s" + +dside_size_misaligned_load_to_non_idempotent_address: + li x4, 0x4 + li x5, 0x1 + // load from across non-idempotent address (with side effects) + // we take advantage of the fact that STDOUT is such an address + li x2, STDOUT-2 + lw x2, 0(x2) + j fail_if_not_serviced + +dside_size_misaligned_store_to_non_idempotent_address: + li x4, 0x6 + li x5, 0x1 + // store to across non-idempotent address (with side effect) + // we take advantage of the fact that STDOUT is such an address + li x2, STDOUT-2 + sw x2, 0(x2) + j fail_if_not_serviced + +main: + call dside_size_misaligned_load_to_non_idempotent_address + call dside_size_misaligned_store_to_non_idempotent_address + j _finish \ No newline at end of file diff --git a/testbench/asm/ebreak_ecall.s b/testbench/asm/ebreak_ecall.s new file mode 100644 index 00000000000..b76870666ad --- /dev/null +++ b/testbench/asm/ebreak_ecall.s @@ -0,0 +1,18 @@ +#include "common.s" + +breakpoint_ebreak: + li x4, 0x3 + li x5, 0x2 + ebreak + j fail_if_not_serviced + +environment_call_from_m_mode: + li x4, 0xB + li x5, 0x0 + ecall + j fail_if_not_serviced + +main: + call breakpoint_ebreak + call environment_call_from_m_mode + j _finish \ No newline at end of file diff --git a/testbench/asm/illegal_instruction.s b/testbench/asm/illegal_instruction.s new file mode 100644 index 00000000000..f6ad7738e38 --- /dev/null +++ b/testbench/asm/illegal_instruction.s @@ -0,0 +1,11 @@ +#include "common.s" + +illegal_instruction: + li x4, 0x2 + li x5, 0x0 + .word 0 + j fail_if_not_serviced + +main: + call illegal_instruction + j _finish \ No newline at end of file diff --git a/testbench/asm/internal_timer_ints.s b/testbench/asm/internal_timer_ints.s new file mode 100644 index 00000000000..2f57843dad5 --- /dev/null +++ b/testbench/asm/internal_timer_ints.s @@ -0,0 +1,28 @@ +#include "common.s" + +machine_internal_timer0_local_interrupt: + li x4, 0x8000001d + li x5, 0x0 + csrw 0x7D4, 0x0 // disable incrementing timer0 + csrw 0x7D2, 0x0 // reset timer0 count value + csrw 0x7D3, 0x8 // set timer0 threshold to 8 + li x2, 0x20000000 + csrw mie, x2 // enable timer0 local interrupt + csrw 0x7D4, 0x1 // reenable incrementing timer0 + j fail_if_not_serviced + +machine_internal_timer1_local_interrupt: + li x4, 0x8000001c + li x5, 0x0 + csrw 0x7D7, 0x0 // disable incrementing timer0 + csrw 0x7D5, 0x0 // reset timer0 count value + csrw 0x7D6, 0x8 // set timer0 threshold to 8 + li x2, 0x10000000 + csrw mie, x2 // enable timer0 local interrupt + csrw 0x7D7, 0x1 // reenable incrementing timer0 + j fail_if_not_serviced + +main: + call machine_internal_timer0_local_interrupt + call machine_internal_timer1_local_interrupt + j _finish \ No newline at end of file diff --git a/testbench/asm/interrupts.ld b/testbench/asm/interrupts.ld new file mode 120000 index 00000000000..0d4df6a4a48 --- /dev/null +++ b/testbench/asm/interrupts.ld @@ -0,0 +1 @@ +hello_world.ld \ No newline at end of file diff --git a/testbench/asm/iside_core_local_unmapped_address_error.s b/testbench/asm/iside_core_local_unmapped_address_error.s new file mode 100644 index 00000000000..d66a3e5b26b --- /dev/null +++ b/testbench/asm/iside_core_local_unmapped_address_error.s @@ -0,0 +1,13 @@ +#include "common.s" + +iside_core_local_unmapped_address_error: + li x4, 0x1 + li x5, 0x2 + // jump to address that's only halfway inside ICCM + li x2, 0xee000000-2 + jalr x2, 0(x2) + j fail_if_not_serviced + +main: + call iside_core_local_unmapped_address_error + j _finish \ No newline at end of file diff --git a/testbench/asm/iside_fetch_precise_bus_error.s b/testbench/asm/iside_fetch_precise_bus_error.s new file mode 100644 index 00000000000..a7a6287940f --- /dev/null +++ b/testbench/asm/iside_fetch_precise_bus_error.s @@ -0,0 +1,16 @@ +#include "common.s" + +iside_fetch_precise_bus_error: + li x4, 0x1 + li x5, 0x9 + li x2, TRIGGER_IBUS_FAULT + li x3, STDOUT + sw x2, 0(x3) + // ibus fault is triggered on subsequent instruction - force refetch from memory + // since testbench relies on bus transaction happening to trigger bus error + fence.i + j fail_if_not_serviced + +main: + call iside_fetch_precise_bus_error + j _finish \ No newline at end of file diff --git a/testbench/asm/lsu_trigger_hit.s b/testbench/asm/lsu_trigger_hit.s new file mode 100644 index 00000000000..a354a9d3502 --- /dev/null +++ b/testbench/asm/lsu_trigger_hit.s @@ -0,0 +1,18 @@ +#include "common.s" + +lsu_trigger_hit: + la x4, 0x3 + la x5, 0x1 + // set up address to trigger on + li x2, 0xdeadbeef + csrw tdata2, x2 + // enable trigger in M-mode, fire on address of a load + li x3, 0x41 + csrw mcontrol, x3 + // load from that address + lw x2, 0(x2) + j fail_if_not_serviced + +main: + call lsu_trigger_hit + j _finish \ No newline at end of file diff --git a/testbench/asm/machine_external_ints.s b/testbench/asm/machine_external_ints.s new file mode 100644 index 00000000000..31a2fdd8057 --- /dev/null +++ b/testbench/asm/machine_external_ints.s @@ -0,0 +1,30 @@ +#include "common.s" + +machine_software_interrupt: + la x4, 0x80000003 + li x5, 0x0 + // enable software interrupt + li x2, 0x8 + csrw mie, x2 + // trigger soft interrupt + li x2, TRIGGER_SOFT_INT + li x3, STDOUT + sw x2, 0(x3) + j fail_if_not_serviced + +machine_timer_interrupt: + la x4, 0x80000007 + li x5, 0x0 + // enable machine timer interrupt + li x2, 0x80 + csrw mie, x2 + // trigger timer interrupt + li x2, TRIGGER_TIMER_INT + li x3, STDOUT + sw x2, 0(x3) + j fail_if_not_serviced + +main: + call machine_software_interrupt + call machine_timer_interrupt + j _finish \ No newline at end of file diff --git a/testbench/asm/machine_external_vec_ints.s b/testbench/asm/machine_external_vec_ints.s new file mode 100644 index 00000000000..9b2817fdd26 --- /dev/null +++ b/testbench/asm/machine_external_vec_ints.s @@ -0,0 +1,90 @@ +#include "common.s" + +enable_ext_int1: + // set up gateway configuration - level triggered active high + li x2, 0x0 + li x3, (RV_PIC_BASE_ADDR + 0x4004) // meigwctrl1 + sw x2, 0(x3) + // clear interrupt bit for gateway + li x3, (RV_PIC_BASE_ADDR + 0x5004) // meigwclr1 + sw zero, 0(x3) + // set up priority level + li x3, (RV_PIC_BASE_ADDR + 0x4) // meipl1 + li x2, 0x1 + sw x2, 0(x3) + + // interrupt priority threshold and priority nesting are + // already initialized at correct value and we're only + // testing one interrupt so we don't bother setting them explicitly + + // enable external interrupt 1 + li x3, (RV_PIC_BASE_ADDR + 0x2004) + li x2, 0x1 + sw x2, 0(x3) + // enable external interrupts + li x2, 0x800 + csrw mie, x2 + ret + +machine_external_interrupt: + la x4, 0x8000000b + la x5, 0x0 + // Set up external interrupt vector table at the beginning of DCCM + la x2, exc_int_handler + li x3, RV_DCCM_SADR + sw x2, 0(x3) + // set up base interrupt vector table address + csrw 0xBC8, x3 // meivt + + mv x6, x1 // save return address + call enable_ext_int1 + mv x1, x6 // restore return address + + li x2, TRIGGER_EXT_INT1 + li x3, STDOUT + sw x2, 0(x3) + j fail_if_not_serviced + +fast_interrupt_dccm_region_access_error: + la x4, 0xF0001001 + la x5, 0x0 + // set up base interrupt vector table address at some address + // *not* in DCCM but in DCCM region + // assume somewhat optimistically that DCCM isn't allocated + // at the end of its region so RV_DCCM_EADR + 1 is still in DCCM region + li x2, RV_DCCM_EADR + 1 + csrw 0xBC8, x2 // meivt + + mv x6, x1 // save return address + call enable_ext_int1 + mv x1, x6 // restore return address + + // trigger external interrupt 1 + li x2, TRIGGER_EXT_INT1 + li x3, STDOUT + sw x2, 0(x3) + j fail_if_not_serviced + +fast_interrupt_non_dccm_region: + la x4, 0xF0001002 + la x5, 0x0 + // set up interrupt vector table address at an address that's + // not in DCCM region + li x2, ((RV_DCCM_REGION + 1) % 0x10) << 28 + csrw 0xBC8, x2 // meivt + + mv x6, x1 // save return address + call enable_ext_int1 + mv x1, x6 // restore return address + + // trigger external interrupt 1 + li x2, TRIGGER_EXT_INT1 + li x3, STDOUT + sw x2, 0(x3) + j fail_if_not_serviced + +main: + call machine_external_interrupt + call fast_interrupt_dccm_region_access_error + call fast_interrupt_non_dccm_region + j _finish \ No newline at end of file diff --git a/testbench/asm/nmi_pin_assertion.s b/testbench/asm/nmi_pin_assertion.s new file mode 100644 index 00000000000..31c524d7f76 --- /dev/null +++ b/testbench/asm/nmi_pin_assertion.s @@ -0,0 +1,14 @@ +#include "common.s" + +nmi_pin_assertion: + li x4, 0x0 + li x5, 0x0 + // trigger NMI + li x2, TRIGGER_NMI + li x3, STDOUT + sw x2, 0(x3) + j fail_if_not_serviced + +main: + call nmi_pin_assertion + j _finish \ No newline at end of file diff --git a/testbench/asm/tb.h b/testbench/asm/tb.h new file mode 100644 index 00000000000..38ac5deed16 --- /dev/null +++ b/testbench/asm/tb.h @@ -0,0 +1,9 @@ +#define STDOUT 0xd0580000 + +#define TRIGGER_NMI 0x80 +#define LOAD_NMI_ADDR 0x81 +#define TRIGGER_DBUS_FAULT 0x82 +#define TRIGGER_IBUS_FAULT 0x83 +#define TRIGGER_SOFT_INT 0x84 +#define TRIGGER_TIMER_INT 0x85 +#define TRIGGER_EXT_INT1 0x86 \ No newline at end of file diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index d74d8bbeded..4ae69f8cb76 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -51,6 +51,8 @@ module tb_top logic [31:0] nmi_vector; logic [31:1] jtag_id; + logic [pt.PIC_TOTAL_INT:1] extintsrc_req; + logic [31:0] ic_haddr ; logic [2:0] ic_hburst ; logic ic_hmastlock ; @@ -143,6 +145,8 @@ module tb_top wire dma_hready_out; int commit_count; + logic [3:0] nmi_assert_int; + logic wb_valid; logic [4:0] wb_dest; logic [31:0] wb_data; @@ -692,12 +696,12 @@ module tb_top `define DEC rvtop_wrapper.rvtop.veer.dec `ifdef RV_BUILD_AXI4 - assign mailbox_write = lmem.awvalid && lmem.awaddr == mem_mailbox && rst_l; - assign mailbox_data = lmem.wdata; + assign mailbox_write = lmem.awvalid && lmem.awaddr == mem_mailbox && rst_l; + assign mailbox_data = lmem.wdata; `endif `ifdef RV_BUILD_AHB_LITE - assign mailbox_write = lmem.write && lmem.laddr == mem_mailbox && rst_l; - assign mailbox_data = lmem.HWDATA; + assign mailbox_write = lmem.write && lmem.laddr == mem_mailbox && rst_l; + assign mailbox_data = lmem.HWDATA; `endif assign mailbox_data_val = mailbox_data[7:0] > 8'h5 && mailbox_data[7:0] < 8'h7f; @@ -705,6 +709,11 @@ module tb_top parameter MAX_CYCLES = 2_000_000; integer fd, tp, el; + logic next_dbus_error; + logic next_ibus_error; + logic [1:0] lsu_axi_rresp_override; + logic [1:0] lsu_axi_bresp_override; + logic [1:0] ifu_axi_rresp_override; always @(negedge core_clk) begin cycleCnt <= cycleCnt+1; @@ -791,7 +800,73 @@ module tb_top $display("TEST_FAILED"); $finish; end + + // Custom test commands + // Available commands (that can be written into address mem_mailbox_testcmd) are: + // 8'h80 - trigger NMI + // 8'h81 - set NMI handler address (mailbox_data[31:8] is the address of a handler, + // i.e. it must be 256 byte-aligned) + // 8'h82 - trigger data bus error on the next load/store + nmi_assert_int <= nmi_assert_int >> 1; + soft_int <= 0; + timer_int <= 0; + extintsrc_req[1] <= 0; + if (mailbox_write && mailbox_data[7:0] == 8'h80 && nmi_assert_int == 4'b0000) begin + nmi_assert_int <= 4'b1111; + end + else if (mailbox_write && mailbox_data[7:0] == 8'h81) begin + // NMI handler address is in the upper 24 bits of mailbox data + nmi_vector[31:1] <= {mailbox_data[31:8], 7'h00}; + end + else if (mailbox_write && mailbox_data[7:0] == 8'h84) begin + soft_int <= 1; + end + else if (mailbox_write && mailbox_data[7:0] == 8'h85) begin + timer_int <= 1; + end + else if (mailbox_write && mailbox_data[7:0] == 8'h86) begin + extintsrc_req[1] <= 1; + end + end + + `ifdef RV_BUILD_AXI4 + // this needs to be a separate block due to sensitivity to other signals + always @(negedge core_clk or lsu_axi_bvalid or lsu_axi_rvalid or ifu_axi_rvalid or ifu_axi_rid) begin + if (mailbox_write && mailbox_data[7:0] == 8'h82) + // wait for current transaction that to complete to not trigger error on it + @(negedge lsu_axi_bvalid) next_dbus_error <= 1; + if (mailbox_write && mailbox_data[7:0] == 8'h83) + @(negedge ifu_axi_rvalid or ifu_axi_rid) next_ibus_error <= 1; + // turn off forcing dbus error after a transaction + if (next_dbus_error) + @(negedge lsu_axi_bvalid or negedge lsu_axi_rvalid) next_dbus_error <= 0; + if (next_ibus_error) + @(negedge ifu_axi_rvalid or ifu_axi_rid) next_ibus_error <= 0; end + `endif + + always_comb begin + `ifdef RV_BUILD_AXI4 + lsu_axi_rresp_override = lsu_axi_rresp; + lsu_axi_bresp_override = lsu_axi_bresp; + ifu_axi_rresp_override = ifu_axi_rresp; + if (next_dbus_error) begin + // force slave bus error + if (lsu_axi_rvalid) + lsu_axi_rresp_override = 2'b10; + if (lsu_axi_bvalid) + lsu_axi_bresp_override = 2'b10; + end + if (next_ibus_error) begin + if (ifu_axi_rvalid) + ifu_axi_rresp_override = 2'b10; + end + `endif + end + + // nmi_int must be asserted for at least two clock cycles and then deasserted for + // at least two clock cycles - see RISC-V VeeR EL2 Programmer's Reference Manual section 2.16 + assign nmi_int = |{nmi_assert_int[3:2]}; // trace monitor always @(posedge core_clk) begin @@ -871,6 +946,10 @@ module tb_top jtag_id[11:1] = 11'h45; reset_vector = `RV_RESET_VEC; nmi_vector = 32'hee000000; + nmi_int = 0; + soft_int = 0; + timer_int = 0; + extintsrc_req = 0; $readmemh("program.hex", lmem.mem); $readmemh("program.hex", imem.mem); @@ -991,7 +1070,7 @@ veer_wrapper rvtop_wrapper ( .lsu_axi_bvalid (lsu_axi_bvalid), .lsu_axi_bready (lsu_axi_bready), - .lsu_axi_bresp (lsu_axi_bresp), + .lsu_axi_bresp (lsu_axi_bresp_override), .lsu_axi_bid (lsu_axi_bid), @@ -1012,7 +1091,7 @@ veer_wrapper rvtop_wrapper ( .lsu_axi_rready (lsu_axi_rready), .lsu_axi_rid (lsu_axi_rid), .lsu_axi_rdata (lsu_axi_rdata), - .lsu_axi_rresp (lsu_axi_rresp), + .lsu_axi_rresp (lsu_axi_rresp_override), .lsu_axi_rlast (lsu_axi_rlast), //-------------------------- IFU AXI signals-------------------------- @@ -1058,7 +1137,7 @@ veer_wrapper rvtop_wrapper ( .ifu_axi_rready (ifu_axi_rready), .ifu_axi_rid (ifu_axi_rid), .ifu_axi_rdata (ifu_axi_rdata), - .ifu_axi_rresp (ifu_axi_rresp), + .ifu_axi_rresp (ifu_axi_rresp_override), .ifu_axi_rlast (ifu_axi_rlast), //-------------------------- SB AXI signals-------------------------- @@ -1149,7 +1228,6 @@ veer_wrapper rvtop_wrapper ( .dma_axi_rlast (dma_axi_rlast), `endif .timer_int ( timer_int ), - .soft_int ( soft_int ), .extintsrc_req ( ext_int ), .lsu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface @@ -1218,6 +1296,7 @@ veer_wrapper rvtop_wrapper ( .ic_data_ext_in_pkt ('0), .ic_tag_ext_in_pkt ('0), + .soft_int (soft_int), .core_id ('0), .scan_mode ( 1'b0 ), // To enable scan mode .mbist_mode ( 1'b0 ), // to enable mbist diff --git a/tools/Makefile b/tools/Makefile index 09e7924a080..2936e006fb9 100755 --- a/tools/Makefile +++ b/tools/Makefile @@ -159,7 +159,7 @@ VERILATOR_MAKE_FLAGS = OPT_FAST="-Os" all: clean verilator clean: - rm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* *.map snapshots veer* \ + rm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* *.map snapshots \ verilator* *.exe obj* *.o *.sym ucli.key vc_hdrs.h csrc *.csv work \ dataset.asdb library.cfg vsimsa.cfg riviera-build wave.asdb From 344e6ae364c6a4350487e2bc63b90b759d3179f2 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Tue, 8 Oct 2024 23:02:38 +0200 Subject: [PATCH 06/11] CI: split regression tests into two flows This way matrix size is below 256 Also limit exceptions tests to AXI and M mode Signed-off-by: Karol Gugala Co-authored-by: Wojciech Sipak --- .github/workflows/ci.yml | 4 + .../workflows/test-regression-exceptions.yml | 102 ++++++++++++++++++ .github/workflows/test-regression.yml | 6 +- 3 files changed, 107 insertions(+), 5 deletions(-) create mode 100644 .github/workflows/test-regression-exceptions.yml diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 0b05b76b673..6da75337aae 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -12,6 +12,10 @@ jobs: name: Test-Regression uses: ./.github/workflows/test-regression.yml + Test-Exceptions-Regression: + name: Test-Exceptions-Regression + uses: ./.github/workflows/test-regression-exceptions.yml + Test-Verification: name: Test-Verification uses: ./.github/workflows/test-verification.yml diff --git a/.github/workflows/test-regression-exceptions.yml b/.github/workflows/test-regression-exceptions.yml new file mode 100644 index 00000000000..9b7d21393cc --- /dev/null +++ b/.github/workflows/test-regression-exceptions.yml @@ -0,0 +1,102 @@ +name: Regression exceptions tests + +on: + workflow_call: + +jobs: + + regression-tests: + name: Regression exceptions tests + runs-on: ubuntu-latest + container: ghcr.io/antmicro/cores-veer-el2:latest + strategy: + matrix: + bus: ["axi"] + test: ["machine_external_ints", "dbus_store_error", "lsu_trigger_hit", "machine_external_vec_ints", "dside_pic_access_error", + "iside_fetch_precise_bus_error", "dside_access_region_prediction_error", "cmark", "iside_core_local_unmapped_address_error", + "dside_access_across_region_boundary", "nmi_pin_assertion", "dside_size_misaligned_access_to_non_idempotent_address", + "dside_core_local_access_unmapped_address_error", "dbus_nonblocking_load_error", "internal_timer_ints", "ebreak_ecall", "illegal_instruction"] + coverage: ["all", "branch", "toggle"] #TODO: add functional coverage + priv: ["0"] + env: + DEBIAN_FRONTEND: "noninteractive" + CCACHE_DIR: "/opt/regression/.cache/" + + steps: + - name: Install utils + run: | + sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ + git python3 python3-pip build-essential ninja-build cpanminus ccache \ + gcc-riscv64-unknown-elf + sudo cpanm Bit::Vector + pip3 install meson + + - name: Setup Cache Metadata + id: cache_metadata + run: | + date=$(date +"%Y_%m_%d") + time=$(date +"%Y%m%d_%H%M%S_%N") + cache_test_restore_key=${{ matrix.test }}_${{ matrix.coverage }}_ + cache_test_key=${cache_test_restore_key}${time} + + echo "date=$date" | tee -a "$GITHUB_ENV" + echo "time=$time" | tee -a "$GITHUB_ENV" + echo "cache_test_restore_key=$cache_test_restore_key" | tee -a "$GITHUB_ENV" + echo "cache_test_key=$cache_test_key" | tee -a "$GITHUB_ENV" + + - name: Setup tests cache + uses: actions/cache@v3 + id: cache-test-setup + with: + path: | + ${{ env.CCACHE_DIR }} + key: ${{ env.cache_test_key }} + restore-keys: ${{ env.cache_test_restore_key }} + + - name: Setup repository + uses: actions/checkout@v3 + with: + submodules: recursive + + - name: install SiteSpawner package + shell: bash + run: | + python3 -m venv .venv + .venv/bin/python3 -m pip install tools/SiteSpawner + source .venv/bin/activate + echo "PATH=$PATH" >> $GITHUB_ENV + python3 -m pip install tools/SiteSpawner + + - name: Setup environment + shell: bash + run: | + echo "/opt/verilator/bin" >> $GITHUB_PATH + RV_ROOT=`pwd` + echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV + PYTHONUNBUFFERED=1 + echo "PYTHONUNBUFFERED=$PYTHONUNBUFFERED" >> $GITHUB_ENV + TEST_PATH=$RV_ROOT/test_results + echo "TEST_PATH=$TEST_PATH" >> $GITHUB_ENV + + - name: Run tests + shell: bash + run: | + export PATH=/opt/verilator/bin:$PATH + export RV_ROOT=`pwd` + .github/scripts/run_regression_test.sh $TEST_PATH ${{ matrix.bus }} ${{ matrix.test}} ${{ matrix.coverage }} ${{ matrix.priv }} + + - name: Prepare coverage data + shell: bash + run: | + source .venv/bin/activate + sis -d convert --dat-dir ${TEST_PATH}/ + mkdir -p results + mv ${TEST_PATH}/coverage.info \ + results/coverage_${{ matrix.bus }}_${{ matrix.test }}_${{ matrix.coverage }}.info + + - name: Pack artifacts + if: always() + uses: actions/upload-artifact@v3 + with: + name: regression_tests_coverage_data + path: results/*.info diff --git a/.github/workflows/test-regression.yml b/.github/workflows/test-regression.yml index d350d747de5..0264c2d0bd5 100644 --- a/.github/workflows/test-regression.yml +++ b/.github/workflows/test-regression.yml @@ -13,11 +13,7 @@ jobs: matrix: bus: ["axi", "ahb"] test: ["hello_world", "hello_world_dccm", "hello_world_iccm", "cmark", "cmark_dccm", "cmark_iccm", "dhry", "ecc", - "csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp", - "machine_external_ints", "dbus_store_error", "lsu_trigger_hit", "machine_external_vec_ints", "dside_pic_access_error", - "iside_fetch_precise_bus_error", "dside_access_region_prediction_error", "cmark", "iside_core_local_unmapped_address_error", - "dside_access_across_region_boundary", "nmi_pin_assertion", "dside_size_misaligned_access_to_non_idempotent_address", - "dside_core_local_access_unmapped_address_error", "dbus_nonblocking_load_error", "internal_timer_ints", "ebreak_ecall", "illegal_instruction"] + "csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp"] coverage: ["all", "branch", "toggle"] #TODO: add functional coverage priv: ["0", "1"] exclude: From 83f4a8ece47690c9ea14627b4bbca5c10c2eac91 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 3 Oct 2024 14:43:14 +0200 Subject: [PATCH 07/11] exclude signals tied to const values from coverage Signed-off-by: Wojciech Sipak Co-authored-by: Karol Gugala Co-authored-by: Tomasz Michalak Co-authored-by: Robert Szczepanski --- design/dbg/el2_dbg.sv | 27 ++++++++ design/el2_veer.sv | 87 ++++++++++++++++++++++++++ design/el2_veer_wrapper.sv | 102 +++++++++++++++++++++++++++++++ design/ifu/el2_ifu.sv | 9 +++ design/ifu/el2_ifu_mem_ctl.sv | 13 ++++ design/lib/ahb_to_axi4.sv | 35 ++++++++++- design/lib/axi4_to_ahb.sv | 5 +- design/lsu/el2_lsu.sv | 24 ++++++++ design/lsu/el2_lsu_bus_buffer.sv | 24 ++++++++ design/lsu/el2_lsu_bus_intf.sv | 24 ++++++++ 10 files changed, 348 insertions(+), 2 deletions(-) diff --git a/design/dbg/el2_dbg.sv b/design/dbg/el2_dbg.sv index d7daec33016..67f424047e6 100644 --- a/design/dbg/el2_dbg.sv +++ b/design/dbg/el2_dbg.sv @@ -64,16 +64,25 @@ import el2_pkg::*; // AXI Write Channels output logic sb_axi_awvalid, input logic sb_axi_awready, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid, + /*verilator coverage_on*/ output logic [31:0] sb_axi_awaddr, output logic [3:0] sb_axi_awregion, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [7:0] sb_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] sb_axi_awsize, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [1:0] sb_axi_awburst, output logic sb_axi_awlock, output logic [3:0] sb_axi_awcache, output logic [2:0] sb_axi_awprot, output logic [3:0] sb_axi_awqos, + /*verilator coverage_on*/ output logic sb_axi_wvalid, input logic sb_axi_wready, @@ -88,19 +97,31 @@ import el2_pkg::*; // AXI Read Channels output logic sb_axi_arvalid, input logic sb_axi_arready, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid, + /*verilator coverage_on*/ output logic [31:0] sb_axi_araddr, output logic [3:0] sb_axi_arregion, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [7:0] sb_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] sb_axi_arsize, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [1:0] sb_axi_arburst, output logic sb_axi_arlock, output logic [3:0] sb_axi_arcache, output logic [2:0] sb_axi_arprot, output logic [3:0] sb_axi_arqos, + /*verilator coverage_on*/ input logic sb_axi_rvalid, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic sb_axi_rready, + /*verilator coverage_on*/ input logic [63:0] sb_axi_rdata, input logic [1:0] sb_axi_rresp, @@ -530,6 +551,8 @@ import el2_pkg::*; dbg_nxtstate = IDLE; dbg_state_en = dmstatus_reg[17]; // resume ack has been updated in the dmstatus register end + /* All legal values are handled above. Exclude the default part from coverage. */ + /*verilator coverage_off*/ default : begin dbg_nxtstate = IDLE; dbg_state_en = 1'b0; @@ -544,6 +567,7 @@ import el2_pkg::*; sb_abmem_cmd_done_en = 1'b0; sb_abmem_data_done_en = 1'b0; end + /*verilator coverage_on*/ endcase end // always_comb begin @@ -656,6 +680,8 @@ import el2_pkg::*; sbcs_sbbusy_din = 1'b0; sbaddress0_reg_wren1 = sbcs_reg[16] & (sbcs_reg[14:12] == 3'b0); // auto increment was set and no error. Update to new address after completing the current command end + /* All legal values are handled above. Exclude the default part from coverage. */ + /*verilator coverage_off*/ default : begin sb_nxtstate = SBIDLE; sb_state_en = 1'b0; @@ -665,6 +691,7 @@ import el2_pkg::*; sbcs_sberror_din[2:0] = 3'b0; sbaddress0_reg_wren1 = 1'b0; end + /*verilator coverage_on*/ endcase end // always_comb begin diff --git a/design/el2_veer.sv b/design/el2_veer.sv index f61da68be46..de7fe13c5ff 100644 --- a/design/el2_veer.sv +++ b/design/el2_veer.sv @@ -134,13 +134,22 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, output logic [31:0] lsu_axi_awaddr, output logic [3:0] lsu_axi_awregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_awsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_awburst, output logic lsu_axi_awlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_awcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_awprot, output logic [3:0] lsu_axi_awqos, + /*verilator coverage_on*/ output logic lsu_axi_wvalid, input logic lsu_axi_wready, @@ -149,7 +158,10 @@ import el2_pkg::*; output logic lsu_axi_wlast, input logic lsu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] lsu_axi_bresp, input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, @@ -159,16 +171,28 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, output logic [31:0] lsu_axi_araddr, output logic [3:0] lsu_axi_arregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_arsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_arburst, output logic lsu_axi_arlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_arcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_arprot, output logic [3:0] lsu_axi_arqos, + /*verilator coverage_on*/ input logic lsu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_rready, + /*verilator coverage_on*/ input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid, input logic [63:0] lsu_axi_rdata, input logic [1:0] lsu_axi_rresp, @@ -176,8 +200,13 @@ import el2_pkg::*; //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_awvalid, + /*verilator coverage_on*/ input logic ifu_axi_awready, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid, output logic [31:0] ifu_axi_awaddr, output logic [3:0] ifu_axi_awregion, @@ -190,13 +219,20 @@ import el2_pkg::*; output logic [3:0] ifu_axi_awqos, output logic ifu_axi_wvalid, + /*verilator coverage_on*/ input logic ifu_axi_wready, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [63:0] ifu_axi_wdata, output logic [7:0] ifu_axi_wstrb, output logic ifu_axi_wlast, + /*verilator coverage_on*/ input logic ifu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] ifu_axi_bresp, input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid, @@ -206,6 +242,8 @@ import el2_pkg::*; output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid, output logic [31:0] ifu_axi_araddr, output logic [3:0] ifu_axi_arregion, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [7:0] ifu_axi_arlen, output logic [2:0] ifu_axi_arsize, output logic [1:0] ifu_axi_arburst, @@ -213,9 +251,13 @@ import el2_pkg::*; output logic [3:0] ifu_axi_arcache, output logic [2:0] ifu_axi_arprot, output logic [3:0] ifu_axi_arqos, + /*verilator coverage_on*/ input logic ifu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_rready, + /*verilator coverage_on*/ input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid, input logic [63:0] ifu_axi_rdata, input logic [1:0] ifu_axi_rresp, @@ -225,16 +267,25 @@ import el2_pkg::*; // AXI Write Channels output logic sb_axi_awvalid, input logic sb_axi_awready, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid, + /*verilator coverage_on*/ output logic [31:0] sb_axi_awaddr, output logic [3:0] sb_axi_awregion, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [7:0] sb_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] sb_axi_awsize, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [1:0] sb_axi_awburst, output logic sb_axi_awlock, output logic [3:0] sb_axi_awcache, output logic [2:0] sb_axi_awprot, output logic [3:0] sb_axi_awqos, + /*verilator coverage_on*/ output logic sb_axi_wvalid, input logic sb_axi_wready, @@ -250,19 +301,31 @@ import el2_pkg::*; // AXI Read Channels output logic sb_axi_arvalid, input logic sb_axi_arready, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid, + /*verilator coverage_on*/ output logic [31:0] sb_axi_araddr, output logic [3:0] sb_axi_arregion, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [7:0] sb_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] sb_axi_arsize, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [1:0] sb_axi_arburst, output logic sb_axi_arlock, output logic [3:0] sb_axi_arcache, output logic [2:0] sb_axi_arprot, output logic [3:0] sb_axi_arqos, + /*verilator coverage_on*/ input logic sb_axi_rvalid, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic sb_axi_rready, + /*verilator coverage_on*/ input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid, input logic [63:0] sb_axi_rdata, input logic [1:0] sb_axi_rresp, @@ -311,8 +374,11 @@ import el2_pkg::*; //// AHB LITE BUS output logic [31:0] haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] hburst, output logic hmastlock, + /*verilator coverage_on*/ output logic [3:0] hprot, output logic [2:0] hsize, output logic [1:0] htrans, @@ -324,8 +390,11 @@ import el2_pkg::*; // LSU AHB Master output logic [31:0] lsu_haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_hburst, output logic lsu_hmastlock, + /*verilator coverage_on*/ output logic [3:0] lsu_hprot, output logic [2:0] lsu_hsize, output logic [1:0] lsu_htrans, @@ -338,8 +407,11 @@ import el2_pkg::*; //System Bus Debug Master output logic [31:0] sb_haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] sb_hburst, output logic sb_hmastlock, + /*verilator coverage_on*/ output logic [3:0] sb_hprot, output logic [2:0] sb_hsize, output logic [1:0] sb_htrans, @@ -484,25 +556,40 @@ import el2_pkg::*; logic sb_axi_rlast_int; logic dma_axi_awvalid_ahb; + /* exclude signals that are tied to constant value in ahb_to_axi4.sv */ + /*verilator coverage_off*/ logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_ahb; + /*verilator coverage_on*/ logic [31:0] dma_axi_awaddr_ahb; logic [2:0] dma_axi_awsize_ahb; + /* exclude signals that are tied to constant value in ahb_to_axi4.sv */ + /*verilator coverage_off*/ logic [2:0] dma_axi_awprot_ahb; logic [7:0] dma_axi_awlen_ahb; logic [1:0] dma_axi_awburst_ahb; + /*verilator coverage_on*/ logic dma_axi_wvalid_ahb; logic [63:0] dma_axi_wdata_ahb; logic [7:0] dma_axi_wstrb_ahb; + /* exclude signals that are tied to constant value in ahb_to_axi4.sv */ + /*verilator coverage_off*/ logic dma_axi_wlast_ahb; logic dma_axi_bready_ahb; + /*verilator coverage_on*/ logic dma_axi_arvalid_ahb; + /* exclude signals that are tied to constant value in ahb_to_axi4.sv */ + /*verilator coverage_off*/ logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid_ahb; + /*verilator coverage_on*/ logic [31:0] dma_axi_araddr_ahb; logic [2:0] dma_axi_arsize_ahb; + /* exclude signals that are tied to constant value in ahb_to_axi4.sv */ + /*verilator coverage_off*/ logic [2:0] dma_axi_arprot_ahb; logic [7:0] dma_axi_arlen_ahb; logic [1:0] dma_axi_arburst_ahb; logic dma_axi_rready_ahb; + /*verilator coverage_on*/ logic dma_axi_awvalid_int; logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_int; diff --git a/design/el2_veer_wrapper.sv b/design/el2_veer_wrapper.sv index d34b97ab96c..d331503d685 100644 --- a/design/el2_veer_wrapper.sv +++ b/design/el2_veer_wrapper.sv @@ -53,13 +53,22 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, output logic [31:0] lsu_axi_awaddr, output logic [3:0] lsu_axi_awregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_awsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_awburst, output logic lsu_axi_awlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_awcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_awprot, output logic [3:0] lsu_axi_awqos, + /*verilator coverage_on*/ output logic lsu_axi_wvalid, input logic lsu_axi_wready, @@ -68,7 +77,10 @@ import el2_pkg::*; output logic lsu_axi_wlast, input logic lsu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] lsu_axi_bresp, input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, @@ -78,16 +90,28 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, output logic [31:0] lsu_axi_araddr, output logic [3:0] lsu_axi_arregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_arsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_arburst, output logic lsu_axi_arlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_arcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_arprot, output logic [3:0] lsu_axi_arqos, + /*verilator coverage_on*/ input logic lsu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_rready, + /*verilator coverage_on*/ input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid, input logic [63:0] lsu_axi_rdata, input logic [1:0] lsu_axi_rresp, @@ -95,8 +119,13 @@ import el2_pkg::*; //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_awvalid, + /*verilator coverage_on*/ input logic ifu_axi_awready, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid, output logic [31:0] ifu_axi_awaddr, output logic [3:0] ifu_axi_awregion, @@ -109,13 +138,20 @@ import el2_pkg::*; output logic [3:0] ifu_axi_awqos, output logic ifu_axi_wvalid, + /*verilator coverage_on*/ input logic ifu_axi_wready, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [63:0] ifu_axi_wdata, output logic [7:0] ifu_axi_wstrb, output logic ifu_axi_wlast, + /*verilator coverage_on*/ input logic ifu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] ifu_axi_bresp, input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid, @@ -125,6 +161,8 @@ import el2_pkg::*; output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid, output logic [31:0] ifu_axi_araddr, output logic [3:0] ifu_axi_arregion, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [7:0] ifu_axi_arlen, output logic [2:0] ifu_axi_arsize, output logic [1:0] ifu_axi_arburst, @@ -132,9 +170,13 @@ import el2_pkg::*; output logic [3:0] ifu_axi_arcache, output logic [2:0] ifu_axi_arprot, output logic [3:0] ifu_axi_arqos, + /*verilator coverage_on*/ input logic ifu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_rready, + /*verilator coverage_on*/ input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid, input logic [63:0] ifu_axi_rdata, input logic [1:0] ifu_axi_rresp, @@ -144,16 +186,25 @@ import el2_pkg::*; // AXI Write Channels output logic sb_axi_awvalid, input logic sb_axi_awready, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid, + /*verilator coverage_on*/ output logic [31:0] sb_axi_awaddr, output logic [3:0] sb_axi_awregion, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [7:0] sb_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] sb_axi_awsize, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [1:0] sb_axi_awburst, output logic sb_axi_awlock, output logic [3:0] sb_axi_awcache, output logic [2:0] sb_axi_awprot, output logic [3:0] sb_axi_awqos, + /*verilator coverage_on*/ output logic sb_axi_wvalid, input logic sb_axi_wready, @@ -169,19 +220,31 @@ import el2_pkg::*; // AXI Read Channels output logic sb_axi_arvalid, input logic sb_axi_arready, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid, + /*verilator coverage_on*/ output logic [31:0] sb_axi_araddr, output logic [3:0] sb_axi_arregion, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [7:0] sb_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] sb_axi_arsize, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic [1:0] sb_axi_arburst, output logic sb_axi_arlock, output logic [3:0] sb_axi_arcache, output logic [2:0] sb_axi_arprot, output logic [3:0] sb_axi_arqos, + /*verilator coverage_on*/ input logic sb_axi_rvalid, + /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */ + /*verilator coverage_off*/ output logic sb_axi_rready, + /*verilator coverage_on*/ input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid, input logic [63:0] sb_axi_rdata, input logic [1:0] sb_axi_rresp, @@ -191,7 +254,10 @@ import el2_pkg::*; // AXI Write Channels input logic dma_axi_awvalid, output logic dma_axi_awready, + /* exclude signals that are tied to constant value in tb_top.sv */ + /*verilator coverage_off*/ input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid, + /*verilator coverage_on*/ input logic [31:0] dma_axi_awaddr, input logic [2:0] dma_axi_awsize, input logic [2:0] dma_axi_awprot, @@ -213,7 +279,10 @@ import el2_pkg::*; // AXI Read Channels input logic dma_axi_arvalid, output logic dma_axi_arready, + /* exclude signals that are tied to constant value in tb_top.sv */ + /*verilator coverage_off*/ input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid, + /*verilator coverage_on*/ input logic [31:0] dma_axi_araddr, input logic [2:0] dma_axi_arsize, input logic [2:0] dma_axi_arprot, @@ -231,45 +300,65 @@ import el2_pkg::*; `ifdef RV_BUILD_AHB_LITE //// AHB LITE BUS output logic [31:0] haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] hburst, output logic hmastlock, + /*verilator coverage_on*/ output logic [3:0] hprot, output logic [2:0] hsize, output logic [1:0] htrans, output logic hwrite, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ input logic [63:0] hrdata, input logic hready, input logic hresp, + /*verilator coverage_on*/ // LSU AHB Master output logic [31:0] lsu_haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_hburst, output logic lsu_hmastlock, + /*verilator coverage_on*/ output logic [3:0] lsu_hprot, output logic [2:0] lsu_hsize, output logic [1:0] lsu_htrans, output logic lsu_hwrite, output logic [63:0] lsu_hwdata, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ input logic [63:0] lsu_hrdata, input logic lsu_hready, input logic lsu_hresp, + /*verilator coverage_on*/ // Debug Syster Bus AHB output logic [31:0] sb_haddr, + /* exclude signals that are tied to constant value in axi4_to_ahb.sv */ + /*verilator coverage_off*/ output logic [2:0] sb_hburst, output logic sb_hmastlock, + /*verilator coverage_on*/ output logic [3:0] sb_hprot, output logic [2:0] sb_hsize, output logic [1:0] sb_htrans, output logic sb_hwrite, output logic [63:0] sb_hwdata, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ input logic [63:0] sb_hrdata, input logic sb_hready, input logic sb_hresp, + /*verilator coverage_on*/ // DMA Slave + /* exclude signals that are tied to constant value in tb_top.sv */ + /*verilator coverage_off*/ input logic dma_hsel, input logic [31:0] dma_haddr, input logic [2:0] dma_hburst, @@ -279,6 +368,7 @@ import el2_pkg::*; input logic [1:0] dma_htrans, input logic dma_hwrite, input logic [63:0] dma_hwdata, + /*verilator coverage_on*/ input logic dma_hreadyin, output logic [63:0] dma_hrdata, @@ -338,6 +428,9 @@ import el2_pkg::*; output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request input logic i_cpu_run_req, // Async restart req to CPU output logic o_cpu_run_ack, // Core response to run req + + /* exclude signals that are tied to constant value or left unconnected in tb_top.sv */ + /* verilator coverage_off */ input logic scan_mode, // To enable scan mode input logic mbist_mode, // to enable mbist @@ -348,6 +441,7 @@ import el2_pkg::*; output logic [ 6:0] dmi_uncore_addr, output logic [31:0] dmi_uncore_wdata, input logic [31:0] dmi_uncore_rdata + /* verilator coverage_on */ ); logic active_l2clk; @@ -418,6 +512,8 @@ import el2_pkg::*; // zero out the signals not presented at the wrapper instantiation level `ifdef RV_BUILD_AXI4 + // Since all the signals in this block are tied to constant, we exclude this from coverage analysis + /*verilator coverage_off*/ //// AHB LITE BUS logic [31:0] haddr; @@ -502,10 +598,14 @@ import el2_pkg::*; assign dma_hwdata[63:0] = '0; assign dma_hreadyin = '0; + /*verilator coverage_on*/ + `endif // `ifdef RV_BUILD_AXI4 `ifdef RV_BUILD_AHB_LITE + // Since all the signals in this block are tied to constant, we exclude this from coverage analysis + /*verilator coverage_off*/ wire lsu_axi_awvalid; wire lsu_axi_awready; wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid; @@ -750,6 +850,8 @@ import el2_pkg::*; assign ifu_axi_bvalid = '0; assign ifu_axi_bresp[1:0] = '0; assign ifu_axi_bid[pt.IFU_BUS_TAG-1:0] = '0; + + /*verilator coverage_on*/ `endif // `ifdef RV_BUILD_AHB_LITE diff --git a/design/ifu/el2_ifu.sv b/design/ifu/el2_ifu.sv index dbb2bc1843f..1d9858d1396 100644 --- a/design/ifu/el2_ifu.sv +++ b/design/ifu/el2_ifu.sv @@ -48,6 +48,8 @@ import el2_pkg::*; //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_awvalid, output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid, output logic [31:0] ifu_axi_awaddr, @@ -66,6 +68,7 @@ import el2_pkg::*; output logic ifu_axi_wlast, output logic ifu_axi_bready, + /*verilator coverage_on*/ // AXI Read Channels output logic ifu_axi_arvalid, @@ -73,6 +76,8 @@ import el2_pkg::*; output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid, output logic [31:0] ifu_axi_araddr, output logic [3:0] ifu_axi_arregion, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic [7:0] ifu_axi_arlen, output logic [2:0] ifu_axi_arsize, output logic [1:0] ifu_axi_arburst, @@ -80,9 +85,13 @@ import el2_pkg::*; output logic [3:0] ifu_axi_arcache, output logic [2:0] ifu_axi_arprot, output logic [3:0] ifu_axi_arqos, + /*verilator coverage_on*/ input logic ifu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */ + /*verilator coverage_off*/ output logic ifu_axi_rready, + /*verilator coverage_on*/ input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid, input logic [63:0] ifu_axi_rdata, input logic [1:0] ifu_axi_rresp, diff --git a/design/ifu/el2_ifu_mem_ctl.sv b/design/ifu/el2_ifu_mem_ctl.sv index 38cb5f3829c..48ff2ab49b9 100644 --- a/design/ifu/el2_ifu_mem_ctl.sv +++ b/design/ifu/el2_ifu_mem_ctl.sv @@ -64,6 +64,8 @@ import el2_pkg::*; //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic ifu_axi_awvalid, output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid, output logic [31:0] ifu_axi_awaddr, @@ -82,6 +84,7 @@ import el2_pkg::*; output logic ifu_axi_wlast, output logic ifu_axi_bready, + /*verilator coverage_on*/ // AXI Read Channels output logic ifu_axi_arvalid, @@ -89,6 +92,8 @@ import el2_pkg::*; output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid, output logic [31:0] ifu_axi_araddr, output logic [3:0] ifu_axi_arregion, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [7:0] ifu_axi_arlen, output logic [2:0] ifu_axi_arsize, output logic [1:0] ifu_axi_arburst, @@ -96,9 +101,13 @@ import el2_pkg::*; output logic [3:0] ifu_axi_arcache, output logic [2:0] ifu_axi_arprot, output logic [3:0] ifu_axi_arqos, + /*verilator coverage_on*/ input logic ifu_axi_rvalid, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic ifu_axi_rready, + /*verilator coverage_on*/ input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid, input logic [63:0] ifu_axi_rdata, input logic [1:0] ifu_axi_rresp, @@ -526,10 +535,12 @@ import el2_pkg::*; exu_flush_final ? ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE; miss_state_en = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt; end + /*verilator coverage_off*/ default: begin : def_case miss_nxtstate = IDLE; miss_state_en = 1'b0; end + /*verilator coverage_on*/ endcase end rvdffs #(($bits(miss_state_t))) miss_state_ff (.clk(active_clk), .din(miss_nxtstate), .dout({miss_state}), .en(miss_state_en), .*); @@ -1012,6 +1023,7 @@ assign ic_miss_buff_half[63:0] = {ic_miss_buff_data[{other_tag,1'b1}],ic_miss iccm_correction_state = 1'b1; end + /*verilator coverage_off*/ default: begin : def_case err_stop_nxtstate = ERR_STOP_IDLE; err_stop_state_en = 1'b0; @@ -1019,6 +1031,7 @@ assign ic_miss_buff_half[63:0] = {ic_miss_buff_data[{other_tag,1'b1}],ic_miss iccm_correction_state = 1'b1; end + /*verilator coverage_on*/ endcase end rvdffs #(($bits(err_stop_state_t))) err_stop_state_ff (.clk(active_clk), .din(err_stop_nxtstate), .dout({err_stop_state}), .en(err_stop_state_en), .*); diff --git a/design/lib/ahb_to_axi4.sv b/design/lib/ahb_to_axi4.sv index 8c8226b3322..56ee49e7f32 100644 --- a/design/lib/ahb_to_axi4.sv +++ b/design/lib/ahb_to_axi4.sv @@ -30,7 +30,9 @@ import el2_pkg::*; ( input clk, input rst_l, + /* verilator coverage_off */ input scan_mode, + /* verilator coverage_on */ input bus_clk_en, input clk_override, @@ -38,45 +40,76 @@ import el2_pkg::*; // AXI Write Channels output logic axi_awvalid, input logic axi_awready, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [TAG-1:0] axi_awid, + /*verilator coverage_on*/ output logic [31:0] axi_awaddr, output logic [2:0] axi_awsize, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [2:0] axi_awprot, output logic [7:0] axi_awlen, output logic [1:0] axi_awburst, + /*verilator coverage_on*/ output logic axi_wvalid, input logic axi_wready, output logic [63:0] axi_wdata, output logic [7:0] axi_wstrb, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic axi_wlast, + /*verilator coverage_on*/ input logic axi_bvalid, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic axi_bready, + /*verilator coverage_on*/ input logic [1:0] axi_bresp, + /* Exclude unused AXI rid since it has no equivalent in AHB */ + /*verilator coverage_off*/ input logic [TAG-1:0] axi_bid, + /*verilator coverage_on*/ // AXI Read Channels output logic axi_arvalid, input logic axi_arready, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [TAG-1:0] axi_arid, + /*verilator coverage_on*/ output logic [31:0] axi_araddr, output logic [2:0] axi_arsize, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [2:0] axi_arprot, output logic [7:0] axi_arlen, output logic [1:0] axi_arburst, + /*verilator coverage_on*/ input logic axi_rvalid, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic axi_rready, + /*verilator coverage_on*/ + /* Exclude unused AXI rid since it has no equivalent in AHB */ + /*verilator coverage_off*/ input logic [TAG-1:0] axi_rid, + /*verilator coverage_on*/ input logic [63:0] axi_rdata, input logic [1:0] axi_rresp, // AHB-Lite signals input logic [31:0] ahb_haddr, // ahb bus address + // Exclude input signals that are unused in this file (their AXI equivalents + // are tied to constants) + /*verilator coverage_off*/ input logic [2:0] ahb_hburst, // tied to 0 input logic ahb_hmastlock, // tied to 0 input logic [3:0] ahb_hprot, // tied to 4'b0011 + /*verilator coverage_on*/ input logic [2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3) input logic [1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now) input logic ahb_hwrite, // ahb bus write @@ -286,4 +319,4 @@ import el2_pkg::*; `endif -endmodule // ahb_to_axi4 \ No newline at end of file +endmodule // ahb_to_axi4 diff --git a/design/lib/axi4_to_ahb.sv b/design/lib/axi4_to_ahb.sv index 201cca97f70..51abd8403c2 100644 --- a/design/lib/axi4_to_ahb.sv +++ b/design/lib/axi4_to_ahb.sv @@ -72,9 +72,12 @@ import el2_pkg::*; // AHB-Lite signals output logic [31:0] ahb_haddr, // ahb bus address + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [2:0] ahb_hburst, // tied to 0 output logic ahb_hmastlock, // tied to 0 - output logic [3:0] ahb_hprot, // tied to 4'b0011 + /*verilator coverage_on*/ + output logic [3:0] ahb_hprot, // [3:1] are tied to 3'b001 output logic [2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3) output logic [1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now) output logic ahb_hwrite, // ahb bus write diff --git a/design/lsu/el2_lsu.sv b/design/lsu/el2_lsu.sv index e3e89a61e64..fd58f71cdc6 100644 --- a/design/lsu/el2_lsu.sv +++ b/design/lsu/el2_lsu.sv @@ -118,13 +118,22 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, output logic [31:0] lsu_axi_awaddr, output logic [3:0] lsu_axi_awregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_awsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_awburst, output logic lsu_axi_awlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_awcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_awprot, output logic [3:0] lsu_axi_awqos, + /*verilator coverage_on*/ output logic lsu_axi_wvalid, input logic lsu_axi_wready, @@ -133,7 +142,10 @@ import el2_pkg::*; output logic lsu_axi_wlast, input logic lsu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] lsu_axi_bresp, input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, @@ -143,16 +155,28 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, output logic [31:0] lsu_axi_araddr, output logic [3:0] lsu_axi_arregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_arsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_arburst, output logic lsu_axi_arlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_arcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_arprot, output logic [3:0] lsu_axi_arqos, + /*verilator coverage_on*/ input logic lsu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_rready, + /*verilator coverage_on*/ input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid, input logic [63:0] lsu_axi_rdata, input logic [1:0] lsu_axi_rresp, diff --git a/design/lsu/el2_lsu_bus_buffer.sv b/design/lsu/el2_lsu_bus_buffer.sv index 7da9b1f1b58..80a97ddae21 100644 --- a/design/lsu/el2_lsu_bus_buffer.sv +++ b/design/lsu/el2_lsu_bus_buffer.sv @@ -106,13 +106,22 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, output logic [31:0] lsu_axi_awaddr, output logic [3:0] lsu_axi_awregion, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_awsize, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_awburst, output logic lsu_axi_awlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_awcache, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_awprot, output logic [3:0] lsu_axi_awqos, + /*verilator coverage_on*/ output logic lsu_axi_wvalid, input logic lsu_axi_wready, @@ -121,7 +130,10 @@ import el2_pkg::*; output logic lsu_axi_wlast, input logic lsu_axi_bvalid, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic lsu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] lsu_axi_bresp, input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, @@ -131,16 +143,28 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, output logic [31:0] lsu_axi_araddr, output logic [3:0] lsu_axi_arregion, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_arsize, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_arburst, output logic lsu_axi_arlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_arcache, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_arprot, output logic [3:0] lsu_axi_arqos, + /*verilator coverage_on*/ input logic lsu_axi_rvalid, + /* exclude signals that are tied to constant value in this file */ + /*verilator coverage_off*/ output logic lsu_axi_rready, + /*verilator coverage_on*/ input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid, input logic [63:0] lsu_axi_rdata, input logic [1:0] lsu_axi_rresp, diff --git a/design/lsu/el2_lsu_bus_intf.sv b/design/lsu/el2_lsu_bus_intf.sv index 2efcbfe810a..71622e92f0d 100644 --- a/design/lsu/el2_lsu_bus_intf.sv +++ b/design/lsu/el2_lsu_bus_intf.sv @@ -102,13 +102,22 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid, output logic [31:0] lsu_axi_awaddr, output logic [3:0] lsu_axi_awregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_awlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_awsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_awburst, output logic lsu_axi_awlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_awcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_awprot, output logic [3:0] lsu_axi_awqos, + /*verilator coverage_on*/ output logic lsu_axi_wvalid, input logic lsu_axi_wready, @@ -117,7 +126,10 @@ import el2_pkg::*; output logic lsu_axi_wlast, input logic lsu_axi_bvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_bready, + /*verilator coverage_on*/ input logic [1:0] lsu_axi_bresp, input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid, @@ -127,16 +139,28 @@ import el2_pkg::*; output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid, output logic [31:0] lsu_axi_araddr, output logic [3:0] lsu_axi_arregion, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [7:0] lsu_axi_arlen, + /*verilator coverage_on*/ output logic [2:0] lsu_axi_arsize, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [1:0] lsu_axi_arburst, output logic lsu_axi_arlock, + /*verilator coverage_on*/ output logic [3:0] lsu_axi_arcache, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic [2:0] lsu_axi_arprot, output logic [3:0] lsu_axi_arqos, + /*verilator coverage_on*/ input logic lsu_axi_rvalid, + /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */ + /*verilator coverage_off*/ output logic lsu_axi_rready, + /*verilator coverage_on*/ input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid, input logic [63:0] lsu_axi_rdata, input logic [1:0] lsu_axi_rresp, From 70cd4d9ef6a700794c34561489f8a53942cc48f8 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Mon, 7 Oct 2024 15:32:17 +0200 Subject: [PATCH 08/11] verlator: testbench: test CPU halt and restart Signed-off-by: Karol Gugala --- testbench/tb_top.sv | 33 ++++++++-------- testbench/test_tb_top.cpp | 80 +++++++++++++++++++++++++++++++++++++++ tools/Makefile | 4 +- 3 files changed, 99 insertions(+), 18 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 4ae69f8cb76..70d0877b585 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -30,7 +30,17 @@ module tb_top input bit core_clk, input bit [31:0] mem_signature_begin, input bit [31:0] mem_signature_end, - input bit [31:0] mem_mailbox + input bit [31:0] mem_mailbox, + input bit i_cpu_halt_req, // Async halt req to CPU + output bit o_cpu_halt_ack, // core response to halt + output bit o_cpu_halt_status, // 1'b1 indicates core is halted + input bit i_cpu_run_req, // Async restart req to CPU + output bit o_cpu_run_ack, // Core response to run req + input bit mpc_debug_halt_req, + output bit mpc_debug_halt_ack, + input bit mpc_debug_run_req, + output bit mpc_debug_run_ack, + output bit o_debug_mode_status ); `endif @@ -111,7 +121,6 @@ module tb_top logic trace_rv_i_interrupt_ip; logic [31:0] trace_rv_i_tval_ip; - logic o_debug_mode_status; logic jtag_tdo; @@ -120,10 +129,6 @@ module tb_top logic jtag_tdi; logic jtag_trst_n; - logic o_cpu_halt_ack; - logic o_cpu_halt_status; - logic o_cpu_run_ack; - logic mailbox_write; logic [63:0] mailbox_data; @@ -132,11 +137,7 @@ module tb_top logic dma_hready ; logic dma_hresp ; - logic mpc_debug_halt_req; - logic mpc_debug_run_req; logic mpc_reset_run_req; - logic mpc_debug_halt_ack; - logic mpc_debug_run_ack; logic debug_brkpt_status; int cycleCnt; @@ -1251,17 +1252,17 @@ veer_wrapper rvtop_wrapper ( .jtag_tdoEn (), .mpc_debug_halt_ack ( mpc_debug_halt_ack), - .mpc_debug_halt_req ( 1'b0), + .mpc_debug_halt_req ( mpc_debug_halt_req), .mpc_debug_run_ack ( mpc_debug_run_ack), - .mpc_debug_run_req ( 1'b1), + .mpc_debug_run_req ( mpc_debug_run_req), .mpc_reset_run_req ( 1'b1), // Start running after reset - .debug_brkpt_status (debug_brkpt_status), + .debug_brkpt_status (debug_brkpt_status), - .i_cpu_halt_req ( 1'b0 ), // Async halt req to CPU + .i_cpu_halt_req ( i_cpu_halt_req ), // Async halt req to CPU .o_cpu_halt_ack ( o_cpu_halt_ack ), // core response to halt .o_cpu_halt_status ( o_cpu_halt_status ), // 1'b1 indicates core is halted - .i_cpu_run_req ( 1'b0 ), // Async restart req to CPU - .o_debug_mode_status (o_debug_mode_status), + .i_cpu_run_req ( i_cpu_run_req ), // Async restart req to CPU + .o_debug_mode_status ( o_debug_mode_status), .o_cpu_run_ack ( o_cpu_run_ack ), // Core response to run req .dec_tlu_perfcnt0 (), diff --git a/testbench/test_tb_top.cpp b/testbench/test_tb_top.cpp index fbebf3a4a79..8bec823410c 100644 --- a/testbench/test_tb_top.cpp +++ b/testbench/test_tb_top.cpp @@ -67,6 +67,7 @@ int main(int argc, char** argv) { Verilated::commandArgs(argc, argv); Vtb_top* tb = new Vtb_top; + bool test_halt = false; tb->mem_signature_begin = 0x00000000; tb->mem_signature_end = 0x00000000; @@ -118,6 +119,14 @@ int main(int argc, char** argv) { } } + // run halt start procedure if requested with + // "--test-halt" + for (int i=1; iopen ("sim.vcd"); #endif // Simulate + if(test_halt) { + // Test halt/start first (if requested) + tb->i_cpu_halt_req = 1; + // wait for ack + std::cout<<"Waiting for halt"<o_cpu_halt_ack) { + main_time += 5; + tb->core_clk = !tb->core_clk; + tb->eval(); + } + tb->i_cpu_halt_req = 0; + // wait for halt signal + while(!tb->o_cpu_halt_status) { + main_time += 5; + tb->core_clk = !tb->core_clk; + tb->eval(); + } + // restart the CPU + tb->i_cpu_run_req = 1; + // wait for ack + while(!tb->o_cpu_run_ack) { + main_time += 5; + tb->core_clk = !tb->core_clk; + tb->eval(); + } + tb->i_cpu_run_req = 0; + // wait for run signal + std::cout<<"Waiting for restart"<o_cpu_halt_status) { + main_time += 5; + tb->core_clk = !tb->core_clk; + tb->eval(); + } + // test mpc halt + tb->mpc_debug_halt_req = 1; + // wait for ack + std::cout<<"Waiting for mpc halt"<mpc_debug_halt_ack) { + main_time += 5; + tb->core_clk = !tb->core_clk; + tb->eval(); + } + tb->mpc_debug_halt_req = 0; + // wait for halt signal + while(!tb->o_debug_mode_status) { + main_time += 5; + tb->core_clk = !tb->core_clk; + tb->eval(); + } + // restart the CPU + tb->mpc_debug_run_req = 1; + // wait for ack + while(!tb->mpc_debug_run_ack) { + main_time += 5; + tb->core_clk = !tb->core_clk; + tb->eval(); + } + tb->mpc_debug_run_req = 0; + // wait for run signal + std::cout<<"Waiting for mpc restart"<o_debug_mode_status) { + main_time += 5; + tb->core_clk = !tb->core_clk; + tb->eval(); + } + } else { + tb->i_cpu_halt_req = 0; + tb->i_cpu_run_req = 0; + tb->mpc_debug_halt_req = 0; + tb->mpc_debug_run_req = 0; + } while(!Verilated::gotFinish()){ #if VM_TRACE tfp->dump (main_time); diff --git a/tools/Makefile b/tools/Makefile index 2936e006fb9..2a279cfb679 100755 --- a/tools/Makefile +++ b/tools/Makefile @@ -218,9 +218,9 @@ verilator: program.hex verilator-build if [ $$? -eq 0 ]; then \ BEG=`grep "begin_signature" $(TEST).sym | cut -d\ -f 1`;\ END=`grep "end_signature" $(TEST).sym | cut -d\ -f 1`;\ - ./obj_dir/Vtb_top --mem-signature $${BEG} $${END}; \ + ./obj_dir/Vtb_top --test-halt --mem-signature $${BEG} $${END}; \ else \ - ./obj_dir/Vtb_top; \ + ./obj_dir/Vtb_top --test-halt; \ fi irun: program.hex irun-build From b292525697bb30ef8ba21c18ca28200f5fc415c8 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Tue, 8 Oct 2024 15:34:07 +0200 Subject: [PATCH 09/11] add tests for custom CSRs Signed-off-by: Wojciech Sipak --- .../workflows/test-regression-exceptions.yml | 3 +- .github/workflows/test-regression.yml | 2 +- testbench/tests/clk_override/clk_override.c | 22 +++++++++++++ testbench/tests/clk_override/clk_override.ld | 14 ++++++++ testbench/tests/clk_override/clk_override.mki | 4 +++ testbench/tests/clk_override/crt0.s | 31 ++++++++++++++++++ testbench/tests/clk_override/printf.c | 1 + testbench/tests/core_pause/core_pause.c | 13 ++++++++ testbench/tests/core_pause/core_pause.ld | 14 ++++++++ testbench/tests/core_pause/core_pause.mki | 4 +++ testbench/tests/core_pause/crt0.s | 31 ++++++++++++++++++ testbench/tests/core_pause/printf.c | 1 + testbench/tests/write_unaligned/crt0.s | 31 ++++++++++++++++++ testbench/tests/write_unaligned/printf.c | 1 + .../tests/write_unaligned/write_unaligned.c | 32 +++++++++++++++++++ .../tests/write_unaligned/write_unaligned.ld | 18 +++++++++++ .../tests/write_unaligned/write_unaligned.mki | 4 +++ 17 files changed, 224 insertions(+), 2 deletions(-) create mode 100644 testbench/tests/clk_override/clk_override.c create mode 100644 testbench/tests/clk_override/clk_override.ld create mode 100644 testbench/tests/clk_override/clk_override.mki create mode 100644 testbench/tests/clk_override/crt0.s create mode 120000 testbench/tests/clk_override/printf.c create mode 100644 testbench/tests/core_pause/core_pause.c create mode 100644 testbench/tests/core_pause/core_pause.ld create mode 100644 testbench/tests/core_pause/core_pause.mki create mode 100644 testbench/tests/core_pause/crt0.s create mode 120000 testbench/tests/core_pause/printf.c create mode 100644 testbench/tests/write_unaligned/crt0.s create mode 120000 testbench/tests/write_unaligned/printf.c create mode 100644 testbench/tests/write_unaligned/write_unaligned.c create mode 100644 testbench/tests/write_unaligned/write_unaligned.ld create mode 100644 testbench/tests/write_unaligned/write_unaligned.mki diff --git a/.github/workflows/test-regression-exceptions.yml b/.github/workflows/test-regression-exceptions.yml index 9b7d21393cc..9e2503b4895 100644 --- a/.github/workflows/test-regression-exceptions.yml +++ b/.github/workflows/test-regression-exceptions.yml @@ -15,7 +15,8 @@ jobs: test: ["machine_external_ints", "dbus_store_error", "lsu_trigger_hit", "machine_external_vec_ints", "dside_pic_access_error", "iside_fetch_precise_bus_error", "dside_access_region_prediction_error", "cmark", "iside_core_local_unmapped_address_error", "dside_access_across_region_boundary", "nmi_pin_assertion", "dside_size_misaligned_access_to_non_idempotent_address", - "dside_core_local_access_unmapped_address_error", "dbus_nonblocking_load_error", "internal_timer_ints", "ebreak_ecall", "illegal_instruction"] + "dside_core_local_access_unmapped_address_error", "dbus_nonblocking_load_error", "internal_timer_ints", "ebreak_ecall", "illegal_instruction", + "clk_override", "core_pause"] coverage: ["all", "branch", "toggle"] #TODO: add functional coverage priv: ["0"] env: diff --git a/.github/workflows/test-regression.yml b/.github/workflows/test-regression.yml index 0264c2d0bd5..eb85a28a9e6 100644 --- a/.github/workflows/test-regression.yml +++ b/.github/workflows/test-regression.yml @@ -13,7 +13,7 @@ jobs: matrix: bus: ["axi", "ahb"] test: ["hello_world", "hello_world_dccm", "hello_world_iccm", "cmark", "cmark_dccm", "cmark_iccm", "dhry", "ecc", - "csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp"] + "csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp", "write_unaligned"] coverage: ["all", "branch", "toggle"] #TODO: add functional coverage priv: ["0", "1"] exclude: diff --git a/testbench/tests/clk_override/clk_override.c b/testbench/tests/clk_override/clk_override.c new file mode 100644 index 00000000000..6d949e54fce --- /dev/null +++ b/testbench/tests/clk_override/clk_override.c @@ -0,0 +1,22 @@ +#include +#include + +int main () { + + uint32_t value = 0; + __asm__ volatile ( + "csrw 0x7f8, %0" // Write the value of foo to MCGC CSR + : // No output operands + : "r"(value) // Input operand (value) as register + ); + + for (int bit = 0; bit <= 9; bit++) { + value = 1 << bit; + __asm__ volatile ( + "csrw 0x7f8, %0" + : + : "r"(value) + ); + } + return 0; +} diff --git a/testbench/tests/clk_override/clk_override.ld b/testbench/tests/clk_override/clk_override.ld new file mode 100644 index 00000000000..ab6ae8ec3c5 --- /dev/null +++ b/testbench/tests/clk_override/clk_override.ld @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS { + . = 0x80000000; + .text : { *(.text.init*) *(.text*) } + _end = .; + .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} + .bss : { *(.bss) } + . = 0xd0580000; + .data.io . : { *(.data.io) } +} diff --git a/testbench/tests/clk_override/clk_override.mki b/testbench/tests/clk_override/clk_override.mki new file mode 100644 index 00000000000..6722aacdc72 --- /dev/null +++ b/testbench/tests/clk_override/clk_override.mki @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +OFILES = crt0.o clk_override.o printf.o +TEST_CFLAGS = -g -O3 -falign-functions=16 diff --git a/testbench/tests/clk_override/crt0.s b/testbench/tests/clk_override/crt0.s new file mode 100644 index 00000000000..7ab884748a6 --- /dev/null +++ b/testbench/tests/clk_override/crt0.s @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +.section .text.init +.global _start +_start: + + # Setup stack + la sp, STACK + + # Call main() + call main + + # Map exit code: == 0 - success, != 0 - failure + mv a1, a0 + li a0, 0xff # ok + beq a1, x0, _finish + li a0, 1 # fail + +.global _finish +_finish: + la t0, tohost + sb a0, 0(t0) # Signal testbench termination + beq x0, x0, _finish + .rept 10 + nop + .endr + +.section .data.io +.global tohost +tohost: .word 0 + diff --git a/testbench/tests/clk_override/printf.c b/testbench/tests/clk_override/printf.c new file mode 120000 index 00000000000..430ba5df62c --- /dev/null +++ b/testbench/tests/clk_override/printf.c @@ -0,0 +1 @@ +../../asm/printf.c \ No newline at end of file diff --git a/testbench/tests/core_pause/core_pause.c b/testbench/tests/core_pause/core_pause.c new file mode 100644 index 00000000000..580c955f859 --- /dev/null +++ b/testbench/tests/core_pause/core_pause.c @@ -0,0 +1,13 @@ +#include +#include + +int main () { + /* pause the core for 0xfff cycles */ + uint32_t value = 0xfff; + __asm__ volatile ( + "csrw 0x7c2, %0" // Write the value of foo to MCPC CSR + : // No output operands + : "r"(value) // Input operand (value) as register + ); + return 0; +} diff --git a/testbench/tests/core_pause/core_pause.ld b/testbench/tests/core_pause/core_pause.ld new file mode 100644 index 00000000000..ab6ae8ec3c5 --- /dev/null +++ b/testbench/tests/core_pause/core_pause.ld @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS { + . = 0x80000000; + .text : { *(.text.init*) *(.text*) } + _end = .; + .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} + .bss : { *(.bss) } + . = 0xd0580000; + .data.io . : { *(.data.io) } +} diff --git a/testbench/tests/core_pause/core_pause.mki b/testbench/tests/core_pause/core_pause.mki new file mode 100644 index 00000000000..1cdeb7d83fd --- /dev/null +++ b/testbench/tests/core_pause/core_pause.mki @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +OFILES = crt0.o core_pause.o printf.o +TEST_CFLAGS = -g -O3 -falign-functions=16 diff --git a/testbench/tests/core_pause/crt0.s b/testbench/tests/core_pause/crt0.s new file mode 100644 index 00000000000..7ab884748a6 --- /dev/null +++ b/testbench/tests/core_pause/crt0.s @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +.section .text.init +.global _start +_start: + + # Setup stack + la sp, STACK + + # Call main() + call main + + # Map exit code: == 0 - success, != 0 - failure + mv a1, a0 + li a0, 0xff # ok + beq a1, x0, _finish + li a0, 1 # fail + +.global _finish +_finish: + la t0, tohost + sb a0, 0(t0) # Signal testbench termination + beq x0, x0, _finish + .rept 10 + nop + .endr + +.section .data.io +.global tohost +tohost: .word 0 + diff --git a/testbench/tests/core_pause/printf.c b/testbench/tests/core_pause/printf.c new file mode 120000 index 00000000000..430ba5df62c --- /dev/null +++ b/testbench/tests/core_pause/printf.c @@ -0,0 +1 @@ +../../asm/printf.c \ No newline at end of file diff --git a/testbench/tests/write_unaligned/crt0.s b/testbench/tests/write_unaligned/crt0.s new file mode 100644 index 00000000000..7ab884748a6 --- /dev/null +++ b/testbench/tests/write_unaligned/crt0.s @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +.section .text.init +.global _start +_start: + + # Setup stack + la sp, STACK + + # Call main() + call main + + # Map exit code: == 0 - success, != 0 - failure + mv a1, a0 + li a0, 0xff # ok + beq a1, x0, _finish + li a0, 1 # fail + +.global _finish +_finish: + la t0, tohost + sb a0, 0(t0) # Signal testbench termination + beq x0, x0, _finish + .rept 10 + nop + .endr + +.section .data.io +.global tohost +tohost: .word 0 + diff --git a/testbench/tests/write_unaligned/printf.c b/testbench/tests/write_unaligned/printf.c new file mode 120000 index 00000000000..430ba5df62c --- /dev/null +++ b/testbench/tests/write_unaligned/printf.c @@ -0,0 +1 @@ +../../asm/printf.c \ No newline at end of file diff --git a/testbench/tests/write_unaligned/write_unaligned.c b/testbench/tests/write_unaligned/write_unaligned.c new file mode 100644 index 00000000000..1bad0789b6a --- /dev/null +++ b/testbench/tests/write_unaligned/write_unaligned.c @@ -0,0 +1,32 @@ +#include + +int handler() __attribute__((section(".handler"))); + +int handler() { + return 0; +} + +int main () { + int (*func)() = (int (*)())0x70000001; + volatile uint32_t csr_value; + + printf("jumping to 0x70000001\n"); + func(); + printf("jumping to 0x80001\n"); + func = 0x80001; + func(); + printf("jumping to 0xe000001\n"); + func = 0xe000001; + func(); + printf("jumping to 0x3fffffff\n"); + func = 0x3fffffff; + func(); + printf("jumping to 0xa001\n"); + func = 0xa001; + func(); + + // read CSR at address 0x7FF (mscause) + __asm__ volatile ("csrr %0, 0x7FF" : "=r"(csr_value)); + + return 0; +} diff --git a/testbench/tests/write_unaligned/write_unaligned.ld b/testbench/tests/write_unaligned/write_unaligned.ld new file mode 100644 index 00000000000..be47ebda0ea --- /dev/null +++ b/testbench/tests/write_unaligned/write_unaligned.ld @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS { + .handler : { + KEEP(*(.handler)) + } > RAM = 0x0 + + . = 0x80000000; + .text : { *(.text.init*) *(.text*) } + _end = .; + .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} + .bss : { *(.bss) } + . = 0xd0580000; + .data.io . : { *(.data.io) } +} diff --git a/testbench/tests/write_unaligned/write_unaligned.mki b/testbench/tests/write_unaligned/write_unaligned.mki new file mode 100644 index 00000000000..42985c1ba2f --- /dev/null +++ b/testbench/tests/write_unaligned/write_unaligned.mki @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +OFILES = crt0.o write_unaligned.o printf.o +TEST_CFLAGS = -g -O3 -falign-functions=16 From e0cc7d1aa29200b6993d5534e337bd96b8c84a46 Mon Sep 17 00:00:00 2001 From: Tomasz Michalak Date: Wed, 9 Oct 2024 23:41:30 +0200 Subject: [PATCH 10/11] Increase coverage of pmp permission tests Signed-off-by: Tomasz Michalak --- design/el2_pmp.sv | 4 ++++ testbench/tests/csr_mseccfg/csr_mseccfg.c | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/design/el2_pmp.sv b/design/el2_pmp.sv index 9a156ee0199..502b11f932c 100644 --- a/design/el2_pmp.sv +++ b/design/el2_pmp.sv @@ -25,7 +25,9 @@ module el2_pmp ) ( input logic clk, // Top level clock input logic rst_l, // Reset + /* verilator coverage_off */ input logic scan_mode, // Scan mode + /* verilator coverage_on */ `ifdef RV_SMEPMP input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits @@ -113,7 +115,9 @@ module el2_pmp 2'b11: result = (pmp_req_type == EXEC) | ((pmp_req_type == READ) & ~priv_mode); + /* verilator coverage_off */ default: ; + /* verilator coverage_on */ endcase end else begin if (csr_pmp_cfg.read & csr_pmp_cfg.write & csr_pmp_cfg.execute & csr_pmp_cfg.lock) begin diff --git a/testbench/tests/csr_mseccfg/csr_mseccfg.c b/testbench/tests/csr_mseccfg/csr_mseccfg.c index cb690ce2d64..a026334ebab 100644 --- a/testbench/tests/csr_mseccfg/csr_mseccfg.c +++ b/testbench/tests/csr_mseccfg/csr_mseccfg.c @@ -98,7 +98,8 @@ int main () { write_csr(CSR_PMPADDR3, PMPADDR(A(_data_end))); uint32_t pmpcfg; - pmpcfg = PMPREGION((PMPCFG_TOR | PMPCFG_X) , 1) | + pmpcfg = PMPREGION((PMPCFG_TOR | PMPCFG_W | PMPCFG_X), 1) | + PMPREGION((PMPCFG_TOR | PMPCFG_W), 2) | PMPREGION((PMPCFG_TOR | PMPCFG_R | PMPCFG_W), 3); write_csr(CSR_PMPCFG0, pmpcfg); From b7d2856e6c043311121268c511b5018fe84d7245 Mon Sep 17 00:00:00 2001 From: Robert Szczepanski Date: Fri, 11 Oct 2024 12:31:55 +0200 Subject: [PATCH 11/11] Remove unused signal Signed-off-by: Robert Szczepanski --- design/lib/ahb_to_axi4.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/design/lib/ahb_to_axi4.sv b/design/lib/ahb_to_axi4.sv index 56ee49e7f32..a6afc9639d4 100644 --- a/design/lib/ahb_to_axi4.sv +++ b/design/lib/ahb_to_axi4.sv @@ -143,7 +143,6 @@ import el2_pkg::*; logic [2:0] ahb_hsize_q; logic ahb_hwrite_q; logic [31:0] ahb_haddr_q; - logic [63:0] ahb_hwdata_q; logic ahb_hresp_q; //Miscellaneous signals