From 662f308ba3b48c38b468c1e756d405b35657aaa0 Mon Sep 17 00:00:00 2001 From: kaede Date: Thu, 19 Sep 2024 22:41:09 +0900 Subject: [PATCH] =?UTF-8?q?DMA=E3=81=8C=E5=8B=95=E3=81=8D=E5=A7=8B?= =?UTF-8?q?=E3=82=81=E3=81=9F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .vscode/launch.json | 1 + src/bldc_motor_driver_stm32g4.rs | 73 ++++++++++++++++++++------------ src/main.rs | 8 +++- 3 files changed, 54 insertions(+), 28 deletions(-) diff --git a/.vscode/launch.json b/.vscode/launch.json index 9e91c94..ff94ecc 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -16,6 +16,7 @@ }, //!MODIFY "chip": "STM32G431RBTx", + "probe": "0483:374f", "coreConfigs": [ { //!MODIFY diff --git a/src/bldc_motor_driver_stm32g4.rs b/src/bldc_motor_driver_stm32g4.rs index 099f39e..beedc64 100644 --- a/src/bldc_motor_driver_stm32g4.rs +++ b/src/bldc_motor_driver_stm32g4.rs @@ -127,7 +127,7 @@ pub fn dma_init(perip: &Peripherals, core_perip: &mut CorePeripherals) { // For category 2 devices: // • DMAMUX channels 0 to 5 are connected to DMA1 channels 1 to 6 // • DMAMUX channels 6 to 11 are connected to DMA2 channels 1 to 6 - // DMA1 ch1 -> DMAMUX ch6 + // DMA2 ch1 -> DMAMUX ch6 perip .DMAMUX .c0cr @@ -167,20 +167,20 @@ pub fn dma_init(perip: &Peripherals, core_perip: &mut CorePeripherals) { perip.DMA1.ccr2.modify(|_, w| w.minc().set_bit()); // increment memory ptr perip.DMA1.ccr2.modify(|_, w| w.pinc().clear_bit()); // not increment periph ptr perip.DMA1.ccr2.modify(|_, w| w.mem2mem().clear_bit()); // memory-to-memory mode - perip.DMA1.ccr2.modify(|_, w| w.dir().clear_bit()); // read from peripheral - perip.DMA1.ccr2.modify(|_, w| w.teie().clear_bit()); // transfer error interrupt enable + perip.DMA1.ccr2.modify(|_, w| w.dir().set_bit()); // read from memory + perip.DMA1.ccr2.modify(|_, w| w.teie().set_bit()); // transfer error interrupt enable perip.DMA1.ccr2.modify(|_, w| w.htie().clear_bit()); // half transfer interrupt enable perip.DMA1.ccr2.modify(|_, w| w.tcie().set_bit()); // transfer complete interrupt enable // For category 2 devices: // • DMAMUX channels 0 to 5 are connected to DMA1 channels 1 to 6 // • DMAMUX channels 6 to 11 are connected to DMA2 channels 1 to 6 - // DMA1 ch1 -> DMAMUX ch6 + // DMA2 ch1 -> DMAMUX ch6 perip .DMAMUX .c1cr .modify(|_, w| unsafe { w.dmareq_id().bits(25) }); // Table.91 25:USART1_TX - perip.DMAMUX.c0cr.modify(|_, w| w.ege().set_bit()); // Enable generate event + perip.DMAMUX.c1cr.modify(|_, w| w.ege().set_bit()); // Enable generate event let uart = &perip.USART1; let uart_data_register_addr = &uart.tdr as *const _ as u32; @@ -191,10 +191,10 @@ pub fn dma_init(perip: &Peripherals, core_perip: &mut CorePeripherals) { // 割り込み設定 unsafe{ - core_perip.NVIC.set_priority(Interrupt::DMA1_CH1, 0b0); - NVIC::unmask(Interrupt::DMA1_CH1); - core_perip.NVIC.set_priority(Interrupt::DMA1_CH2, 0b0); + core_perip.NVIC.set_priority(Interrupt::DMA1_CH2, 0b10); NVIC::unmask(Interrupt::DMA1_CH2); + core_perip.NVIC.set_priority(Interrupt::USART1, 0b10); + NVIC::unmask(Interrupt::USART1); } } @@ -509,17 +509,13 @@ impl<'a> Uart1 { // Set stop bit uart.cr2.modify(|_, w| unsafe { w.stop().bits(0b00) }); - // Set stop bit - uart.cr3.modify(|_, w| w.dmat().set_bit() ); // DMA - - - // Set uart enable - uart.cr1.modify(|_, w| w.ue().set_bit()); + // // Set uart enable + // uart.cr1.modify(|_, w| w.ue().set_bit()); - // Set uart recieve enable - uart.cr1.modify(|_, w| w.re().set_bit()); - // Set uart transmitter enable - uart.cr1.modify(|_, w| w.te().set_bit()); + // // Set uart recieve enable + // uart.cr1.modify(|_, w| w.re().set_bit()); + // // Set uart transmitter enable + // uart.cr1.modify(|_, w| w.te().set_bit()); } }); } @@ -539,8 +535,21 @@ impl<'a> Uart1 { None => (), Some(perip) => { let uart = &perip.USART1; + + defmt::info!("tc: {}", uart.isr.read().tc().bits()); + defmt::info!("txe: {}", uart.isr.read().txe().bits()); + defmt::info!("tdr: {}", uart.tdr.read().bits()); + defmt::info!("len: {}", perip.DMA1.cndtr2.read().ndt().bits()); + // wait for last transmission - while uart.isr.read().tc().bit_is_clear() {} + while uart.isr.read().tc().bit_is_clear() { + // defmt::info!("tc: {}", uart.isr.read().tc().bits()); + // defmt::info!("txe: {}", uart.isr.read().txe().bits()); + // defmt::info!("tdr: {}", uart.tdr.read().bits()); + // defmt::info!("len: {}", perip.DMA1.cndtr2.read().ndt().bits()); + } + + perip.DMA1.ccr2.modify(|_, w| w.en().clear_bit()); // DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 // register. Data are loaded from an SRAM area configured using the DMA peripheral (refer to @@ -559,11 +568,11 @@ impl<'a> Uart1 { // after each TXE (or TXFNF if FIFO mode is enabled) event. perip .DMA1 - .cmar1 - .modify(|_, w| unsafe { w.ma().bits(&s as *const _ as u32) }); // memory address + .cmar2 + .modify(|_, w| unsafe { w.ma().bits(s.as_ptr() as u32) }); // memory address // 3. Configure the total number of bytes to be transferred to the DMA control register. - perip.DMA1.cndtr1.modify(|_, w| unsafe { w.ndt().bits(s.len() as u16) }); // num + perip.DMA1.cndtr2.modify(|_, w| unsafe { w.ndt().bits(s.len() as u16) }); // num // 4. Configure the channel priority in the DMA register @@ -581,15 +590,25 @@ impl<'a> Uart1 { // 7. Activate the channel in the DMA register. perip.DMA1.ccr2.modify(|_, w| w.en().set_bit()); - } - }); + // Set uart enable + uart.cr1.modify(|_, w| w.ue().set_bit()); + + // Set uart recieve enable + uart.cr1.modify(|_, w| w.re().set_bit()); + // Set uart transmitter enable + uart.cr1.modify(|_, w| w.te().set_bit()); + uart.cr3.modify(|_, w| w.dmat().set_bit() ); // DMA + + defmt::info!("2tc: {}", uart.isr.read().tc().bits()); + defmt::info!("2txe: {}", uart.isr.read().txe().bits()); + defmt::info!("2tdr: {}", uart.tdr.read().bits()); + defmt::info!("2len: {}", perip.DMA1.cndtr2.read().ndt().bits()); - for c in s.bytes() { - self.putc(c); - } + } + }); } } diff --git a/src/main.rs b/src/main.rs index e72f6c4..bd48476 100644 --- a/src/main.rs +++ b/src/main.rs @@ -52,6 +52,7 @@ fn DMA1_CH1(){ static mut TIM3_COUNT: u32 = 0; // `TIM3_COUNT` has type `&mut u32` and it's safe to use *TIM3_COUNT += 1; + // defmt::info!("dma1 ch1!"); let mut tim_count = 0; free(|cs| { match bldc_motor_driver_stm32g4::G_PERIPHERAL @@ -82,11 +83,14 @@ fn DMA1_CH1(){ } } }); + // defmt::info!("dma1 ch1! finish"); } #[interrupt] fn DMA1_CH2(){ + defmt::info!("dma1 ch2!"); + free(|cs| { match bldc_motor_driver_stm32g4::G_PERIPHERAL .borrow(cs) @@ -106,6 +110,7 @@ fn DMA1_CH2(){ } } }); + defmt::info!("dma1 ch2! finish"); } #[interrupt] @@ -279,7 +284,6 @@ fn main() -> ! { } }); - uart.put_str("Hello, from DMA"); // write!(uart, "{}, {:4}, {:4}", calib_count, deg, rad).unwrap(); // write!(uart, "\"tv\": {:4}\r\n", tv,).unwrap(); @@ -296,6 +300,8 @@ fn main() -> ! { // ) // .unwrap(); + defmt::info!("dma start"); + uart.put_str("Hello, from DMA"); defmt::info!("diff: {}", diff_count); // // floatのまま送るとFLASHをバカほど食うのでcastする