From 8f4fc795d4f34da907933b3f6692de227784c7dd Mon Sep 17 00:00:00 2001 From: XxChang Date: Mon, 4 Nov 2024 18:16:46 +0800 Subject: [PATCH 1/7] add dvp supports --- data/chips/CH32V307VCT6.yaml | 1 + data/interrupts/CH32V3.yaml | 2 + data/peripherals/V3x_DVP.yaml | 49 ++++++ data/registers/dvp_v3.yaml | 283 ++++++++++++++++++++++++++++++++++ 4 files changed, 335 insertions(+) create mode 100644 data/peripherals/V3x_DVP.yaml create mode 100644 data/registers/dvp_v3.yaml diff --git a/data/chips/CH32V307VCT6.yaml b/data/chips/CH32V307VCT6.yaml index 4e13a60..f398e6c 100644 --- a/data/chips/CH32V307VCT6.yaml +++ b/data/chips/CH32V307VCT6.yaml @@ -76,6 +76,7 @@ cores: - "../peripherals/FV2x_V3x_SDIO.yaml" - "../peripherals/FV2x_V3x_CAN1.yaml" - "../peripherals/FV2x_V3x_CAN2.yaml" + - "../peripherals/V3x_DVP.yaml" include_interrupts: "../interrupts/CH32V3.yaml" include_dma_channels: diff --git a/data/interrupts/CH32V3.yaml b/data/interrupts/CH32V3.yaml index a6b3e95..65e2d17 100644 --- a/data/interrupts/CH32V3.yaml +++ b/data/interrupts/CH32V3.yaml @@ -127,6 +127,8 @@ OTG_FS: 83 USBHS_WKUP: 84 # 85 - USBHS USBHS: 85 +# 86 - DVP global interrupt +DVP: 86 # 87 - USART6 global interrupt USART6: 87 # 88 - USART7 global interrupt diff --git a/data/peripherals/V3x_DVP.yaml b/data/peripherals/V3x_DVP.yaml new file mode 100644 index 0000000..72755cf --- /dev/null +++ b/data/peripherals/V3x_DVP.yaml @@ -0,0 +1,49 @@ +- name: DVP + address: 50050000 + registers: + kind: dvp + version: v3 + block: DVP + rcc: + bus_clock: HCLK + kernel_clock: HCLK + enable: + register: AHBPCENR + field: DVP_EN + reset: + register: AHBRSTR + field: DVPRST + interrupts: + - signal: GLOBAL + interrupt: DVP + pins: + - pin: PA4 + signal: HSYNC + - pin: PA5 + signal: VSYNC + - pin: PA6 + signal: PCLK + - pin: PA9 + signal: D0 + - pin: PA10 + signal: D1 + - pin: PC8 + signal: D2 + - pin: PC9 + signal: D3 + - pin: PC11 + signal: D4 + - pin: PB3 + signal: D5 + - pin: PB8 + signal: D6 + - pin: PB9 + signal: D7 + - pin: PC10 + signal: D8 + - pin: PC12 + signal: D9 + - pin: PD6 + signal: D10 + - pin: PD2 + signal: D11 diff --git a/data/registers/dvp_v3.yaml b/data/registers/dvp_v3.yaml new file mode 100644 index 0000000..b472aa3 --- /dev/null +++ b/data/registers/dvp_v3.yaml @@ -0,0 +1,283 @@ +block/DVP: + description: Digital Video Port. + items: + - name: CR0 + description: Digital Video control register. (DVP_CR0). + byte_offset: 0 + bit_size: 8 + fieldset: CR0 + - name: CR1 + description: Digital Video control register. (DVP_CR1). + byte_offset: 1 + bit_size: 8 + fieldset: CR1 + - name: IER + description: Digital Video Interrupt register. (DVP_IER). + byte_offset: 2 + bit_size: 8 + fieldset: IER + - name: ROW_NUM + description: Image line count configuration register. (DVP_ROW_NUM). + byte_offset: 4 + bit_size: 16 + fieldset: ROW_NUM + - name: COL_NUM + description: Image column number configuration register. (DVP_COL_NUM). + byte_offset: 6 + bit_size: 16 + fieldset: COL_NUM + - name: DMA_BUF0 + description: Digital Video DMA address register. (DVP_DMA_BUF0). + byte_offset: 8 + fieldset: DMA_BUF0 + - name: DMA_BUF1 + description: Digital Video DMA address register. (DVP_DMA_BUF1). + byte_offset: 12 + fieldset: DMA_BUF1 + - name: IFR + description: Digital Video Flag register. (DVP_IFR). + byte_offset: 16 + bit_size: 8 + fieldset: IFR + - name: STATUS + description: Digital Video STATUS register. (DVP_STATUS). + byte_offset: 17 + access: Read + bit_size: 8 + fieldset: STATUS + - name: ROW_CNT + description: Digital Video line counter register. (DVP_ROW_CNT). + byte_offset: 20 + access: Read + bit_size: 16 + fieldset: ROW_CNT + - name: HOFFCNT + description: Digital Video horizontal displacement register. (DVP_HOFFCNT). + byte_offset: 24 + bit_size: 16 + fieldset: HOFFCNT + - name: VST + description: Digital Video line number register. (DVP_VST). + byte_offset: 26 + bit_size: 16 + fieldset: VST + - name: CAPCNT + description: Digital Video Capture count register. (DVP_CAPCNT). + byte_offset: 28 + bit_size: 16 + fieldset: CAPCNT + - name: VLINE + description: Digital Video Vertical line count register. (DVP_VLINE). + byte_offset: 30 + bit_size: 16 + fieldset: VLINE + - name: DR + description: Digital Video Data register. (DVP_DR). + byte_offset: 32 + access: Read + fieldset: DR +fieldset/CAPCNT: + description: Digital Video Capture count register. (DVP_CAPCNT). + bit_size: 16 + fields: + - name: RB_DVP_CAPCNT + description: Number of PCLK cycles captured by clipping window. + bit_offset: 0 + bit_size: 16 +fieldset/COL_NUM: + description: Image column number configuration register. (DVP_COL_NUM). + bit_size: 16 + fields: + - name: RB_DVP_COL_NUM + description: Number of PCLK cycles for row data. + bit_offset: 0 + bit_size: 16 +fieldset/CR0: + description: Digital Video control register. (DVP_CR0). + bit_size: 8 + fields: + - name: RB_DVP_ENABLE + description: DVP enable. + bit_offset: 0 + bit_size: 1 + - name: RB_DVP_V_POLAR + description: DVP VSYNC polarity control. + bit_offset: 1 + bit_size: 1 + - name: RB_DVP_H_POLAR + description: DVP HSYNC polarity control. + bit_offset: 2 + bit_size: 1 + - name: RB_DVP_P_POLAR + description: DVP PCLK polarity control. + bit_offset: 3 + bit_size: 1 + - name: RB_DVP_MSK_DAT_MOD + description: DVP data mode. + bit_offset: 4 + bit_size: 2 + - name: RB_DVP_JPEG + description: DVP JPEG mode. + bit_offset: 6 + bit_size: 1 +fieldset/CR1: + description: Digital Video control register. (DVP_CR1). + bit_size: 8 + fields: + - name: RB_DVP_DMA_EN + description: DVP dma enable. + bit_offset: 0 + bit_size: 1 + - name: RB_DVP_ALL_CLR + description: DVP all clear. + bit_offset: 1 + bit_size: 1 + - name: RB_DVP_RCV_CLR + description: DVP receive logic clear. + bit_offset: 2 + bit_size: 1 + - name: RB_DVP_BUF_TOG + description: DVP bug toggle by software. + bit_offset: 3 + bit_size: 1 + - name: RB_DVP_CM + description: DVP capture mode. + bit_offset: 4 + bit_size: 1 + - name: RB_DVP_CROP + description: DVP Crop feature enable. + bit_offset: 5 + bit_size: 1 + - name: RB_DVP_FCRC + description: DVP frame capture rate control. + bit_offset: 6 + bit_size: 2 +fieldset/DMA_BUF0: + description: Digital Video DMA address register. (DVP_DMA_BUF0). + fields: + - name: RB_DVP_DMA_BUF0 + description: DMA receive address 0. + bit_offset: 0 + bit_size: 17 +fieldset/DMA_BUF1: + description: Digital Video DMA address register. (DVP_DMA_BUF1). + fields: + - name: RB_DVP_DMA_BUF1 + description: DMA receive address 1. + bit_offset: 0 + bit_size: 17 +fieldset/DR: + description: Digital Video Data register. (DVP_DR). + fields: + - name: RB_DVP_DR + description: Prevent DMA overflow. + bit_offset: 0 + bit_size: 32 +fieldset/HOFFCNT: + description: Digital Video horizontal displacement register. (DVP_HOFFCNT). + bit_size: 16 + fields: + - name: RB_DVP_HOFFCNT + description: Number of PCLK cycles for row data. + bit_offset: 0 + bit_size: 16 +fieldset/IER: + description: Digital Video Interrupt register. (DVP_IER). + bit_size: 8 + fields: + - name: RB_DVP_IE_STR_FRM + description: DVP frame start interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: RB_DVP_IE_ROW_DONE + description: DVP row received done interrupt enable. + bit_offset: 1 + bit_size: 1 + - name: RB_DVP_IE_FRM_DONE + description: DVP frame received done interrupt enable. + bit_offset: 2 + bit_size: 1 + - name: RB_DVP_IE_FIFO_OV + description: DVP receive fifo overflow interrupt enable. + bit_offset: 3 + bit_size: 1 + - name: RB_DVP_IE_STP_FRM + description: DVP frame stop interrupt enable. + bit_offset: 4 + bit_size: 1 +fieldset/IFR: + description: Digital Video Flag register. (DVP_IFR). + bit_size: 8 + fields: + - name: RB_DVP_IF_STR_FRM + description: DVP frame start interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: RB_DVP_IF_ROW_DONE + description: DVP row received done interrupt enable. + bit_offset: 1 + bit_size: 1 + - name: RB_DVP_IF_FRM_DONE + description: DVP frame received done interrupt enable. + bit_offset: 2 + bit_size: 1 + - name: RB_DVP_IF_FIFO_OV + description: DVP receive fifo overflow interrupt enable. + bit_offset: 3 + bit_size: 1 + - name: RB_DVP_IF_STP_FRM + description: DVP frame stop interrupt enable. + bit_offset: 4 + bit_size: 1 +fieldset/ROW_CNT: + description: Digital Video line counter register. (DVP_ROW_CNT). + bit_size: 16 + fields: + - name: RB_DVP_ROW_CNT + description: The number of rows of frame image data. + bit_offset: 0 + bit_size: 16 +fieldset/ROW_NUM: + description: Image line count configuration register. (DVP_ROW_NUM). + bit_size: 16 + fields: + - name: RB_DVP_ROW_NUM + description: The number of rows of frame image data. + bit_offset: 0 + bit_size: 16 +fieldset/STATUS: + description: Digital Video STATUS register. (DVP_STATUS). + bit_size: 8 + fields: + - name: RB_DVP_FIFO_RDY + description: DVP frame start interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: RB_DVP_FIFO_FULL + description: DVP row received done interrupt enable. + bit_offset: 1 + bit_size: 1 + - name: RB_DVP_FIFO_OV + description: DVP frame received done interrupt enable. + bit_offset: 2 + bit_size: 1 + - name: RB_DVP_MSK_FIFO_CNT + description: DVP receive fifo overflow interrupt enable. + bit_offset: 4 + bit_size: 3 +fieldset/VLINE: + description: Digital Video Vertical line count register. (DVP_VLINE). + bit_size: 16 + fields: + - name: RB_DVP_VLINE + description: Crop the number of rows captured by window. + bit_offset: 0 + bit_size: 16 +fieldset/VST: + description: Digital Video line number register. (DVP_VST). + bit_size: 16 + fields: + - name: RB_DVP_VST + description: The number of lines captured by the image. + bit_offset: 0 + bit_size: 16 From d426b5d60c16fac1a3ab2d9233d176e4f2d9a465 Mon Sep 17 00:00:00 2001 From: XxChang Date: Thu, 7 Nov 2024 19:06:14 +0800 Subject: [PATCH 2/7] fix address bug --- data/peripherals/V3x_DVP.yaml | 4 +- data/registers/dvp_v3.yaml | 79 +++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+), 2 deletions(-) diff --git a/data/peripherals/V3x_DVP.yaml b/data/peripherals/V3x_DVP.yaml index 72755cf..ccbd329 100644 --- a/data/peripherals/V3x_DVP.yaml +++ b/data/peripherals/V3x_DVP.yaml @@ -1,5 +1,5 @@ - name: DVP - address: 50050000 + address: 0x50050000 registers: kind: dvp version: v3 @@ -33,7 +33,7 @@ signal: D3 - pin: PC11 signal: D4 - - pin: PB3 + - pin: PB6 signal: D5 - pin: PB8 signal: D6 diff --git a/data/registers/dvp_v3.yaml b/data/registers/dvp_v3.yaml index b472aa3..76694f9 100644 --- a/data/registers/dvp_v3.yaml +++ b/data/registers/dvp_v3.yaml @@ -104,22 +104,27 @@ fieldset/CR0: description: DVP VSYNC polarity control. bit_offset: 1 bit_size: 1 + enum: VSYNC_POLARITY - name: RB_DVP_H_POLAR description: DVP HSYNC polarity control. bit_offset: 2 bit_size: 1 + enum: HSYNC_POLARITY - name: RB_DVP_P_POLAR description: DVP PCLK polarity control. bit_offset: 3 bit_size: 1 + enum: PCLK_POLARITY - name: RB_DVP_MSK_DAT_MOD description: DVP data mode. bit_offset: 4 bit_size: 2 + enum: DATA_MODE - name: RB_DVP_JPEG description: DVP JPEG mode. bit_offset: 6 bit_size: 1 + enum: CAPTURE_MODE fieldset/CR1: description: Digital Video control register. (DVP_CR1). bit_size: 8 @@ -152,6 +157,7 @@ fieldset/CR1: description: DVP frame capture rate control. bit_offset: 6 bit_size: 2 + enum: CAPTURE_RATE fieldset/DMA_BUF0: description: Digital Video DMA address register. (DVP_DMA_BUF0). fields: @@ -281,3 +287,76 @@ fieldset/VST: description: The number of lines captured by the image. bit_offset: 0 bit_size: 16 + +enum/CAPTURE_RATE: + bit_size: 2 + description: Capture rate + variants: + - name: ALL + description: Capture all frames. + value: 0b00 + - name: HALF + description: One frame per Two Captures. + value: 0b01 + - name: QUARTER + description: One frame per Four Captures. + value: 0b10 + +enum/CAPTURE_MODE: + bit_size: 1 + description: Capture mode. + variants: + - name: CAPTURE_MODE_RAW + description: Raw data capture mode. + value: 0b0 + - name: CAPTURE_MODE_JPEG + description: JPEG data capture mode. + value: 0b1 + +enum/DATA_MODE: + bit_size: 2 + description: Data mode. + variants: + - name: DATA_MODE_8BIT + description: 8-bit data mode. + value: 0b00 + - name: DATA_MODE_10BIT + description: 10-bit data mode. + value: 0b01 + - name: DATA_MODE_12BIT + description: 12-bit data mode. + value: 0b10 + +enum/PCLK_POLARITY: + bit_size: 1 + description: PCLK polarity control. + variants: + - name: PCLK_POLARITY_FALLING_EDGE + description: PCLK falling edge. + value: 0b1 + - name: PCLK_POLARITY_RISING_EDGE + description: PCLK rising edge. + value: 0b0 + +enum/HSYNC_POLARITY: + bit_size: 1 + description: HSYNC polarity control. + variants: + - name: HSYNC_POLARITY_LOW + description: HSYNC active low. + value: 0b1 + - name: HSYNC_POLARITY_HIGH + description: HSYNC active high. + value: 0b0 + +enum/VSYNC_POLARITY: + bit_size: 1 + description: VSYNC polarity control. + variants: + - name: VSYNC_POLARITY_LOW + description: VSYNC active low. + value: 0b0 + - name: VSYNC_POLARITY_HIGH + description: VSYNC active high. + value: 0b1 + \ No newline at end of file From f19e9efa690a1453e24222f41e873839ac03b095 Mon Sep 17 00:00:00 2001 From: XxChang Date: Thu, 7 Nov 2024 19:12:26 +0800 Subject: [PATCH 3/7] fix typo --- data/peripherals/V3x_DVP.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/data/peripherals/V3x_DVP.yaml b/data/peripherals/V3x_DVP.yaml index ccbd329..f28ab1d 100644 --- a/data/peripherals/V3x_DVP.yaml +++ b/data/peripherals/V3x_DVP.yaml @@ -46,4 +46,4 @@ - pin: PD6 signal: D10 - pin: PD2 - signal: D11 + signal: D11 \ No newline at end of file From 21ed16f969dca589d045938477799d639eb57b9d Mon Sep 17 00:00:00 2001 From: XxChang Date: Thu, 7 Nov 2024 19:13:48 +0800 Subject: [PATCH 4/7] fix typo --- data/peripherals/V3x_DVP.yaml | 2 +- data/registers/dvp_v3.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/data/peripherals/V3x_DVP.yaml b/data/peripherals/V3x_DVP.yaml index f28ab1d..ccbd329 100644 --- a/data/peripherals/V3x_DVP.yaml +++ b/data/peripherals/V3x_DVP.yaml @@ -46,4 +46,4 @@ - pin: PD6 signal: D10 - pin: PD2 - signal: D11 \ No newline at end of file + signal: D11 diff --git a/data/registers/dvp_v3.yaml b/data/registers/dvp_v3.yaml index 76694f9..650aad1 100644 --- a/data/registers/dvp_v3.yaml +++ b/data/registers/dvp_v3.yaml @@ -359,4 +359,4 @@ enum/VSYNC_POLARITY: - name: VSYNC_POLARITY_HIGH description: VSYNC active high. value: 0b1 - \ No newline at end of file + \ No newline at end of file From 9741801c2700db4e6deadaa8b2231a9fd48d0346 Mon Sep 17 00:00:00 2001 From: XxChang Date: Thu, 7 Nov 2024 19:14:23 +0800 Subject: [PATCH 5/7] fix typo --- data/registers/dvp_v3.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/data/registers/dvp_v3.yaml b/data/registers/dvp_v3.yaml index 650aad1..6042828 100644 --- a/data/registers/dvp_v3.yaml +++ b/data/registers/dvp_v3.yaml @@ -359,4 +359,3 @@ enum/VSYNC_POLARITY: - name: VSYNC_POLARITY_HIGH description: VSYNC active high. value: 0b1 - \ No newline at end of file From 0fe1263597449d289268a60018993e2fb35a845d Mon Sep 17 00:00:00 2001 From: XxChang Date: Fri, 8 Nov 2024 08:49:55 +0800 Subject: [PATCH 6/7] delete RB_DVP_ prefix --- data/registers/dvp_v3.yaml | 74 +++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/data/registers/dvp_v3.yaml b/data/registers/dvp_v3.yaml index 6042828..3d80b55 100644 --- a/data/registers/dvp_v3.yaml +++ b/data/registers/dvp_v3.yaml @@ -80,7 +80,7 @@ fieldset/CAPCNT: description: Digital Video Capture count register. (DVP_CAPCNT). bit_size: 16 fields: - - name: RB_DVP_CAPCNT + - name: CAPCNT description: Number of PCLK cycles captured by clipping window. bit_offset: 0 bit_size: 16 @@ -88,7 +88,7 @@ fieldset/COL_NUM: description: Image column number configuration register. (DVP_COL_NUM). bit_size: 16 fields: - - name: RB_DVP_COL_NUM + - name: COL_NUM description: Number of PCLK cycles for row data. bit_offset: 0 bit_size: 16 @@ -96,31 +96,31 @@ fieldset/CR0: description: Digital Video control register. (DVP_CR0). bit_size: 8 fields: - - name: RB_DVP_ENABLE + - name: ENABLE description: DVP enable. bit_offset: 0 bit_size: 1 - - name: RB_DVP_V_POLAR + - name: V_POLAR description: DVP VSYNC polarity control. bit_offset: 1 bit_size: 1 enum: VSYNC_POLARITY - - name: RB_DVP_H_POLAR + - name: H_POLAR description: DVP HSYNC polarity control. bit_offset: 2 bit_size: 1 enum: HSYNC_POLARITY - - name: RB_DVP_P_POLAR + - name: P_POLAR description: DVP PCLK polarity control. bit_offset: 3 bit_size: 1 enum: PCLK_POLARITY - - name: RB_DVP_MSK_DAT_MOD + - name: MSK_DAT_MOD description: DVP data mode. bit_offset: 4 bit_size: 2 enum: DATA_MODE - - name: RB_DVP_JPEG + - name: JPEG description: DVP JPEG mode. bit_offset: 6 bit_size: 1 @@ -129,31 +129,31 @@ fieldset/CR1: description: Digital Video control register. (DVP_CR1). bit_size: 8 fields: - - name: RB_DVP_DMA_EN + - name: DMA_EN description: DVP dma enable. bit_offset: 0 bit_size: 1 - - name: RB_DVP_ALL_CLR + - name: ALL_CLR description: DVP all clear. bit_offset: 1 bit_size: 1 - - name: RB_DVP_RCV_CLR + - name: RCV_CLR description: DVP receive logic clear. bit_offset: 2 bit_size: 1 - - name: RB_DVP_BUF_TOG + - name: BUF_TOG description: DVP bug toggle by software. bit_offset: 3 bit_size: 1 - - name: RB_DVP_CM + - name: CM description: DVP capture mode. bit_offset: 4 bit_size: 1 - - name: RB_DVP_CROP + - name: CROP description: DVP Crop feature enable. bit_offset: 5 bit_size: 1 - - name: RB_DVP_FCRC + - name: FCRC description: DVP frame capture rate control. bit_offset: 6 bit_size: 2 @@ -161,21 +161,21 @@ fieldset/CR1: fieldset/DMA_BUF0: description: Digital Video DMA address register. (DVP_DMA_BUF0). fields: - - name: RB_DVP_DMA_BUF0 + - name: DMA_BUF0 description: DMA receive address 0. bit_offset: 0 bit_size: 17 fieldset/DMA_BUF1: description: Digital Video DMA address register. (DVP_DMA_BUF1). fields: - - name: RB_DVP_DMA_BUF1 + - name: DMA_BUF1 description: DMA receive address 1. bit_offset: 0 bit_size: 17 fieldset/DR: description: Digital Video Data register. (DVP_DR). fields: - - name: RB_DVP_DR + - name: DR description: Prevent DMA overflow. bit_offset: 0 bit_size: 32 @@ -183,7 +183,7 @@ fieldset/HOFFCNT: description: Digital Video horizontal displacement register. (DVP_HOFFCNT). bit_size: 16 fields: - - name: RB_DVP_HOFFCNT + - name: HOFFCNT description: Number of PCLK cycles for row data. bit_offset: 0 bit_size: 16 @@ -191,23 +191,23 @@ fieldset/IER: description: Digital Video Interrupt register. (DVP_IER). bit_size: 8 fields: - - name: RB_DVP_IE_STR_FRM + - name: IE_STR_FRM description: DVP frame start interrupt enable. bit_offset: 0 bit_size: 1 - - name: RB_DVP_IE_ROW_DONE + - name: IE_ROW_DONE description: DVP row received done interrupt enable. bit_offset: 1 bit_size: 1 - - name: RB_DVP_IE_FRM_DONE + - name: IE_FRM_DONE description: DVP frame received done interrupt enable. bit_offset: 2 bit_size: 1 - - name: RB_DVP_IE_FIFO_OV + - name: IE_FIFO_OV description: DVP receive fifo overflow interrupt enable. bit_offset: 3 bit_size: 1 - - name: RB_DVP_IE_STP_FRM + - name: IE_STP_FRM description: DVP frame stop interrupt enable. bit_offset: 4 bit_size: 1 @@ -215,23 +215,23 @@ fieldset/IFR: description: Digital Video Flag register. (DVP_IFR). bit_size: 8 fields: - - name: RB_DVP_IF_STR_FRM + - name: IF_STR_FRM description: DVP frame start interrupt enable. bit_offset: 0 bit_size: 1 - - name: RB_DVP_IF_ROW_DONE + - name: IF_ROW_DONE description: DVP row received done interrupt enable. bit_offset: 1 bit_size: 1 - - name: RB_DVP_IF_FRM_DONE + - name: IF_FRM_DONE description: DVP frame received done interrupt enable. bit_offset: 2 bit_size: 1 - - name: RB_DVP_IF_FIFO_OV + - name: IF_FIFO_OV description: DVP receive fifo overflow interrupt enable. bit_offset: 3 bit_size: 1 - - name: RB_DVP_IF_STP_FRM + - name: IF_STP_FRM description: DVP frame stop interrupt enable. bit_offset: 4 bit_size: 1 @@ -239,7 +239,7 @@ fieldset/ROW_CNT: description: Digital Video line counter register. (DVP_ROW_CNT). bit_size: 16 fields: - - name: RB_DVP_ROW_CNT + - name: ROW_CNT description: The number of rows of frame image data. bit_offset: 0 bit_size: 16 @@ -247,7 +247,7 @@ fieldset/ROW_NUM: description: Image line count configuration register. (DVP_ROW_NUM). bit_size: 16 fields: - - name: RB_DVP_ROW_NUM + - name: ROW_NUM description: The number of rows of frame image data. bit_offset: 0 bit_size: 16 @@ -255,19 +255,19 @@ fieldset/STATUS: description: Digital Video STATUS register. (DVP_STATUS). bit_size: 8 fields: - - name: RB_DVP_FIFO_RDY + - name: FIFO_RDY description: DVP frame start interrupt enable. bit_offset: 0 bit_size: 1 - - name: RB_DVP_FIFO_FULL + - name: FIFO_FULL description: DVP row received done interrupt enable. bit_offset: 1 bit_size: 1 - - name: RB_DVP_FIFO_OV + - name: FIFO_OV description: DVP frame received done interrupt enable. bit_offset: 2 bit_size: 1 - - name: RB_DVP_MSK_FIFO_CNT + - name: MSK_FIFO_CNT description: DVP receive fifo overflow interrupt enable. bit_offset: 4 bit_size: 3 @@ -275,7 +275,7 @@ fieldset/VLINE: description: Digital Video Vertical line count register. (DVP_VLINE). bit_size: 16 fields: - - name: RB_DVP_VLINE + - name: VLINE description: Crop the number of rows captured by window. bit_offset: 0 bit_size: 16 @@ -283,7 +283,7 @@ fieldset/VST: description: Digital Video line number register. (DVP_VST). bit_size: 16 fields: - - name: RB_DVP_VST + - name: VST description: The number of lines captured by the image. bit_offset: 0 bit_size: 16 From f6ae54386c81cc6fd3d9266067355c07e61834d1 Mon Sep 17 00:00:00 2001 From: Andelf Date: Sat, 9 Nov 2024 21:26:23 +0800 Subject: [PATCH 7/7] chore: rm enum prefix --- data/registers/dvp_v3.yaml | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/data/registers/dvp_v3.yaml b/data/registers/dvp_v3.yaml index 3d80b55..fadfc4a 100644 --- a/data/registers/dvp_v3.yaml +++ b/data/registers/dvp_v3.yaml @@ -306,10 +306,10 @@ enum/CAPTURE_MODE: bit_size: 1 description: Capture mode. variants: - - name: CAPTURE_MODE_RAW + - name: RAW description: Raw data capture mode. value: 0b0 - - name: CAPTURE_MODE_JPEG + - name: JPEG description: JPEG data capture mode. value: 0b1 @@ -317,13 +317,13 @@ enum/DATA_MODE: bit_size: 2 description: Data mode. variants: - - name: DATA_MODE_8BIT + - name: _8BIT description: 8-bit data mode. value: 0b00 - - name: DATA_MODE_10BIT + - name: _10BIT description: 10-bit data mode. value: 0b01 - - name: DATA_MODE_12BIT + - name: _12BIT description: 12-bit data mode. value: 0b10 @@ -331,10 +331,10 @@ enum/PCLK_POLARITY: bit_size: 1 description: PCLK polarity control. variants: - - name: PCLK_POLARITY_FALLING_EDGE + - name: FALLING_EDGE description: PCLK falling edge. value: 0b1 - - name: PCLK_POLARITY_RISING_EDGE + - name: RISING_EDGE description: PCLK rising edge. value: 0b0 @@ -342,10 +342,10 @@ enum/HSYNC_POLARITY: bit_size: 1 description: HSYNC polarity control. variants: - - name: HSYNC_POLARITY_LOW + - name: ACTIVE_LOW description: HSYNC active low. value: 0b1 - - name: HSYNC_POLARITY_HIGH + - name: ACTIVE_HIGH description: HSYNC active high. value: 0b0 @@ -353,9 +353,9 @@ enum/VSYNC_POLARITY: bit_size: 1 description: VSYNC polarity control. variants: - - name: VSYNC_POLARITY_LOW + - name: ACTIVE_LOW description: VSYNC active low. value: 0b0 - - name: VSYNC_POLARITY_HIGH + - name: ACTIVE_HIGH description: VSYNC active high. value: 0b1