diff --git a/data/chips/CH32V303RCT6.yaml b/data/chips/CH32V303RCT6.yaml
index 9bd91d3..f07eed3 100644
--- a/data/chips/CH32V303RCT6.yaml
+++ b/data/chips/CH32V303RCT6.yaml
@@ -62,6 +62,7 @@ cores:
       - "../peripherals/FV2x_V3x_I2C2.yaml"
       - "../peripherals/FV2x_V3x_RNG.yaml"
       - "../peripherals/FV2x_V3x_DAC.yaml"
+      - "../peripherals/FV2x_V3x_SDIO.yaml"
 
     include_interrupts: "../interrupts/CH32V3.yaml"
     include_dma_channels:
diff --git a/data/chips/CH32V303VCT6.yaml b/data/chips/CH32V303VCT6.yaml
index f87aebb..298dddc 100644
--- a/data/chips/CH32V303VCT6.yaml
+++ b/data/chips/CH32V303VCT6.yaml
@@ -63,6 +63,7 @@ cores:
       - "../peripherals/FV2x_V3x_I2C2.yaml"
       - "../peripherals/FV2x_V3x_RNG.yaml"
       - "../peripherals/FV2x_V3x_DAC.yaml"
+      - "../peripherals/FV2x_V3x_SDIO.yaml"
 
     include_interrupts: "../interrupts/CH32V3.yaml"
     include_dma_channels:
diff --git a/data/chips/CH32V305GBU6.yaml b/data/chips/CH32V305GBU6.yaml
index 733c229..0ff720d 100644
--- a/data/chips/CH32V305GBU6.yaml
+++ b/data/chips/CH32V305GBU6.yaml
@@ -64,6 +64,7 @@ cores:
       - "../peripherals/FV2x_V3x_RNG.yaml"
       - "../peripherals/FV2x_V3x_USBHS.yaml"
       - "../peripherals/FV2x_V3x_DAC.yaml"
+      - "../peripherals/FV2x_V3x_SDIO.yaml"
 
     include_interrupts: "../interrupts/CH32V3.yaml"
     include_dma_channels:
diff --git a/data/chips/CH32V305RBT6.yaml b/data/chips/CH32V305RBT6.yaml
index 9ea40e0..20c2928 100644
--- a/data/chips/CH32V305RBT6.yaml
+++ b/data/chips/CH32V305RBT6.yaml
@@ -63,6 +63,7 @@ cores:
       - "../peripherals/FV2x_V3x_RNG.yaml"
       - "../peripherals/FV2x_V3x_USBHS.yaml"
       - "../peripherals/FV2x_V3x_DAC.yaml"
+      - "../peripherals/FV2x_V3x_SDIO.yaml"
 
     include_interrupts: "../interrupts/CH32V3.yaml"
     include_dma_channels:
diff --git a/data/chips/CH32V307RCT6.yaml b/data/chips/CH32V307RCT6.yaml
index c9d2419..4585b94 100644
--- a/data/chips/CH32V307RCT6.yaml
+++ b/data/chips/CH32V307RCT6.yaml
@@ -70,6 +70,7 @@ cores:
       - "../peripherals/FV2x_V3x_RNG.yaml"
       - "../peripherals/FV2x_V3x_USBHS.yaml"
       - "../peripherals/FV2x_V3x_DAC.yaml"
+      - "../peripherals/FV2x_V3x_SDIO.yaml"
 
     include_interrupts: "../interrupts/CH32V3.yaml"
     include_dma_channels:
diff --git a/data/chips/CH32V307VCT6.yaml b/data/chips/CH32V307VCT6.yaml
index 60fc039..cfee6ad 100644
--- a/data/chips/CH32V307VCT6.yaml
+++ b/data/chips/CH32V307VCT6.yaml
@@ -72,6 +72,7 @@ cores:
       - "../peripherals/FV2x_V3x_RNG.yaml"
       - "../peripherals/FV2x_V3x_USBHS.yaml"
       - "../peripherals/FV2x_V3x_DAC.yaml"
+      - "../peripherals/FV2x_V3x_SDIO.yaml"
 
     include_interrupts: "../interrupts/CH32V3.yaml"
     include_dma_channels:
diff --git a/data/chips/CH32V307WCU6.yaml b/data/chips/CH32V307WCU6.yaml
index f560379..b7eb612 100644
--- a/data/chips/CH32V307WCU6.yaml
+++ b/data/chips/CH32V307WCU6.yaml
@@ -70,6 +70,7 @@ cores:
       - "../peripherals/FV2x_V3x_RNG.yaml"
       - "../peripherals/FV2x_V3x_USBHS.yaml"
       - "../peripherals/FV2x_V3x_DAC.yaml"
+      - "../peripherals/FV2x_V3x_SDIO.yaml"
 
     include_interrupts: "../interrupts/CH32V3.yaml"
     include_dma_channels:
diff --git a/data/peripherals/FV2x_V3x_SDIO.yaml b/data/peripherals/FV2x_V3x_SDIO.yaml
new file mode 100644
index 0000000..21133d4
--- /dev/null
+++ b/data/peripherals/FV2x_V3x_SDIO.yaml
@@ -0,0 +1,38 @@
+- name: SDIO
+  address: 0x40012400
+  registers:
+    kind: sdio
+    version: v3
+    block: SDIO
+  rcc:
+    bus_clock: HCLK1
+    kernel_clock: HCLK1
+    enable:
+      register: AHBPCENR
+      field: SDIOEN
+  interrupts:
+    - signal: GLOBAL
+      interrupt: SDIO
+  pins:
+    - pin: PC8
+      signal: D0
+    - pin: PC9
+      signal: D1
+    - pin: PC10
+      signal: D2
+    - pin: PC11
+      signal: D3
+    - pin: PB8
+      signal: D4
+    - pin: PB9
+      signal: D5
+    - pin: PC6
+      signal: D6
+    - pin: PC7
+      signal: D7
+    - pin: PC12
+      signal: CK
+    - pin: PD2
+      signal: CMD
+
+
diff --git a/data/registers/sdio_v3.yaml b/data/registers/sdio_v3.yaml
new file mode 100644
index 0000000..c37fdef
--- /dev/null
+++ b/data/registers/sdio_v3.yaml
@@ -0,0 +1,496 @@
+block/SDIO:
+  description: SDIO, Secure digital input/output interface.
+  items:
+  - name: POWER
+    description: 'Bits 1:0 = PWRCTRL: Power supply control bits.'
+    byte_offset: 0
+    fieldset: POWER
+  - name: CLKCR
+    description: SDI clock control register (SDIO_CLKCR).
+    byte_offset: 4
+    fieldset: CLKCR
+  - name: ARG
+    description: 'Bits 31:0 = : Command argument.'
+    byte_offset: 8
+    fieldset: ARG
+  - name: CMD
+    description: SDIO command register (SDIO_CMD).
+    byte_offset: 12
+    fieldset: CMD
+  - name: RESPCMD
+    description: SDIO command register.
+    byte_offset: 16
+    access: Read
+    fieldset: RESPCMD
+  - name: RESP
+    description: Bits 31:0 = CARDSTATUS1.
+    byte_offset: 20
+    access: Read
+    arrary:
+      size: 4
+      stride: 4
+    fieldset: RESP
+  - name: DTIMER
+    description: 'Bits 31:0 = DATATIME: Data timeout period.'
+    byte_offset: 36
+    fieldset: DTIMER
+  - name: DLEN
+    description: 'Bits 24:0 = DATALENGTH: Data length value.'
+    byte_offset: 40
+    fieldset: DLEN
+  - name: DCTRL
+    description: SDIO data control register (SDIO_DCTRL).
+    byte_offset: 44
+    fieldset: DCTRL
+  - name: DCOUNT
+    description: 'Bits 24:0 = DATACOUNT: Data count value.'
+    byte_offset: 48
+    access: Read
+    fieldset: DCOUNT
+  - name: STA
+    description: SDIO status register (SDIO_STA).
+    byte_offset: 52
+    access: Read
+    fieldset: STA
+  - name: ICR
+    description: SDIO interrupt clear register (SDIO_ICR).
+    byte_offset: 56
+    fieldset: ICR
+  - name: MASK
+    description: SDIO mask register (SDIO_MASK).
+    byte_offset: 60
+    fieldset: MASK
+  - name: FIFOCNT
+    description: 'Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO.'
+    byte_offset: 72
+    access: Read
+    fieldset: FIFOCNT
+  - name: FIFO
+    description: 'bits 31:0 = FIFOData: Receive and transmit FIFO data.'
+    byte_offset: 128
+    fieldset: FIFO
+fieldset/ARG:
+  description: 'Bits 31:0 = : Command argument.'
+  fields:
+  - name: CMDARG
+    description: Command argument.
+    bit_offset: 0
+    bit_size: 32
+fieldset/CLKCR:
+  description: SDI clock control register (SDIO_CLKCR).
+  fields:
+  - name: CLKDIV
+    description: Clock divide factor.
+    bit_offset: 0
+    bit_size: 8
+  - name: CLKEN
+    description: Clock enable bit.
+    bit_offset: 8
+    bit_size: 1
+  - name: PWRSAV
+    description: Power saving configuration bit.
+    bit_offset: 9
+    bit_size: 1
+  - name: BYPASS
+    description: Clock divider bypass enable bit.
+    bit_offset: 10
+    bit_size: 1
+  - name: WIDBUS
+    description: Wide bus mode enable bit.
+    bit_offset: 11
+    bit_size: 2
+  - name: NEGEDGE
+    description: SDIO_CK dephasing selection bit.
+    bit_offset: 13
+    bit_size: 1
+  - name: HWFC_EN
+    description: HW Flow Control enable.
+    bit_offset: 14
+    bit_size: 1
+fieldset/CMD:
+  description: SDIO command register (SDIO_CMD).
+  fields:
+  - name: CMDINDEX
+    description: Command index.
+    bit_offset: 0
+    bit_size: 6
+  - name: WAITRESP
+    description: Wait for response bits.
+    bit_offset: 6
+    bit_size: 2
+  - name: WAITINT
+    description: CPSM waits for interrupt request.
+    bit_offset: 8
+    bit_size: 1
+  - name: WAITPEND
+    description: CPSM Waits for ends of data transfer (CmdPend internal signal).
+    bit_offset: 9
+    bit_size: 1
+  - name: CPSMEN
+    description: Command path state machine (CPSM) Enable bit.
+    bit_offset: 10
+    bit_size: 1
+  - name: SDIOSuspend
+    description: SD I/O suspend command.
+    bit_offset: 11
+    bit_size: 1
+  - name: ENCMDcompl
+    description: Enable CMD completion.
+    bit_offset: 12
+    bit_size: 1
+  - name: nIEN
+    description: not Interrupt Enable.
+    bit_offset: 13
+    bit_size: 1
+  - name: CE_ATACMD
+    description: CE-ATA command.
+    bit_offset: 14
+    bit_size: 1
+fieldset/DCOUNT:
+  description: 'Bits 24:0 = DATACOUNT: Data count value.'
+  fields:
+  - name: DATACOUNT
+    description: Data count value.
+    bit_offset: 0
+    bit_size: 25
+fieldset/DCTRL:
+  description: SDIO data control register (SDIO_DCTRL).
+  fields:
+  - name: DTEN
+    description: Data transfer enabled bit.
+    bit_offset: 0
+    bit_size: 1
+  - name: DTDIR
+    description: Data transfer direction selection.
+    bit_offset: 1
+    bit_size: 1
+  - name: DTMODE
+    description: 'Data transfer mode selection 1: Stream or SDIO multibyte data transfer.'
+    bit_offset: 2
+    bit_size: 1
+  - name: DMAEN
+    description: DMA enable bit.
+    bit_offset: 3
+    bit_size: 1
+  - name: DBLOCKSIZE
+    description: Data block size.
+    bit_offset: 4
+    bit_size: 4
+  - name: PWSTART
+    description: Read wait start.
+    bit_offset: 8
+    bit_size: 1
+  - name: PWSTOP
+    description: Read wait stop.
+    bit_offset: 9
+    bit_size: 1
+  - name: RWMOD
+    description: Read wait mode.
+    bit_offset: 10
+    bit_size: 1
+  - name: SDIOEN
+    description: SD I/O enable functions.
+    bit_offset: 11
+    bit_size: 1
+fieldset/DLEN:
+  description: 'Bits 24:0 = DATALENGTH: Data length value.'
+  fields:
+  - name: DATALENGTH
+    description: Data length value.
+    bit_offset: 0
+    bit_size: 25
+fieldset/DTIMER:
+  description: 'Bits 31:0 = DATATIME: Data timeout period.'
+  fields:
+  - name: DATATIME
+    description: Data timeout period.
+    bit_offset: 0
+    bit_size: 32
+fieldset/FIFO:
+  description: 'bits 31:0 = FIFOData: Receive and transmit FIFO data.'
+  fields:
+  - name: FIFOData
+    description: Receive and transmit FIFO data.
+    bit_offset: 0
+    bit_size: 32
+fieldset/FIFOCNT:
+  description: 'Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO.'
+  fields:
+  - name: FIF0COUNT
+    description: Remaining number of words to be written to or read from the FIFO.
+    bit_offset: 0
+    bit_size: 32
+fieldset/ICR:
+  description: SDIO interrupt clear register (SDIO_ICR).
+  fields:
+  - name: CCRCFAILC
+    description: CCRCFAIL flag clear bit.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCRCFAILC
+    description: DCRCFAIL flag clear bit.
+    bit_offset: 1
+    bit_size: 1
+  - name: CTIMEOUTC
+    description: CTIMEOUT flag clear bit.
+    bit_offset: 2
+    bit_size: 1
+  - name: DTIMEOUTC
+    description: DTIMEOUT flag clear bit.
+    bit_offset: 3
+    bit_size: 1
+  - name: TXUNDERRC
+    description: TXUNDERR flag clear bit.
+    bit_offset: 4
+    bit_size: 1
+  - name: RXOVERRC
+    description: RXOVERR flag clear bit.
+    bit_offset: 5
+    bit_size: 1
+  - name: CMDRENDC
+    description: CMDREND flag clear bit.
+    bit_offset: 6
+    bit_size: 1
+  - name: CMDSENTC
+    description: CMDSENT flag clear bit.
+    bit_offset: 7
+    bit_size: 1
+  - name: DATAENDC
+    description: DATAEND flag clear bit.
+    bit_offset: 8
+    bit_size: 1
+  - name: STBITERRC
+    description: STBITERR flag clear bit.
+    bit_offset: 9
+    bit_size: 1
+  - name: DBCKENDC
+    description: DBCKEND flag clear bit.
+    bit_offset: 10
+    bit_size: 1
+  - name: SDIOITC
+    description: SDIOIT flag clear bit.
+    bit_offset: 22
+    bit_size: 1
+  - name: CEATAENDC
+    description: CEATAEND flag clear bit.
+    bit_offset: 23
+    bit_size: 1
+fieldset/MASK:
+  description: SDIO mask register (SDIO_MASK).
+  fields:
+  - name: CCRCFAILIE
+    description: Command CRC fail interrupt enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCRCFAILIE
+    description: Data CRC fail interrupt enable.
+    bit_offset: 1
+    bit_size: 1
+  - name: CTIMEOUTIE
+    description: Command timeout interrupt enable.
+    bit_offset: 2
+    bit_size: 1
+  - name: DTIMEOUTIE
+    description: Data timeout interrupt enable.
+    bit_offset: 3
+    bit_size: 1
+  - name: TXUNDERRIE
+    description: Tx FIFO underrun error interrupt enable.
+    bit_offset: 4
+    bit_size: 1
+  - name: RXOVERRIE
+    description: Rx FIFO overrun error interrupt enable.
+    bit_offset: 5
+    bit_size: 1
+  - name: CMDRENDIE
+    description: Command response received interrupt enable.
+    bit_offset: 6
+    bit_size: 1
+  - name: CMDSENTIE
+    description: Command sent interrupt enable.
+    bit_offset: 7
+    bit_size: 1
+  - name: DATAENDIE
+    description: Data end interrupt enable.
+    bit_offset: 8
+    bit_size: 1
+  - name: STBITERRIE
+    description: Start bit error interrupt enable.
+    bit_offset: 9
+    bit_size: 1
+  - name: DBACKENDIE
+    description: Data block end interrupt enable.
+    bit_offset: 10
+    bit_size: 1
+  - name: CMDACTIE
+    description: Command acting interrupt enable.
+    bit_offset: 11
+    bit_size: 1
+  - name: TXACTIE
+    description: Data transmit acting interrupt enable.
+    bit_offset: 12
+    bit_size: 1
+  - name: RXACTIE
+    description: Data receive acting interrupt enable.
+    bit_offset: 13
+    bit_size: 1
+  - name: TXFIFOHEIE
+    description: Tx FIFO half empty interrupt enable.
+    bit_offset: 14
+    bit_size: 1
+  - name: RXFIFOHFIE
+    description: Rx FIFO half full interrupt enable.
+    bit_offset: 15
+    bit_size: 1
+  - name: TXFIFOFIE
+    description: Tx FIFO full interrupt enable.
+    bit_offset: 16
+    bit_size: 1
+  - name: RXFIFOFIE
+    description: Rx FIFO full interrupt enable.
+    bit_offset: 17
+    bit_size: 1
+  - name: TXFIFOEIE
+    description: Tx FIFO empty interrupt enable.
+    bit_offset: 18
+    bit_size: 1
+  - name: RXFIFOEIE
+    description: Rx FIFO empty interrupt enable.
+    bit_offset: 19
+    bit_size: 1
+  - name: TXDAVLIE
+    description: Data available in Tx FIFO interrupt enable.
+    bit_offset: 20
+    bit_size: 1
+  - name: RXDAVLIE
+    description: Data available in Rx FIFO interrupt enable.
+    bit_offset: 21
+    bit_size: 1
+  - name: SDIOITIE
+    description: SDIO mode interrupt received interrupt enable.
+    bit_offset: 22
+    bit_size: 1
+  - name: CEATENDIE
+    description: CE-ATA command completion signal received interrupt enable.
+    bit_offset: 23
+    bit_size: 1
+fieldset/POWER:
+  description: 'Bits 1:0 = PWRCTRL: Power supply control bits.'
+  fields:
+  - name: PWRCTRL
+    description: Power supply control bits.
+    bit_offset: 0
+    bit_size: 2
+fieldset/RESP:
+  description: Bits 31:0 = CARDSTATUS1.
+  fields:
+  - name: CARDSTATUS
+    description: Card status 1.
+    bit_offset: 0
+    bit_size: 32
+fieldset/RESPCMD:
+  description: SDIO command register.
+  fields:
+  - name: RESPCMD
+    description: Response command index.
+    bit_offset: 0
+    bit_size: 6
+fieldset/STA:
+  description: SDIO status register (SDIO_STA).
+  fields:
+  - name: CCRCFAIL
+    description: Command response received (CRC check failed).
+    bit_offset: 0
+    bit_size: 1
+  - name: DCRCFAIL
+    description: Data block sent/received (CRC check failed).
+    bit_offset: 1
+    bit_size: 1
+  - name: CTIMEOUT
+    description: Command response timeout.
+    bit_offset: 2
+    bit_size: 1
+  - name: DTIMEOUT
+    description: Data timeout.
+    bit_offset: 3
+    bit_size: 1
+  - name: TXUNDERR
+    description: Transmit FIFO underrun error.
+    bit_offset: 4
+    bit_size: 1
+  - name: RXOVERR
+    description: Received FIFO overrun error.
+    bit_offset: 5
+    bit_size: 1
+  - name: CMDREND
+    description: Command response received (CRC check passed).
+    bit_offset: 6
+    bit_size: 1
+  - name: CMDSENT
+    description: Command sent (no response required).
+    bit_offset: 7
+    bit_size: 1
+  - name: DATAEND
+    description: Data end (data counter, SDIDCOUNT, is zero).
+    bit_offset: 8
+    bit_size: 1
+  - name: STBITERR
+    description: Start bit not detected on all data signals in wide bus mode.
+    bit_offset: 9
+    bit_size: 1
+  - name: DBCKEND
+    description: Data block sent/received (CRC check passed).
+    bit_offset: 10
+    bit_size: 1
+  - name: CMDACT
+    description: Command transfer in progress.
+    bit_offset: 11
+    bit_size: 1
+  - name: TXACT
+    description: Data transmit in progress.
+    bit_offset: 12
+    bit_size: 1
+  - name: RXACT
+    description: Data receive in progress.
+    bit_offset: 13
+    bit_size: 1
+  - name: TXFIFOHE
+    description: 'Transmit FIFO half empty: at least 8 words can be written into the FIFO.'
+    bit_offset: 14
+    bit_size: 1
+  - name: RXFIFOHF
+    description: 'Receive FIFO half full: there are at least 8 words in the FIFO.'
+    bit_offset: 15
+    bit_size: 1
+  - name: TXFIFOF
+    description: Transmit FIFO full.
+    bit_offset: 16
+    bit_size: 1
+  - name: RXFIFOF
+    description: Receive FIFO full.
+    bit_offset: 17
+    bit_size: 1
+  - name: TXFIFOE
+    description: Transmit FIFO empty.
+    bit_offset: 18
+    bit_size: 1
+  - name: RXFIFOE
+    description: Receive FIFO empty.
+    bit_offset: 19
+    bit_size: 1
+  - name: TXDAVL
+    description: Data available in transmit FIFO.
+    bit_offset: 20
+    bit_size: 1
+  - name: RXDAVL
+    description: Data available in receive FIFO.
+    bit_offset: 21
+    bit_size: 1
+  - name: SDIOIT
+    description: SDIO interrupt received.
+    bit_offset: 22
+    bit_size: 1
+  - name: CEATAEND
+    description: CE-ATA command completion signal received for CMD61.
+    bit_offset: 23
+    bit_size: 1