From 7b153b6e397e4f56c23390b2525b5bf9119f1286 Mon Sep 17 00:00:00 2001
From: Leon Schoorl <leon@qbaylogic.com>
Date: Wed, 18 Dec 2024 17:27:28 +0100
Subject: [PATCH] Probe GTH resets

---
 .../src/Bittide/Instances/Hitl/Transceivers.hs   | 16 ++++++++++++++--
 bittide/src/Bittide/Transceiver.hs               |  8 ++++++++
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs b/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs
index 6dba64c6a..4bb5b2dba 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs
@@ -260,6 +260,9 @@ transceiversUpTest refClkDiff sysClkDiff syncIn rxns rxps miso =
   failAfterUp = isFalling sysClk testRst enableGen False allUp
   failAfterUpSticky = sticky sysClk testRst failAfterUp
 
+  rst_alls_bv = fmap pack $ bundle $ map unsafeToActiveHigh transceivers.rst_alls
+  rst_rxs_bv = fmap pack $ bundle $ map unsafeToActiveHigh transceivers.rst_rxs
+
   startTest = isJust <$> maybeFpgaIndex
   fpgaIndex = fromMaybe 0 <$> maybeFpgaIndex
 
@@ -293,6 +296,9 @@ transceiversUpTest refClkDiff sysClkDiff syncIn rxns rxps miso =
             :> "probe_startTest"
             :> "probe_syncInRst"
 
+            :> "probe_rst_alls"
+            :> "probe_rst_rxs"
+
             :> "dbgDataRx6" :> "dbgDataRx5" :> "dbgDataRx4" :> "dbgDataRx3" :> "dbgDataRx2" :> "dbgDataRx1" :> "dbgDataRx0"
             :> "dbgDataExp6" :> "dbgDataExp5" :> "dbgDataExp4" :> "dbgDataExp3" :> "dbgDataExp2" :> "dbgDataExp1" :> "dbgDataExp0"
 
@@ -316,6 +322,9 @@ transceiversUpTest refClkDiff sysClkDiff syncIn rxns rxps miso =
         startTest
         (unsafeToActiveHigh syncInRst)
 
+        rst_alls_bv
+        rst_rxs_bv
+
         dbgDataRx6 dbgDataRx5 dbgDataRx4 dbgDataRx3 dbgDataRx2 dbgDataRx1 dbgDataRx0
         dbgDataExp6 dbgDataExp5 dbgDataExp4 dbgDataExp3 dbgDataExp2 dbgDataExp1 dbgDataExp0
 
@@ -332,9 +341,12 @@ transceiversUpTest refClkDiff sysClkDiff syncIn rxns rxps miso =
         , unsafeToActiveHigh sysRst
         , startTest
         , unsafeToActiveHigh syncInRst
+        , milliseconds1
+        , rst_alls_bv
+        , rst_rxs_bv
 
-        ,bundle (dbgDataRx6, dbgDataRx5, dbgDataRx4, dbgDataRx3, dbgDataRx2, dbgDataRx1, dbgDataRx0)
-        ,bundle (dbgDataExp6, dbgDataExp5, dbgDataExp4, dbgDataExp3, dbgDataExp2, dbgDataExp1, dbgDataExp0)
+        -- ,bundle (dbgDataRx6, dbgDataRx5, dbgDataRx4, dbgDataRx3, dbgDataRx2, dbgDataRx1, dbgDataRx0)
+        -- ,bundle (dbgDataExp6, dbgDataExp5, dbgDataExp4, dbgDataExp3, dbgDataExp2, dbgDataExp1, dbgDataExp0)
 
         )
   timeSucc = countSucc @(Unsigned 16, Index (PeriodToCycles Basic125 (Milliseconds 1)))
diff --git a/bittide/src/Bittide/Transceiver.hs b/bittide/src/Bittide/Transceiver.hs
index 59c11586e..ee5b6c0f9 100644
--- a/bittide/src/Bittide/Transceiver.hs
+++ b/bittide/src/Bittide/Transceiver.hs
@@ -196,6 +196,8 @@ data Outputs n tx rx txS free = Outputs
   -- ^ See 'Output.linkReady'
   , stats :: Vec n (Signal free ResetManager.Statistics)
   -- ^ See 'Output.stats'
+  , rst_alls :: Vec n (Reset free)
+  , rst_rxs  :: Vec n (Reset free)
   }
 
 data Output tx rx txS free serializedData = Output
@@ -227,6 +229,8 @@ data Output tx rx txS free serializedData = Output
   -- doing so. I.e., 'linkUp' implies 'linkReady'. Note that this
   , stats :: Signal free ResetManager.Statistics
   -- ^ Statistics exported by 'ResetManager.resetManager'. Useful for debugging.
+  , rst_all :: Reset free
+  , rst_rx :: Reset free
   }
 
 data Input tx rx ref free rxS serializedData = Input
@@ -317,6 +321,8 @@ transceiverPrbsN opts inputs@Inputs{clock, reset, refClock} =
       linkUps = map (.linkUp) outputs
     , linkReadys = map (.linkReady) outputs
     , stats = map (.stats) outputs
+    , rst_alls = map (.rst_all) outputs
+    , rst_rxs = map (.rst_rx) outputs    
     }
  where
   -- XXX: Replacing 'zipWithN' with '<$>' and '<*>' triggers a combination of:
@@ -482,6 +488,8 @@ transceiverPrbsWith gthCore opts args@Input{clock, reset} =
       , linkUp
       , linkReady
       , stats
+      , rst_all
+      , rst_rx
       }
 
   linkUp =