Generalize the interface to the NC Verilog Simulator

[atsmith3]

Currently the NC Verilog Simulator is set up to model the entire device as a single restive load based on McPAT calculations. In order to model the power delivery network for modern large many core devices, The Verilog model and the interface shared memory interface should be dynamic based on the number of cores in the device.

This is easy to do from the verilog side as the VPI routines are recompiled at the time of running, however because the interface is shared memory and cannot use any C++ containers, it can just be statically allocated at Gem5 compile to use 256 entries for a maximum of 256 cores.

The files for this interface can be found in the src/python/pybind11/ and src/python/m5/