From 34de609f1ccd65b40d6ed8b18253751dda4e9f3f Mon Sep 17 00:00:00 2001 From: Godones <1925466036@qq.com> Date: Mon, 18 Sep 2023 19:53:53 +0800 Subject: [PATCH 01/19] feat: add basic loongarch64 support - Refactor the [repo](https://github.com/aoooos/arceos) code to merge - Use standard toolchain - Fix the compile command --- .gitignore | 1 + Cargo.lock | 10 + Cargo.toml | 1 + Makefile | 6 +- crates/kernel_guard/src/arch/loongarch64.rs | 19 ++ crates/kernel_guard/src/arch/mod.rs | 3 + crates/loongarch64/Cargo.toml | 10 + crates/loongarch64/src/asm.rs | 33 ++++ crates/loongarch64/src/consts.rs | 21 +++ crates/loongarch64/src/cpu.rs | 96 ++++++++++ crates/loongarch64/src/extioi.rs | 53 ++++++ crates/loongarch64/src/ipi.rs | 76 ++++++++ crates/loongarch64/src/lib.rs | 15 ++ crates/loongarch64/src/loongson.rs | 61 ++++++ crates/loongarch64/src/ls7a.rs | 84 +++++++++ crates/loongarch64/src/mem.rs | 6 + crates/loongarch64/src/mod.rs | 17 ++ crates/loongarch64/src/register/badi.rs | 26 +++ crates/loongarch64/src/register/badv.rs | 27 +++ crates/loongarch64/src/register/cpuid.rs | 27 +++ crates/loongarch64/src/register/crmd.rs | 98 ++++++++++ crates/loongarch64/src/register/csr.rs | 58 ++++++ crates/loongarch64/src/register/dmwn.rs | 109 +++++++++++ crates/loongarch64/src/register/ecfg.rs | 51 +++++ crates/loongarch64/src/register/eentry.rs | 29 +++ crates/loongarch64/src/register/era.rs | 37 ++++ crates/loongarch64/src/register/estat.rs | 178 ++++++++++++++++++ crates/loongarch64/src/register/misc.rs | 40 ++++ crates/loongarch64/src/register/mod.rs | 26 +++ crates/loongarch64/src/register/prcfg1.rs | 34 ++++ crates/loongarch64/src/register/prcfg2.rs | 25 +++ crates/loongarch64/src/register/prcfg3.rs | 46 +++++ crates/loongarch64/src/register/prmd.rs | 65 +++++++ crates/loongarch64/src/register/rvacfg.rs | 37 ++++ crates/loongarch64/src/register/saven.rs | 35 ++++ crates/loongarch64/src/register/tcfg.rs | 61 ++++++ crates/loongarch64/src/register/ticlr.rs | 33 ++++ crates/loongarch64/src/register/time.rs | 30 +++ crates/loongarch64/src/register/tval.rs | 21 +++ crates/loongarch64/src/rtc.rs | 80 ++++++++ crates/loongarch64/src/tlb/asid.rs | 40 ++++ crates/loongarch64/src/tlb/mod.rs | 35 ++++ crates/loongarch64/src/tlb/pgd.rs | 28 +++ crates/loongarch64/src/tlb/pgdh.rs | 33 ++++ crates/loongarch64/src/tlb/pgdl.rs | 33 ++++ crates/loongarch64/src/tlb/pwch.rs | 51 +++++ crates/loongarch64/src/tlb/pwcl.rs | 99 ++++++++++ crates/loongarch64/src/tlb/stlbps.rs | 32 ++++ crates/loongarch64/src/tlb/tlbehi.rs | 37 ++++ crates/loongarch64/src/tlb/tlbelo.rs | 168 +++++++++++++++++ crates/loongarch64/src/tlb/tlbentry.rs | 37 ++++ crates/loongarch64/src/tlb/tlbidx.rs | 58 ++++++ crates/loongarch64/src/tlb/tlbrbadv.rs | 30 +++ crates/loongarch64/src/tlb/tlbrehi.rs | 46 +++++ crates/loongarch64/src/tlb/tlbrelo.rs | 154 +++++++++++++++ crates/loongarch64/src/tlb/tlbrera.rs | 46 +++++ crates/loongarch64/src/tlb/tlbrprmd.rs | 59 ++++++ crates/loongarch64/src/tlb/tlbrsave.rs | 1 + crates/percpu/src/imp.rs | 4 + crates/percpu_macros/src/arch.rs | 8 + modules/axhal/Cargo.toml | 4 + modules/axhal/linker.lds.S | 2 +- modules/axhal/src/arch/loongarch64/context.rs | 106 +++++++++++ modules/axhal/src/arch/loongarch64/mod.rs | 117 ++++++++++++ modules/axhal/src/arch/loongarch64/tlb.S | 105 +++++++++++ modules/axhal/src/arch/loongarch64/trap.S | 153 +++++++++++++++ modules/axhal/src/arch/loongarch64/trap.rs | 34 ++++ modules/axhal/src/arch/mod.rs | 3 + modules/axhal/src/cpu.rs | 8 + modules/axhal/src/platform/mod.rs | 5 +- .../platform/qemu_virt_loongarch64/boot.rs | 96 ++++++++++ .../platform/qemu_virt_loongarch64/console.rs | 77 ++++++++ .../src/platform/qemu_virt_loongarch64/irq.rs | 64 +++++++ .../src/platform/qemu_virt_loongarch64/mem.rs | 6 + .../platform/qemu_virt_loongarch64/misc.rs | 6 + .../src/platform/qemu_virt_loongarch64/mod.rs | 51 +++++ .../src/platform/qemu_virt_loongarch64/mp.rs | 15 ++ .../platform/qemu_virt_loongarch64/time.rs | 45 +++++ platforms/loongarch64-qemu-virt.toml | 35 ++++ scripts/make/cargo.mk | 4 + scripts/make/qemu.mk | 25 +++ tools/la64/efi-virtio.rom | Bin 0 -> 160768 bytes tools/la64/la-gdb.sh | 9 + tools/la64/la-qemu.sh | 11 ++ tools/la64/loongarch_bios_0310.bin | Bin 0 -> 4190208 bytes tools/la64/loongarch_bios_0310_debug.bin | Bin 0 -> 4190208 bytes 86 files changed, 3662 insertions(+), 3 deletions(-) create mode 100644 crates/kernel_guard/src/arch/loongarch64.rs create mode 100644 crates/loongarch64/Cargo.toml create mode 100644 crates/loongarch64/src/asm.rs create mode 100644 crates/loongarch64/src/consts.rs create mode 100644 crates/loongarch64/src/cpu.rs create mode 100644 crates/loongarch64/src/extioi.rs create mode 100644 crates/loongarch64/src/ipi.rs create mode 100644 crates/loongarch64/src/lib.rs create mode 100644 crates/loongarch64/src/loongson.rs create mode 100644 crates/loongarch64/src/ls7a.rs create mode 100644 crates/loongarch64/src/mem.rs create mode 100644 crates/loongarch64/src/mod.rs create mode 100644 crates/loongarch64/src/register/badi.rs create mode 100644 crates/loongarch64/src/register/badv.rs create mode 100644 crates/loongarch64/src/register/cpuid.rs create mode 100644 crates/loongarch64/src/register/crmd.rs create mode 100644 crates/loongarch64/src/register/csr.rs create mode 100644 crates/loongarch64/src/register/dmwn.rs create mode 100644 crates/loongarch64/src/register/ecfg.rs create mode 100644 crates/loongarch64/src/register/eentry.rs create mode 100644 crates/loongarch64/src/register/era.rs create mode 100644 crates/loongarch64/src/register/estat.rs create mode 100644 crates/loongarch64/src/register/misc.rs create mode 100644 crates/loongarch64/src/register/mod.rs create mode 100644 crates/loongarch64/src/register/prcfg1.rs create mode 100644 crates/loongarch64/src/register/prcfg2.rs create mode 100644 crates/loongarch64/src/register/prcfg3.rs create mode 100644 crates/loongarch64/src/register/prmd.rs create mode 100644 crates/loongarch64/src/register/rvacfg.rs create mode 100644 crates/loongarch64/src/register/saven.rs create mode 100644 crates/loongarch64/src/register/tcfg.rs create mode 100644 crates/loongarch64/src/register/ticlr.rs create mode 100644 crates/loongarch64/src/register/time.rs create mode 100644 crates/loongarch64/src/register/tval.rs create mode 100644 crates/loongarch64/src/rtc.rs create mode 100644 crates/loongarch64/src/tlb/asid.rs create mode 100644 crates/loongarch64/src/tlb/mod.rs create mode 100644 crates/loongarch64/src/tlb/pgd.rs create mode 100644 crates/loongarch64/src/tlb/pgdh.rs create mode 100644 crates/loongarch64/src/tlb/pgdl.rs create mode 100644 crates/loongarch64/src/tlb/pwch.rs create mode 100644 crates/loongarch64/src/tlb/pwcl.rs create mode 100644 crates/loongarch64/src/tlb/stlbps.rs create mode 100644 crates/loongarch64/src/tlb/tlbehi.rs create mode 100644 crates/loongarch64/src/tlb/tlbelo.rs create mode 100644 crates/loongarch64/src/tlb/tlbentry.rs create mode 100644 crates/loongarch64/src/tlb/tlbidx.rs create mode 100644 crates/loongarch64/src/tlb/tlbrbadv.rs create mode 100644 crates/loongarch64/src/tlb/tlbrehi.rs create mode 100644 crates/loongarch64/src/tlb/tlbrelo.rs create mode 100644 crates/loongarch64/src/tlb/tlbrera.rs create mode 100644 crates/loongarch64/src/tlb/tlbrprmd.rs create mode 100644 crates/loongarch64/src/tlb/tlbrsave.rs create mode 100644 modules/axhal/src/arch/loongarch64/context.rs create mode 100644 modules/axhal/src/arch/loongarch64/mod.rs create mode 100644 modules/axhal/src/arch/loongarch64/tlb.S create mode 100644 modules/axhal/src/arch/loongarch64/trap.S create mode 100644 modules/axhal/src/arch/loongarch64/trap.rs create mode 100644 modules/axhal/src/platform/qemu_virt_loongarch64/boot.rs create mode 100644 modules/axhal/src/platform/qemu_virt_loongarch64/console.rs create mode 100644 modules/axhal/src/platform/qemu_virt_loongarch64/irq.rs create mode 100644 modules/axhal/src/platform/qemu_virt_loongarch64/mem.rs create mode 100644 modules/axhal/src/platform/qemu_virt_loongarch64/misc.rs create mode 100644 modules/axhal/src/platform/qemu_virt_loongarch64/mod.rs create mode 100644 modules/axhal/src/platform/qemu_virt_loongarch64/mp.rs create mode 100644 modules/axhal/src/platform/qemu_virt_loongarch64/time.rs create mode 100644 platforms/loongarch64-qemu-virt.toml create mode 100644 tools/la64/efi-virtio.rom create mode 100755 tools/la64/la-gdb.sh create mode 100755 tools/la64/la-qemu.sh create mode 100644 tools/la64/loongarch_bios_0310.bin create mode 100644 tools/la64/loongarch_bios_0310_debug.bin diff --git a/.gitignore b/.gitignore index 9d91ac5720..305250feec 100644 --- a/.gitignore +++ b/.gitignore @@ -6,3 +6,4 @@ actual.out qemu.log rusty-tags.vi +.idea diff --git a/Cargo.lock b/Cargo.lock index b305bb4329..9460a40110 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -372,6 +372,7 @@ dependencies = [ "axalloc", "axconfig", "axlog", + "bit_field", "bitflags 2.4.0", "cfg-if", "crate_interface", @@ -380,6 +381,7 @@ dependencies = [ "kernel_guard", "lazy_init", "log", + "loongarch64", "memory_addr", "page_table", "page_table_entry", @@ -1222,6 +1224,14 @@ version = "0.4.19" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "b06a4cde4c0f271a446782e3eff8de789548ce57dbc8eca9292c27f4a42004b4" +[[package]] +name = "loongarch64" +version = "0.1.0" +dependencies = [ + "bit_field", + "log", +] + [[package]] name = "managed" version = "0.8.0" diff --git a/Cargo.toml b/Cargo.toml index 1db098f126..fc6dc78bb3 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -35,6 +35,7 @@ members = [ "crates/spinlock", "crates/timer_list", "crates/tuple_for_each", + "crates/loongarch64", "modules/axalloc", "modules/axconfig", diff --git a/Makefile b/Makefile index b351596584..abe3ba1c1f 100644 --- a/Makefile +++ b/Makefile @@ -103,8 +103,12 @@ else ifeq ($(ARCH), aarch64) ACCEL ?= n PLATFORM_NAME ?= aarch64-qemu-virt TARGET := aarch64-unknown-none-softfloat +else ifeq ($(ARCH), loongarch64) + ACCEL ?= n + PLATFORM_NAME ?= loongarch64-qemu-virt + TARGET := loongarch64-unknown-none else - $(error "ARCH" must be one of "x86_64", "riscv64", or "aarch64") + $(error "ARCH" must be one of "x86_64", "riscv64", "aarch64" or "loongarch64") endif export AX_ARCH=$(ARCH) diff --git a/crates/kernel_guard/src/arch/loongarch64.rs b/crates/kernel_guard/src/arch/loongarch64.rs new file mode 100644 index 0000000000..d4a323854f --- /dev/null +++ b/crates/kernel_guard/src/arch/loongarch64.rs @@ -0,0 +1,19 @@ +use core::arch::asm; + +#[inline] +pub fn local_irq_save_and_disable() -> usize { + let mut flags: usize = 0; + let ie_mask: usize = 1 << 2; + // clear the `IE` bit, and return the old CSR + // unsafe { asm!("csrrd {}, 0x0", out(reg) flags) }; + unsafe { asm!("csrxchg {}, {}, 0x0", inout(reg)flags, in(reg) ie_mask) }; + flags & ie_mask +} + +#[inline] +#[allow(unused_assignments)] +pub fn local_irq_restore(mut flags: usize) { + // restore the `IE` bit + let mask: usize = 1 << 2; + unsafe { asm!("csrxchg {}, {}, 0x0", inout(reg)flags, in(reg) mask) }; +} diff --git a/crates/kernel_guard/src/arch/mod.rs b/crates/kernel_guard/src/arch/mod.rs index 3a05149726..c5207deda8 100644 --- a/crates/kernel_guard/src/arch/mod.rs +++ b/crates/kernel_guard/src/arch/mod.rs @@ -10,5 +10,8 @@ cfg_if::cfg_if! { } else if #[cfg(target_arch = "aarch64")] { mod aarch64; pub use self::aarch64::*; + }else if #[cfg(target_arch = "loongarch64")] { + mod loongarch64; + pub use self::loongarch64::*; } } diff --git a/crates/loongarch64/Cargo.toml b/crates/loongarch64/Cargo.toml new file mode 100644 index 0000000000..f4062b186e --- /dev/null +++ b/crates/loongarch64/Cargo.toml @@ -0,0 +1,10 @@ +[package] +name = "loongarch64" +version = "0.1.0" +edition = "2021" + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +bit_field = "0.10.1" +log = "0.4" \ No newline at end of file diff --git a/crates/loongarch64/src/asm.rs b/crates/loongarch64/src/asm.rs new file mode 100644 index 0000000000..3b79353015 --- /dev/null +++ b/crates/loongarch64/src/asm.rs @@ -0,0 +1,33 @@ +//! Assembly instructions + +macro_rules! instruction { + ($(#[$attr:meta])*, $fnname:ident, $asm:expr) => ( + $(#[$attr])* + #[inline] + pub unsafe fn $fnname() { + match () { + #[cfg(target_arch = "loongarch64")] + () => core::arch::asm!($asm), + + #[cfg(not(target_arch = "loongarch64"))] + () => unimplemented!(), + } + } + ) +} + +instruction!( + /// `nop` instruction wrapper + /// + /// Generates a no-operation. Useful to prevent delay loops from being optimized away. + , nop, "nop"); +instruction!( + /// `EBREAK` instruction wrapper + /// + /// Generates a breakpoint exception. + , r#break, "break"); +instruction!( + /// `EBREAK` instruction wrapper + /// + /// The format is `idle level`. What is level is still unknown. Temporarily use `1` as `level`. + , idle, "idle 1"); diff --git a/crates/loongarch64/src/consts.rs b/crates/loongarch64/src/consts.rs new file mode 100644 index 0000000000..ba452d5d9a --- /dev/null +++ b/crates/loongarch64/src/consts.rs @@ -0,0 +1,21 @@ +pub const LOONGARCH_IOCSR_IPI_STATUS: usize = 0x1000; +pub const LOONGARCH_IOCSR_IPI_EN: usize = 0x1004; +pub const LOONGARCH_IOCSR_IPI_SET: usize = 0x1008; +pub const LOONGARCH_IOCSR_IPI_CLEAR: usize = 0x100c; +pub const LOONGARCH_CSR_MAIL_BUF0: usize = 0x1020; +pub const LOONGARCH_CSR_MAIL_BUF1: usize = 0x1028; +pub const LOONGARCH_CSR_MAIL_BUF2: usize = 0x1030; +pub const LOONGARCH_CSR_MAIL_BUF3: usize = 0x1038; + +pub const IOCSR_MBUF_SEND_CPU_SHIFT: usize = 16; +pub const IOCSR_MBUF_SEND_BUF_SHIFT: usize = 32; +pub const IOCSR_MBUF_SEND_H32_MASK: usize = 0xFFFF_FFFF_0000_0000; + +pub const LOONGARCH_IOCSR_IPI_SEND: usize = 0x1040; +pub const IOCSR_IPI_SEND_IP_SHIFT: usize = 0; +pub const IOCSR_IPI_SEND_CPU_SHIFT: usize = 16; +pub const IOCSR_IPI_SEND_BLOCKING: u32 = 1 << 31; + +pub const LOONGARCH_IOCSR_MBUF_SEND: usize = 0x1048; +pub const IOCSR_MBUF_SEND_BLOCKING: u64 = 1 << 31; +pub const IOCSR_MBUF_SEND_BOX_SHIFT: usize = 2; diff --git a/crates/loongarch64/src/cpu.rs b/crates/loongarch64/src/cpu.rs new file mode 100644 index 0000000000..e07284c136 --- /dev/null +++ b/crates/loongarch64/src/cpu.rs @@ -0,0 +1,96 @@ +use bit_field::BitField; +use core::arch::asm; +#[derive(Debug, Clone, Copy)] +pub enum CpuMode { + User = 3, + Supervisor = 0, +} + +pub struct CPUCFG { + bits: usize, +} + +impl CPUCFG { + // 读取index对应字的内容 + pub fn read(index: usize) -> Self { + let mut bits; + unsafe { + asm!("cpucfg {},{}",out(reg) bits,in(reg) index); + } + Self { bits } + } + pub fn get_bit(&self, index: usize) -> bool { + self.bits.get_bit(index) + } + pub fn get_bits(&self, start: usize, end: usize) -> usize { + self.bits.get_bits(start..=end) + } +} + +// 获取处理器标识 +pub fn get_prid() -> usize { + let cfg = CPUCFG::read(0); + cfg.get_bits(0, 31) +} + +// 获取架构信息 +pub fn get_arch() -> usize { + let cfg = CPUCFG::read(1); + cfg.get_bits(0, 1) +} + +pub fn get_mmu_support_page() -> bool { + let cfg = CPUCFG::read(1); + cfg.get_bit(2) +} + +pub fn get_support_iocsr() -> bool { + let cfg = CPUCFG::read(1); + cfg.get_bit(3) +} + +// 获取支持的物理地址位数 +pub fn get_palen() -> usize { + let cfg = CPUCFG::read(1); + cfg.get_bits(4, 11) + 1 +} + +// 获取支持的虚拟地址位数 +pub fn get_valen() -> usize { + let cfg = CPUCFG::read(1); + cfg.get_bits(12, 19) + 1 +} +// 是否支持非对齐访存 +pub fn get_ual() -> bool { + let cfg = CPUCFG::read(1); + cfg.get_bit(20) +} + +pub fn get_support_read_forbid() -> bool { + let cfg = CPUCFG::read(1); + cfg.get_bit(21) +} +pub fn get_support_execution_protection() -> bool { + let cfg = CPUCFG::read(1); + cfg.get_bit(22) +} +pub fn get_support_rplv() -> bool { + let cfg = CPUCFG::read(1); + cfg.get_bit(23) +} +pub fn get_support_huge_page() -> bool { + let cfg = CPUCFG::read(1); + cfg.get_bit(24) +} +pub fn get_support_rva() -> bool { + let cfg = CPUCFG::read(3); + cfg.get_bit(12) +} +pub fn get_support_rva_len() -> usize { + let cfg = CPUCFG::read(3); + cfg.get_bits(13, 16) + 1 +} +pub fn get_support_lspw() -> bool { + let cfg = CPUCFG::read(2); + cfg.get_bit(21) +} diff --git a/crates/loongarch64/src/extioi.rs b/crates/loongarch64/src/extioi.rs new file mode 100644 index 0000000000..31f33add26 --- /dev/null +++ b/crates/loongarch64/src/extioi.rs @@ -0,0 +1,53 @@ +use super::loongson::{ + iocsr_read_b, iocsr_read_d, iocsr_read_w, iocsr_write_b, iocsr_write_d, iocsr_write_h, + iocsr_write_w, LOONGARCH_IOCSR_EXRIOI_NODETYPE_BASE, LOONGARCH_IOCSR_EXTIOI_EN_BASE, + LOONGARCH_IOCSR_EXTIOI_ISR_BASE, LOONGARCH_IOCSR_EXTIOI_MAP_BASE, + LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE, +}; +use super::ls7a::{KEYBOARD_IRQ, MOUSE_IRQ, UART0_IRQ}; +use super::register::csr::Register; +use super::register::estat::Estat; +use bit_field::BitField; +use log::{debug, info}; +/// 初始化外部中断 +pub fn extioi_init() { + let estat = Estat::read(); + debug!("before_extioi_init_estat={:#x?}", estat.get_val()); + /* let mut enable = 0; + enable + .set_bit(KEYBOARD_IRQ, true) + .set_bit(MOUSE_IRQ, true) + .set_bit(UART0_IRQ, true); + info!("extioi_init: enable = {:#b}", enable);*/ + // 使能外部设备中断 + // iocsr_write_d(LOONGARCH_IOCSR_EXTIOI_EN_BASE, enable); + + // extioi[31:0] map to cpu irq pin INT1, other to INT0 + //路由到INT1上 + iocsr_write_b(LOONGARCH_IOCSR_EXTIOI_MAP_BASE, 0x1); + // extioi IRQ 0-7 route to core 0, use node type 0 + //路由到EXT_IOI_node_type0指向的0号处理器上 + iocsr_write_w(LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE, 0x0); + // nodetype0 set to 1, always trigger at node 0 */ + //固定分发模式时,只在0号处理器上触发 + iocsr_write_h(LOONGARCH_IOCSR_EXRIOI_NODETYPE_BASE, 0x1); + + //检查扩展i/o触发器是不是全0，即没有被触发的中断 + let extioi_isr = iocsr_read_b(LOONGARCH_IOCSR_EXTIOI_ISR_BASE); + debug!("extioi_init: extioi_isr = {:#b}", extioi_isr); + let current_trigger = extioi_claim(); + debug!("extioi_init: current_trigger = {:#b}", current_trigger); + assert_eq!(extioi_isr, 0); + let estat = Estat::read(); + debug!("after_extioi_init_estat={:#x?}", estat.get_val()); + debug!("extioi_init: current_trigger = {:#b}", current_trigger); +} + +// ask the extioi what interrupt we should serve. +pub fn extioi_claim() -> u64 { + iocsr_read_d(LOONGARCH_IOCSR_EXTIOI_ISR_BASE) +} + +pub fn extioi_complete(irq: u64) { + iocsr_write_d(LOONGARCH_IOCSR_EXTIOI_ISR_BASE, irq); +} diff --git a/crates/loongarch64/src/ipi.rs b/crates/loongarch64/src/ipi.rs new file mode 100644 index 0000000000..6e661e5cc3 --- /dev/null +++ b/crates/loongarch64/src/ipi.rs @@ -0,0 +1,76 @@ +use crate::consts::*; +use bit_field::BitField; +use core::arch::asm; +pub fn iocsr_write_u32(addr: usize, value: u32) { + unsafe { + asm!("iocsrwr.w {},{}", in(reg) value,in(reg) addr); + } +} + +pub fn iocsr_read_u32(addr: usize) -> u32 { + let mut value: u32; + unsafe { + asm!("iocsrrd.w {},{}", out(reg) value, in(reg) addr); + } + value +} + +pub fn iocsr_write_u64(addr: usize, value: u64) { + unsafe { + asm!("iocsrwr.d {},{}", in(reg) value, in(reg) addr); + } +} + +pub fn iocsr_read_u64(addr: usize) -> u64 { + let mut value: u64; + unsafe { + asm!("iocsrrd.d {},{}", out(reg) value, in(reg) addr); + } + value +} + +fn iocsr_mbuf_send_box_lo(box_: usize) -> usize { + box_ << 1 +} +fn iocsr_mbuf_send_box_hi(box_: usize) -> usize { + (box_ << 1) + 1 +} + +pub fn csr_mail_send(entry: u64, cpu: usize, mailbox: usize) { + let mut val: u64; + val = IOCSR_MBUF_SEND_BLOCKING; + val |= (iocsr_mbuf_send_box_hi(mailbox) << IOCSR_MBUF_SEND_BOX_SHIFT) as u64; + val |= (cpu << IOCSR_MBUF_SEND_CPU_SHIFT) as u64; + val |= entry & IOCSR_MBUF_SEND_H32_MASK as u64; + iocsr_write_u64(LOONGARCH_IOCSR_MBUF_SEND, val); + val = IOCSR_MBUF_SEND_BLOCKING; + val |= (iocsr_mbuf_send_box_lo(mailbox) << IOCSR_MBUF_SEND_BOX_SHIFT) as u64; + val |= (cpu << IOCSR_MBUF_SEND_CPU_SHIFT) as u64; + val |= entry << IOCSR_MBUF_SEND_BUF_SHIFT; + iocsr_write_u64(LOONGARCH_IOCSR_MBUF_SEND, val); +} + +/// IPI_Send 0x1040 WO 32 位中断分发寄存器 +/// `[31]` 等待完成标志，置 1 时会等待中断生效 +/// +/// `[30:26]` 保留 +/// +/// `[25:16]` 处理器核号 +/// +/// `[15:5]` 保留 +/// +/// `[4:0]` 中断向量号，对应 IPI_Status 中的向量 +pub fn ipi_write_action(cpu: usize, action: u32) { + let mut val: u32 = IOCSR_IPI_SEND_BLOCKING; + for i in 0..32 { + if action.get_bit(i) { + val |= (cpu << IOCSR_IPI_SEND_CPU_SHIFT) as u32; + val |= i as u32; + iocsr_write_u32(LOONGARCH_IOCSR_IPI_SEND, val); + } + } +} + +pub fn send_ipi_single(cpu: usize, action: u32) { + ipi_write_action(cpu, action); +} diff --git a/crates/loongarch64/src/lib.rs b/crates/loongarch64/src/lib.rs new file mode 100644 index 0000000000..97a398234e --- /dev/null +++ b/crates/loongarch64/src/lib.rs @@ -0,0 +1,15 @@ +#![no_std] +#![allow(unused)] +pub mod asm; +pub mod consts; +pub mod cpu; +pub mod extioi; +pub mod ipi; +pub mod loongson; +pub mod ls7a; +pub mod mem; +pub mod register; +pub mod tlb; + +pub const VALEN: usize = 48; +pub const PALEN: usize = 48; diff --git a/crates/loongarch64/src/loongson.rs b/crates/loongarch64/src/loongson.rs new file mode 100644 index 0000000000..e3acf5b64a --- /dev/null +++ b/crates/loongarch64/src/loongson.rs @@ -0,0 +1,61 @@ +/* extioi registers */ +use core::arch::asm; + +pub const LOONGARCH_IOCSR_EXTIOI_EN_BASE: usize = 0x1600; //扩展 IO 中断[63:0]的中断使能配置 +pub const LOONGARCH_IOCSR_EXTIOI_ISR_BASE: usize = 0x1800; //路由至处理器核 0 的扩展 IO 中断[63:0]的中断状态 +pub const LOONGARCH_IOCSR_EXTIOI_MAP_BASE: usize = 0x14c0; //EXT_IOI[31:0]的引脚路由方式 +pub const LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE: usize = 0x1c00; //EXT_IOI[0]的处理器核路由方式 +pub const LOONGARCH_IOCSR_EXRIOI_NODETYPE_BASE: usize = 0x14a0; //16 个结点的映射向量类型 0（软件配置 +pub const LOONGARCH_IOCSR_EXRIOI_SEND: usize = 0x1140; // 配置寄存器中增加了一个扩展 IO 中断触发寄存 + // 器，用于将对应的 IO 中断置位 + +/// 4 +pub fn iocsr_write_w(reg: usize, value: u32) { + unsafe { + asm!("iocsrwr.w {},{}", in(reg) value, in(reg) reg); + } +} +// 8 +pub fn iocsr_write_d(reg: usize, value: u64) { + unsafe { + asm!("iocsrwr.d {},{}", in(reg) value, in(reg) reg); + } +} +// 2 +pub fn iocsr_write_h(reg: usize, value: u16) { + unsafe { + asm!("iocsrwr.h {},{}", in(reg) value, in(reg) reg); + } +} +// 1 +pub fn iocsr_write_b(reg: usize, value: u8) { + unsafe { + asm!("iocsrwr.b {},{}", in(reg) value, in(reg) reg); + } +} + +pub fn iocsr_read_b(reg: usize) -> u8 { + let val: u8; + unsafe { + asm!("iocsrrd.b {},{}",out(reg) val, in(reg) reg); + } + val +} + +// 4 +pub fn iocsr_read_w(reg: usize) -> u32 { + let val: u32; + unsafe { + asm!("iocsrrd.w {},{}",out(reg) val, in(reg) reg); + } + val +} + +// 8 +pub fn iocsr_read_d(reg: usize) -> u64 { + let val: u64; + unsafe { + asm!("iocsrrd.d {},{}",out(reg) val, in(reg) reg); + } + val +} diff --git a/crates/loongarch64/src/ls7a.rs b/crates/loongarch64/src/ls7a.rs new file mode 100644 index 0000000000..a537d908d8 --- /dev/null +++ b/crates/loongarch64/src/ls7a.rs @@ -0,0 +1,84 @@ +/// LS7A桥片配置空间 +/// LS7A桥片配置空间--中断控制器起始地址 +/// 0x1000_0000~0x1000_0fff 4k +pub const LS7A_PCH_REG_BASE: usize = 0x1000_0000; +pub const LS7A_MISC_REG_BASE: usize = LS7A_PCH_REG_BASE + 0x00080000; +pub const LS7A_ACPI_REG_BASE: usize = LS7A_MISC_REG_BASE + 0x00050000; +pub const LS7A_RTC_REG_BASE: usize = LS7A_MISC_REG_BASE + 0x00050100; + +pub const UART0_IRQ: usize = 2; +pub const KEYBOARD_IRQ: usize = 3; +pub const MOUSE_IRQ: usize = 4; + +// 8042 Keyboard Controller +pub const LS7A_I8042_DATA: usize = 0x1fe00060; +pub const LS7A_I8042_COMMAND: usize = 0x1fe00064; +pub const LS7A_I8042_STATUS: usize = 0x1fe00064; + +pub const LS7A_INT_MASK_REG: usize = LS7A_PCH_REG_BASE + 0x020; //中断掩码寄存器低32位 +pub const LS7A_INT_EDGE_REG: usize = LS7A_PCH_REG_BASE + 0x060; //触发方式寄存器 +pub const LS7A_INT_CLEAR_REG: usize = LS7A_PCH_REG_BASE + 0x080; //边沿触发中断清除寄存器 +pub const LS7A_INT_HTMSI_VEC_REG: usize = LS7A_PCH_REG_BASE + 0x200; //HT 中断向量寄存器[ 7- 0] +pub const LS7A_INT_STATUS_REG: usize = LS7A_PCH_REG_BASE + 0x3a0; //中断状态（在服务）寄存器 ISR +pub const LS7A_INT_POL_REG: usize = LS7A_PCH_REG_BASE + 0x3e0; //中断触发电平选择寄存器 + +pub fn ls7a_read_w(addr: usize) -> u32 { + unsafe { (addr as *const u32).read_volatile() } +} + +pub fn ls7a_write_w(addr: usize, value: u32) { + unsafe { + (addr as *mut u32).write_volatile(value); + } +} +pub fn ls7a_write_b(addr: usize, value: u8) { + unsafe { + (addr as *mut u8).write_volatile(value); + } +} +pub fn ls7a_read_b(addr: usize) -> u8 { + unsafe { (addr as *const u8).read_volatile() } +} + +pub fn ls7a_read_d(addr: usize) -> u64 { + unsafe { (addr as *const u64).read_volatile() } +} + +pub fn ls7a_write_d(addr: usize, value: u64) { + unsafe { + (addr as *mut u64).write_volatile(value); + } +} + +/// 初始化ls7a中断控制器 +pub fn ls7a_intc_init() { + // enable uart0/keyboard/mouse + // 使能设备的中断 + ls7a_write_w( + LS7A_INT_MASK_REG, + !((0x1 << UART0_IRQ) | (0x1 << KEYBOARD_IRQ) | (0x1 << MOUSE_IRQ)), + ); + // 触发方式设置寄存器 + // 0：电平触发中断 + // 1：边沿触发中断 + // 这里设置为电平触发 + ls7a_write_w( + LS7A_INT_EDGE_REG, + 0x1 << (UART0_IRQ | KEYBOARD_IRQ | MOUSE_IRQ), + ); + // route to the same irq in extioi, pch_irq == extioi_irq + ls7a_write_b(LS7A_INT_HTMSI_VEC_REG + UART0_IRQ, UART0_IRQ as u8); + ls7a_write_b(LS7A_INT_HTMSI_VEC_REG + KEYBOARD_IRQ, KEYBOARD_IRQ as u8); + ls7a_write_b(LS7A_INT_HTMSI_VEC_REG + MOUSE_IRQ, MOUSE_IRQ as u8); + // 设置中断电平触发极性 + // 对于电平触发类型： + // 0：高电平触发； + // 1：低电平触发 + // 这里是高电平触发 + ls7a_write_w(LS7A_INT_POL_REG, 0x0); +} + +pub fn ls7a_intc_complete(irq: u64) { + // 将对应位写1 清除中断 + ls7a_write_d(LS7A_INT_CLEAR_REG, irq); +} diff --git a/crates/loongarch64/src/mem.rs b/crates/loongarch64/src/mem.rs new file mode 100644 index 0000000000..d49e26efac --- /dev/null +++ b/crates/loongarch64/src/mem.rs @@ -0,0 +1,6 @@ +pub enum AccessMemType { + Suc = 0, + Cc = 1, + Wuc = 2, + Saved = 3, +} diff --git a/crates/loongarch64/src/mod.rs b/crates/loongarch64/src/mod.rs new file mode 100644 index 0000000000..b7d0605e8e --- /dev/null +++ b/crates/loongarch64/src/mod.rs @@ -0,0 +1,17 @@ +pub mod cpu; +mod driver; +mod extioi; +mod loongson; +mod ls7a; +pub mod mem; +pub mod register; +mod rtc; +pub mod tlb; + +pub use driver::*; +pub use extioi::{extioi_claim, extioi_complete, extioi_init}; +pub use loongson::*; +pub use ls7a::*; +pub use rtc::{check_rtc, rtc_init, rtc_time_read}; + +pub use driver::{ahci_init, BLOCK_DEVICE}; diff --git a/crates/loongarch64/src/register/badi.rs b/crates/loongarch64/src/register/badi.rs new file mode 100644 index 0000000000..fada9edaad --- /dev/null +++ b/crates/loongarch64/src/register/badi.rs @@ -0,0 +1,26 @@ +use super::csr::Register; +//use super::csr::CSR_BADI; +use core::arch::asm; +// 该寄存器用于记录触发同步类例外的指令的指令码。所谓同步类例外是指除了中断（INT）、客户机 CSR +// 硬件修改例外（GCHC）、机器错误例外（MERR）之外的所有例外。 +#[derive(Debug)] +pub struct Badi { + bits: usize, +} + +impl Register for Badi { + fn read() -> Self { + let mut bits; + //unsafe { asm!("csrrd {},{}", out(reg) bits, const CSR_BADI ) } + unsafe { asm!("csrrd {},0x8", out(reg) bits ) } + Self { bits } + } + + fn write(&mut self) {} +} + +impl Badi { + pub fn get_val(&self) -> usize { + self.bits + } +} diff --git a/crates/loongarch64/src/register/badv.rs b/crates/loongarch64/src/register/badv.rs new file mode 100644 index 0000000000..db06f89f1f --- /dev/null +++ b/crates/loongarch64/src/register/badv.rs @@ -0,0 +1,27 @@ +use super::csr::Register; +use super::csr::CSR_BADV; +use core::arch::asm; +// 该寄存器用于触发地址错误相关例外时，记录出错的虚地址。此类例外包括： +#[derive(Debug)] +pub struct Badv { + bits: usize, +} + +impl Register for Badv { + fn read() -> Self { + let mut bits; + // unsafe { asm!("csrrd {},{}", out(reg) bits,const CSR_BADV ) } + unsafe { asm!("csrrd {},0x7", out(reg) bits ) } + Self { bits } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}",in(reg) self.bits, const CSR_BADV) } + unsafe { asm!("csrwr {},0x7",in(reg) self.bits) } + } +} + +impl Badv { + pub fn get_value(&self) -> usize { + self.bits + } +} diff --git a/crates/loongarch64/src/register/cpuid.rs b/crates/loongarch64/src/register/cpuid.rs new file mode 100644 index 0000000000..00e16b678f --- /dev/null +++ b/crates/loongarch64/src/register/cpuid.rs @@ -0,0 +1,27 @@ +// 该寄存器中存有处理器核编号信息。 + +use super::csr::Register; +use super::csr::CSR_CPUID; +use core::arch::asm; +pub struct Cpuid { + bits: u32, +} + +impl Register for Cpuid { + fn read() -> Self { + let bits: u32; + + unsafe { + //asm!("csrrd {},{}",out(reg) bits, const CSR_CPUID); + asm!("csrrd {},0x20",out(reg) bits); + } + Self { bits } + } + fn write(&mut self) {} +} + +impl Cpuid { + pub fn get_val(&self) -> u32 { + self.bits + } +} diff --git a/crates/loongarch64/src/register/crmd.rs b/crates/loongarch64/src/register/crmd.rs new file mode 100644 index 0000000000..48286c2666 --- /dev/null +++ b/crates/loongarch64/src/register/crmd.rs @@ -0,0 +1,98 @@ +use super::super::cpu::CpuMode; +use super::csr::Register; +use super::csr::CSR_CRMD; +use bit_field::BitField; +use core::arch::asm; +// 当前模式信息 +#[repr(C)] +pub struct Crmd { + bits: usize, +} + +impl Register for Crmd { + fn read() -> Self { + //读取crmd的内容 + let mut crmd; + unsafe { + // asm!("csrrd {},{}", out(reg) crmd,const CSR_CRMD); + asm!("csrrd {},0x0", out(reg) crmd); + } + Crmd { bits: crmd } + } + fn write(&mut self) { + //写入crmd + unsafe { + // asm!("csrwr {},{}", in(reg) self.bits,const CSR_CRMD); + asm!("csrwr {},0x0", in(reg) self.bits); + } + } +} + +impl Crmd { + // 返回整个寄存器的内容 + pub fn get_val(&self) -> usize { + self.bits + } + pub fn set_val(&mut self, val: usize) -> &mut Self { + self.bits = val; + self + } + // 返回当前特权级模式 + // 0-1位 + pub fn get_plv(&self) -> usize { + self.bits.get_bits(0..2) + } + // 设置特权级模式 + pub fn set_plv(&mut self, mode: CpuMode) -> &mut Self { + self.bits.set_bits(0..2, mode as usize); + self + } + // 设置全局中断使能 + // 第2位 + pub fn set_ie(&mut self, enable: bool) -> &mut Self { + self.bits.set_bit(2, enable); + self + } + // 获取全局中断使能 + pub fn get_ie(&self) -> bool { + self.bits.get_bit(2) + } + // 获取DA + pub fn get_da(&self) -> bool { + // 第3位 + self.bits.get_bit(3) + } + // 设置DA,直接地址翻译使能 + pub fn set_da(&mut self, da: bool) -> &mut Self { + self.bits.set_bit(3, da); + self + } + // 获取PG + // 第4位 + pub fn get_pg(&self) -> bool { + self.bits.get_bit(4) + } + // 设置PG,页翻译使能 + pub fn set_pg(&mut self, pg: bool) -> &mut Self { + self.bits.set_bit(4, pg); + self + } + // 获取直接地址翻译模式时，取指操作的存储访问类型 + // 在采用软件处理 TLB 重填的情况下，当软件将 PG 置为 1 时，需同时将 DATF 域置为 + // 0b01，即一致可缓存类型 + pub fn get_datf(&self) -> usize { + self.bits.get_bits(5..=6) + } + pub fn set_datf(&mut self, datf: usize) -> &mut Self { + self.bits.set_bits(5..=6, datf); + self + } + // 直接地址翻译模式时，load 和 store 操作的存储访问类型 + pub fn get_datm(&self) -> usize { + self.bits.get_bits(7..=8) + } + pub fn set_datm(&mut self, datm: usize) -> &mut Self { + self.bits.set_bits(7..=8, datm); + self + } +} diff --git a/crates/loongarch64/src/register/csr.rs b/crates/loongarch64/src/register/csr.rs new file mode 100644 index 0000000000..3b3758c8c4 --- /dev/null +++ b/crates/loongarch64/src/register/csr.rs @@ -0,0 +1,58 @@ +pub trait Register { + fn read() -> Self; + fn write(&mut self); +} +pub const CSR_CRMD: usize = 0x0; +pub const CSR_PRMD: usize = 0x1; +pub const CSR_EUEN: usize = 0x2; +pub const CSR_MISC: usize = 0x3; +pub const CSR_ECFG: usize = 0x4; +pub const CSR_ESTAT: usize = 0x5; +pub const CSR_ERA: usize = 0x6; +pub const CSR_BADV: usize = 0x7; +pub const CSR_BADI: usize = 0x8; +pub const CSR_EENTRY: usize = 0xC; +pub const CSR_TLBIDX: usize = 0x10; +pub const CSR_TLBEHI: usize = 0x11; + +pub const CSR_TLBELO: usize = 0x12; + +pub const CSR_ASID: usize = 0x18; +pub const CSR_PGDL: usize = 0x19; +pub const CSR_PGDH: usize = 0x1A; +pub const CSR_PGD: usize = 0x1B; +pub const CSR_PWCL: usize = 0x1C; +pub const CSR_PWCH: usize = 0x1D; +pub const CSR_STLBPS: usize = 0x1E; +pub const CSR_RVACFG: usize = 0x1F; +pub const CSR_CPUID: usize = 0x20; +pub const CSR_PRCFG1: usize = 0x21; +pub const CSR_PRCFG2: usize = 0x22; +pub const CSR_PRCFG3: usize = 0x23; +pub const CSR_SAVE: usize = 0x30; //0x30 + n(n[0-15] +pub const CSR_TID: usize = 0x40; +pub const CSR_TCFG: usize = 0x41; +pub const CSR_TVAL: usize = 0x42; +pub const CSR_CNTC: usize = 0x43; +pub const CSR_TICLR: usize = 0x44; + +pub const CSR_TLBRENTRY: usize = 0x88; +pub const CSR_TLBRBADV: usize = 0x89; +pub const CSR_TLBRERA: usize = 0x8A; +pub const CSR_TLBRSAVE: usize = 0x8B; + +pub const CSR_TLBRELO: usize = 0x8C; + +pub const CSR_TLBREHI: usize = 0x8E; +pub const CSR_TLBRPRMD: usize = 0x8F; + +pub const CSR_MERRCTL: usize = 0x90; +pub const CSR_MERRINF01: usize = 0x91; +pub const CSR_MERRINF02: usize = 0x92; +pub const CSR_MERRENTRY: usize = 0x93; +pub const CSR_MEMRERA: usize = 0x94; +pub const CSR_MEMRSAVE: usize = 0x95; + +pub const CSR_CTAG: usize = 0x98; + +pub const CSR_DMW: usize = 0x180; //0x180 + n(n[0-3] diff --git a/crates/loongarch64/src/register/dmwn.rs b/crates/loongarch64/src/register/dmwn.rs new file mode 100644 index 0000000000..716841c4ff --- /dev/null +++ b/crates/loongarch64/src/register/dmwn.rs @@ -0,0 +1,109 @@ +use super::csr::Register; +use bit_field::BitField; +use core::arch::asm; +// 直接地址映射配置窗口 +pub struct Dmw0 { + bits: usize, +} +pub struct Dmw1 { + bits: usize, +} +pub struct Dmw2 { + bits: usize, +} +pub struct Dmw3 { + bits: usize, +} + +impl Register for Dmw0 { + fn read() -> Self { + let mut bits: usize; + unsafe { asm!("csrrd {},0x180", out(reg) bits ) } + Dmw0 { bits } + } + fn write(&mut self) { + unsafe { asm!("csrwr {},0x180", in(reg) self.bits ) } + } +} +impl Dmw0 { + pub fn get_value(&self) -> usize { + self.bits + } + pub fn set_value(&mut self, value: usize) -> &mut Self { + self.bits = value; + self + } + pub fn set_plv_with_level(&mut self, level: usize, enable: bool) -> &mut Self { + assert!(level <= 3); + self.bits.set_bit(level, enable); + self + } + pub fn set_mat(&mut self, enable: bool) -> &mut Self { + self.bits.set_bit(4, enable); + self + } + pub fn set_vesg(&mut self, value: usize) -> &mut Self { + self.bits.set_bits(60..64, value); + self + } +} + +impl Register for Dmw1 { + fn read() -> Self { + let mut bits: usize; + unsafe { asm!("csrrd {},0x181", out(reg) bits ) } + Dmw1 { bits } + } + fn write(&mut self) { + unsafe { asm!("csrwr {},0x181", in(reg) self.bits ) } + } +} +impl Dmw1 { + pub fn get_value(&self) -> usize { + self.bits + } + pub fn set_value(&mut self, value: usize) -> &mut Self { + self.bits = value; + self + } +} + +impl Register for Dmw2 { + fn read() -> Self { + let mut bits: usize; + unsafe { asm!("csrrd {},0x182", out(reg) bits ) } + Dmw2 { bits } + } + fn write(&mut self) { + unsafe { asm!("csrwr {},0x182", in(reg) self.bits ) } + } +} +impl Dmw2 { + pub fn get_value(&self) -> usize { + self.bits + } + pub fn set_value(&mut self, value: usize) -> &mut Self { + self.bits = value; + self + } +} + +impl Register for Dmw3 { + fn read() -> Self { + let mut bits: usize; + unsafe { asm!("csrrd {},0x183", out(reg) bits ) } + Dmw3 { bits } + } + fn write(&mut self) { + unsafe { asm!("csrwr {},0x183", in(reg) self.bits ) } + } +} +impl Dmw3 { + pub fn get_value(&self) -> usize { + self.bits + } + pub fn set_value(&mut self, value: usize) -> &mut Self { + self.bits = value; + self + } +} diff --git a/crates/loongarch64/src/register/ecfg.rs b/crates/loongarch64/src/register/ecfg.rs new file mode 100644 index 0000000000..8fbb93ed67 --- /dev/null +++ b/crates/loongarch64/src/register/ecfg.rs @@ -0,0 +1,51 @@ +use super::csr::{Register, CSR_ECFG}; +use bit_field::BitField; +use core::arch::asm; +/// 控制例外和中断的入口地址计算方式，以及局部中断使能 +pub struct Ecfg { + bits: usize, +} +impl Register for Ecfg { + fn read() -> Self { + let mut bits; + // unsafe { asm!("csrrd {},{}", out(reg) bits,const CSR_ECFG ) } + unsafe { asm!("csrrd {},0x4", out(reg) bits ) } + Self { bits } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}", in(reg) self.bits,const CSR_ECFG ) } + unsafe { asm!("csrwr {},0x4", in(reg) self.bits ) } + } +} + +impl Ecfg { + pub fn get_val(&self) -> usize { + self.bits + } + pub fn set_val(&mut self, val: usize) -> &mut Self { + self.bits = val; + self + } + pub fn get_lie_with_index(&self, index: usize) -> bool { + // 中断位于0-12位,每一位代表一个局部中断 + assert!(index < 13); + self.bits.get_bit(index) + } + pub fn set_lie_with_index(&mut self, index: usize, val: bool) -> &mut Self { + // 中断位于0-12位,每一位代表一个局部中断 + assert!(index < 13); + self.bits.set_bit(index, val); + self + } + // 例外处理中断入口的间距 + // 16-18位 + // 当此值为0 时，例外处理中断入口是同一个地址 + // 不为0时，每个异常有自己的中断入口 + pub fn get_vs(&self) -> usize { + self.bits.get_bits(16..19) + } + pub fn set_vs(&mut self, value: usize) -> &mut Self { + self.bits.set_bits(16..19, value); + self + } +} diff --git a/crates/loongarch64/src/register/eentry.rs b/crates/loongarch64/src/register/eentry.rs new file mode 100644 index 0000000000..f66bb40fe6 --- /dev/null +++ b/crates/loongarch64/src/register/eentry.rs @@ -0,0 +1,29 @@ +//例外入口地址 + +use super::csr::Register; +use core::arch::asm; +pub struct Eentry { + bits: usize, +} +impl Register for Eentry { + fn read() -> Self { + let bits: usize; + unsafe { asm!("csrrd {},0xc", out(reg) bits, ) } + Eentry { bits } + } + fn write(&mut self) { + unsafe { asm!("csrwr {},0xc", in(reg) self.bits, ) } + } +} + +impl Eentry { + pub fn get_eentry(&self) -> usize { + // 12位以后,以页对齐 + self.bits + } + pub fn set_eentry(&mut self, eentry: usize) -> &mut Self { + assert!(eentry & 0xfff == 0); + self.bits = eentry; + self + } +} diff --git a/crates/loongarch64/src/register/era.rs b/crates/loongarch64/src/register/era.rs new file mode 100644 index 0000000000..a1103dfe6e --- /dev/null +++ b/crates/loongarch64/src/register/era.rs @@ -0,0 +1,37 @@ +use super::csr::{Register, CSR_ERA}; +use core::arch::asm; +// 该寄存器记录普通例外处理完毕之后的返回地址。当触发例外时，如果例外类型既不是 TLB 重填例外 +// 也不是机器错误例外，则触发例外的指令的 PC 将被记录在该寄存器中 +pub struct Era { + bits: usize, +} + +impl Register for Era { + fn read() -> Self { + //读取era的内容出来 + let mut era; + unsafe { + // asm!("csrrd {},{}", out(reg) era,const CSR_ERA); + asm!("csrrd {},0x6", out(reg) era); + } + Era { bits: era } + } + fn write(&mut self) { + //写入era的内容 + unsafe { + // asm!("csrwr {},{}", in(reg) self.bits,const CSR_ERA); + asm!("csrwr {},0x6", in(reg) self.bits); + } + } +} + +impl Era { + pub fn set_pc(&mut self, pc: usize) -> &mut Self { + self.bits = pc; + self + } + pub fn get_pc(&self) -> usize { + // 返回pc + self.bits + } +} diff --git a/crates/loongarch64/src/register/estat.rs b/crates/loongarch64/src/register/estat.rs new file mode 100644 index 0000000000..3fe95ae9b3 --- /dev/null +++ b/crates/loongarch64/src/register/estat.rs @@ -0,0 +1,178 @@ +use super::super::tlb::TLBREra; +use super::csr::Register; +use super::csr::CSR_ESTAT; +use super::ecfg::Ecfg; +use bit_field::BitField; +use core::arch::asm; +// 该寄存器记录例外的状态信息，包括所触发例外的一二级编码，以及各中断的状态 +#[derive(Debug, Clone, Copy)] +pub struct Estat { + pub bits: usize, +} + +impl Register for Estat { + fn read() -> Self { + //读取sstat的内容出来 + let mut bits; + unsafe { + // asm!("csrrd {},{}", out(reg) bits,const CSR_ESTAT); + asm!("csrrd {}, 0x5", out(reg) bits); + } + Estat { bits } + } + fn write(&mut self) { + unsafe { + // asm!("csrwr {},{}", in(reg) self.bits,const CSR_ESTAT); + asm!("csrwr {}, 0x5", in(reg) self.bits); + } + } +} + +impl Estat { + pub fn get_val(&self) -> usize { + self.bits + } + pub fn set_val(&mut self, val: usize) -> &mut Self { + self.bits = val; + self + } + pub fn get_is_with_index(&self, index: usize) -> bool { + // 0-12位为中断 + assert!(index < 13); + self.bits.get_bit(index) + } + // 只有写0和1位有效，这两位控制软件中断 + pub fn set_is_with_index(&mut self, index: usize, value: bool) -> &mut Self { + assert!(index < 13); + self.bits.set_bit(index, value); + self + } + // 例外类型一级编码。触发例外时： + // 如果是 TLB 重填例外或机器错误例外，该域保持不变； + // 否则，硬件会根据例外类型将表 7- 8 中 Ecode 栏定义的数值写入该域。 + //例外类型一级编号 21-16位 + pub fn get_ecode(&self) -> usize { + self.bits.get_bits(16..=21) + } + //例外类型二级编号 22-30位 + pub fn get_esubcode(&self) -> usize { + self.bits.get_bits(22..=30) + } + + pub fn cause(&self) -> Trap { + // 优先判断是否是重填异常 + let is_tlb_reload = TLBREra::read().get_is_tlbr(); + if is_tlb_reload { + return Trap::Exception(Exception::TLBRFill); + } + let ecode = self.get_ecode(); + if ecode == 0 { + // 仅当 CSR.ECFG.VS=0 时，表示是中断 + let ecfg = Ecfg::read(); + let ecfg_vs = ecfg.get_vs(); + if ecfg_vs == 0 { + // 读取中断位 + for index in (0..13).rev() { + if self.get_is_with_index(index) && ecfg.get_lie_with_index(index) { + //log::debug!("index={:#x?}", index); + return Trap::Interrupt(Interrupt::from_usize(index)); + } + } + } + return Trap::Unknown; + } + let sub_ecode = self.get_esubcode(); + match ecode { + 0x1 => Trap::Exception(Exception::LoadPageInvalid), // load + 0x2 => Trap::Exception(Exception::StorePageInvalid), // store + 0x3 => Trap::Exception(Exception::FetchPageInvalid), //取指操作页面不存在 + 0x4 => Trap::Exception(Exception::PageModification), //页修改例外 + 0x5 => Trap::Exception(Exception::PageNonReadable), //页不可读 + 0x6 => Trap::Exception(Exception::PageNonExecutable), //页不可执行 + 0x7 => Trap::Exception(Exception::PagePrivilegeIllegal), //页特权级不合规 + 0x8 => { + match sub_ecode { + 0x1 => Trap::Exception(Exception::FetchInstructionAddressError), //取指地址错误 + 0x2 => Trap::Exception(Exception::MemoryAccessInstructionAddressError), //访存地址访问错误 + _ => Trap::Unknown, + } + } + 0x9 => Trap::Exception(Exception::AddressAlignmentFault), //地址不对齐 + 0xa => Trap::Exception(Exception::BoundCheck), //越界例外 + 0xb => Trap::Exception(Exception::Syscall), //系统调用 + 0xc => Trap::Exception(Exception::Breakpoint), //调试中断 + 0xd => Trap::Exception(Exception::InstructionNonDefined), //指令不合规 + 0xe => Trap::Exception(Exception::InstructionPrivilegeError), //指令特权级不合规 + 0xf => Trap::Exception(Exception::FloatingPointInstructionDisable), //浮点处理器不可用 + _ => Trap::Unknown, + } + } +} + +// 异常类型 +#[derive(Debug, Clone, Copy)] +pub enum Exception { + LoadPageInvalid, + StorePageInvalid, + FetchPageInvalid, + PageModification, + PageNonReadable, + PageNonExecutable, + PagePrivilegeIllegal, + FetchInstructionAddressError, + MemoryAccessInstructionAddressError, //内存访问错误 + AddressAlignmentFault = 0x9, //地址不对齐 + BoundCheck = 0xA, //越界检查错误 + Syscall = 0xB, //系统调用 + Breakpoint = 0xC, //调试中断 + InstructionNonDefined = 0xD, //指令不合规 + InstructionPrivilegeError = 0xE, //特权指令不合规 + FloatingPointInstructionDisable = 0xF, //浮点不可用 + TLBRFill, //TLB重填 +} + +// 中断类型 +#[derive(Debug, Clone, Copy)] +pub enum Interrupt { + SWI0, //软件中断0 + SWI1, //软件中断1 + HWI0, //硬件中断0 + HWI1, //硬件中断1 + HWI2, //硬件中断2 + HWI3, //硬件中断3 + HWI4, //硬件中断4 + HWI5, //硬件中断5 + HWI6, //硬件中断6 + HWI7, //硬件中断7 + PMI, //性能监测计数溢出中断 + Timer, //定时器中断 + IPI, //多处理器间的中断 +} + +impl Interrupt { + pub fn from_usize(value: usize) -> Self { + match value { + 0 => Interrupt::SWI0, + 1 => Interrupt::SWI1, + 2 => Interrupt::HWI0, + 3 => Interrupt::HWI1, + 4 => Interrupt::HWI2, + 5 => Interrupt::HWI3, + 6 => Interrupt::HWI4, + 7 => Interrupt::HWI5, + 8 => Interrupt::HWI6, + 9 => Interrupt::HWI7, + 10 => Interrupt::PMI, + 11 => Interrupt::Timer, + 12 => Interrupt::IPI, + _ => panic!("invalid interrupt index"), + } + } +} + +#[derive(Debug, Clone, Copy)] +pub enum Trap { + Exception(Exception), + Interrupt(Interrupt), + Unknown, +} diff --git a/crates/loongarch64/src/register/misc.rs b/crates/loongarch64/src/register/misc.rs new file mode 100644 index 0000000000..6076148917 --- /dev/null +++ b/crates/loongarch64/src/register/misc.rs @@ -0,0 +1,40 @@ +use super::csr::{Register, CSR_MISC}; +use bit_field::BitField; +use core::arch::asm; + +pub struct Misc { + bits: u32, +} + +impl Register for Misc { + fn read() -> Self { + let bits: u32; + unsafe { + // asm!("csrrd {},{}",out(reg)bits,const CSR_MISC); + asm!("csrrd {},0x3",out(reg)bits); + } + Self { bits } + } + fn write(&mut self) { + unsafe { + // asm!("csrwr {},{}",in(reg)self.bits,const CSR_MISC); + asm!("csrwr {},0x3",in(reg)self.bits); + } + } +} +impl Misc { + pub fn get_enable_32_in_plv1(&self) -> bool { + self.bits.get_bit(1) + } + pub fn set_enable_32_in_plv1(&mut self, value: bool) -> &mut Self { + self.bits.set_bit(1, value); + self + } + pub fn get_enable_32_in_plv3(&self) -> bool { + self.bits.get_bit(3) + } + pub fn set_enable_32_in_plv3(&mut self, value: bool) -> &mut Self { + self.bits.set_bit(3, value); + self + } +} diff --git a/crates/loongarch64/src/register/mod.rs b/crates/loongarch64/src/register/mod.rs new file mode 100644 index 0000000000..aa360dfd87 --- /dev/null +++ b/crates/loongarch64/src/register/mod.rs @@ -0,0 +1,26 @@ +//! loongArch的一些寄存器 + +pub mod badi; +pub mod badv; +pub mod cpuid; +pub mod crmd; +pub mod csr; +pub mod dmwn; +pub mod ecfg; +pub mod eentry; +pub mod era; +pub mod estat; +mod misc; +pub mod prcfg1; +pub mod prcfg2; +pub mod prcfg3; +pub mod prmd; +pub mod rvacfg; +pub mod saven; +pub mod tcfg; +pub mod ticlr; +pub mod tval; + +pub mod time; + +pub use misc::Misc; diff --git a/crates/loongarch64/src/register/prcfg1.rs b/crates/loongarch64/src/register/prcfg1.rs new file mode 100644 index 0000000000..56d259d2aa --- /dev/null +++ b/crates/loongarch64/src/register/prcfg1.rs @@ -0,0 +1,34 @@ +use super::csr::{Register, CSR_PRCFG1}; +use bit_field::BitField; +use core::arch::asm; +#[derive(Debug)] +pub struct Prcfg1 { + // [0-3] Savenum 保存数据寄存器的数量 + // [4-11] TimerBits 定时器的位数-1 + // [12-14] 例外入口地址间距的 vs可以设置的最大值 + // [15-31] 0 + bits: usize, +} + +impl Register for Prcfg1 { + fn read() -> Self { + let mut bits; + // unsafe { asm!("csrrd {},{}", out(reg) bits,const CSR_PRCFG1 ) } + unsafe { asm!("csrrd {},0x21", out(reg) bits ) } + Self { bits } + } + fn write(&mut self) {} +} + +impl Prcfg1 { + pub fn get_save_num(&self) -> usize { + self.bits.get_bits(0..4) + } + pub fn get_timer_bits(&self) -> usize { + // 返回定时器的位数 + self.bits.get_bits(4..12) + 1 + } + pub fn get_vs_max(&self) -> usize { + self.bits.get_bits(12..15) + } +} diff --git a/crates/loongarch64/src/register/prcfg2.rs b/crates/loongarch64/src/register/prcfg2.rs new file mode 100644 index 0000000000..4eca4e160f --- /dev/null +++ b/crates/loongarch64/src/register/prcfg2.rs @@ -0,0 +1,25 @@ +use super::csr::Register; +use super::csr::CSR_PRCFG2; +use core::arch::asm; +// 指示 TLB 能够支持的页大小（Page Size）。当第 i 位为 1，表明支持 2 +// i字节大小的页 +pub struct Prcfg2 { + bits: usize, +} +impl Register for Prcfg2 { + fn read() -> Self { + let bits: usize; + unsafe { + // asm!("csrrd {},{}",out(reg) bits,const CSR_PRCFG2); + asm!("csrrd {},0x22",out(reg) bits); + } + Self { bits } + } + fn write(&mut self) {} +} + +impl Prcfg2 { + pub fn get_val(&self) -> usize { + self.bits + } +} diff --git a/crates/loongarch64/src/register/prcfg3.rs b/crates/loongarch64/src/register/prcfg3.rs new file mode 100644 index 0000000000..24bd1a15e2 --- /dev/null +++ b/crates/loongarch64/src/register/prcfg3.rs @@ -0,0 +1,46 @@ +use super::csr::Register; +use super::csr::CSR_PRCFG3; +use bit_field::BitField; +use core::arch::asm; +// 该寄存器包含一些特权资源的配置信息。 +pub struct Prcfg3 { + bits: u32, +} +impl Register for Prcfg3 { + fn read() -> Self { + let bits: u32; + unsafe { + // asm!("csrrd {},{}",out(reg) bits,const CSR_PRCFG3); + asm!("csrrd {},0x23",out(reg) bits); + } + Self { bits } + } + fn write(&mut self) {} +} + +impl Prcfg3 { + // 指示 TLB 组织方式： + // 0：没有 TLB； + // 1：一个全相联的多重页大小 TLB（MTLB） + // 2：一个全相联的多重页大小 TLB（MTLB）+一个组相联的单个页大小 TLB（STLB）； + // 其它值：保留。 + + pub fn get_tlb_type(&self) -> u32 { + self.bits.get_bits(0..=3) + } + // 当 TLBType=1 或 2 时，该域的值是全相联多重页大小 TLB 的项数减 1 + pub fn get_mtlb_entries(&self) -> u32 { + self.bits.get_bits(4..=11) + } + + // STLBWays + pub fn get_stlb_ways(&self) -> u32 { + self.bits.get_bits(12..=19) + 1 + } + + // 当 TLBType=2 时，该域的值是组相联单个页大小 TLB 的每一路项数的幂指数，即每一 + // 路有 2 ^ STLBSets项。 + pub fn get_sltb_sets(&self) -> u32 { + self.bits.get_bits(20..=25) + } +} diff --git a/crates/loongarch64/src/register/prmd.rs b/crates/loongarch64/src/register/prmd.rs new file mode 100644 index 0000000000..cbd8b4b80c --- /dev/null +++ b/crates/loongarch64/src/register/prmd.rs @@ -0,0 +1,65 @@ +use super::super::cpu::CpuMode; +use super::csr::{Register, CSR_PRMD}; +use bit_field::BitField; +use core::arch::asm; +// 当触发例外时，如果例外类型不是 TLB 重填例外和机器错误例外，硬件会将此时处理器核的特权等级、 +// 全局中断使能和监视点使能位保存至例外前模式信息寄存器中，用于例外返回时恢复处理器核的现场 +pub struct Prmd { + bits: usize, +} + +impl Register for Prmd { + fn read() -> Self { + let mut bits; + // unsafe { asm!("csrrd {},{}", out(reg) bits ,const CSR_PRMD) } + unsafe { asm!("csrrd {},0x1", out(reg) bits) } + Self { bits } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}", in(reg) self.bits ,const CSR_PRMD) } + unsafe { asm!("csrwr {},0x1", in(reg) self.bits) } + } +} + +impl Prmd { + pub fn get_val(&self) -> usize { + self.bits + } + pub fn set_val(&mut self, val: usize) -> &mut Self { + self.bits = val; + self + } + + // 当触发例外时，如果例外类型不是 TLB 重填例外和机器错误例外，硬件会将 CSR.CRMD + // 中 PLV 域的旧值记录在这个域。 + // 当所处理的例外既不是 TLB 重填例外（CSR.TLBRERA.IsTLBR=0）也不是机器错误例外 + // （CSR.ERRCTL.IsMERR=0）时，执行 ERTN 指令从例外处理程序返回时，硬件会将这个 + // 域的值恢复到 CSR.CRMD 的 PLV 域 + pub fn get_pplv(&self) -> usize { + self.bits.get_bits(0..2) + } + pub fn set_pplv(&mut self, pplv: CpuMode) -> &mut Self { + //设置特权级 + // 用于在进入用户程序时设置特权级 + self.bits.set_bits(0..2, pplv as usize); + self + } + // 记录例外发生前的crmd.ie + pub fn get_pie(&self) -> bool { + self.bits.get_bit(2) + } + // 设置中断使能 + // 用于在进入用户程序时设置中断使能 + pub fn set_pie(&mut self, pie: bool) -> &mut Self { + self.bits.set_bit(2, pie); + self + } + + pub fn get_pwe(&self) -> bool { + self.bits.get_bit(3) + } + pub fn set_pwe(&mut self, pwe: bool) -> &mut Self { + self.bits.set_bit(3, pwe); + self + } +} diff --git a/crates/loongarch64/src/register/rvacfg.rs b/crates/loongarch64/src/register/rvacfg.rs new file mode 100644 index 0000000000..eeaa68bb20 --- /dev/null +++ b/crates/loongarch64/src/register/rvacfg.rs @@ -0,0 +1,37 @@ +use super::csr::Register; +use super::csr::CSR_RVACFG; +use core::arch::asm; +// 该寄存器用于控制虚地址缩减模式下被缩减的地址位宽。 +pub struct RvaCfg { + bits: u32, +} + +impl Register for RvaCfg { + fn read() -> Self { + let bits: u32; + unsafe { + // asm!("csrrd {},{}",out(reg) bits, const CSR_RVACFG); + asm!("csrrd {},0x1F",out(reg) bits); + } + Self { bits } + } + fn write(&mut self) { + unsafe { + // asm!("csrwr {},{}",in(reg) self.bits, const CSR_RVACFG); + asm!("csrwr {},0x1F",in(reg) self.bits); + } + } +} + +impl RvaCfg { + fn get_val(&self) -> u32 { + self.bits + } + // 虚地址缩减模式下，被缩减的高位地址的位数。可以配置为 0~8 之间的值。 + // 0 是一个特殊的配置值，意味着不启用虚地址缩减模式。 + // 如果配置的值大于 8，则处理器行为不确定 + fn set_val(&mut self, val: u32) -> &mut Self { + self.bits = val; + self + } +} diff --git a/crates/loongarch64/src/register/saven.rs b/crates/loongarch64/src/register/saven.rs new file mode 100644 index 0000000000..e4b3594991 --- /dev/null +++ b/crates/loongarch64/src/register/saven.rs @@ -0,0 +1,35 @@ +// 数据保存控制状态寄存器用于给系统软件暂存数据。每个数据保存寄存器可以存放一个通用寄存器的数据。 +// 数据保存寄存器最少实现 1 个，最多实现 16 个 + +use crate::register::csr::Register; +use core::arch::asm; + +pub struct SaveReg0 { + bits: usize, +} + +impl Register for SaveReg0 { + fn read() -> Self { + unsafe { + let mut bit: usize; + asm!("csrrd {},0x30",out(reg) bit); + Self { bits: bit } + } + } + + fn write(&mut self) { + unsafe { + asm!("csrwr {},0x30",in(reg) self.bits); + } + } +} + +impl SaveReg0 { + pub fn get_value(&self) -> usize { + self.bits + } + pub fn set_value(&mut self, value: usize) -> &mut Self { + self.bits = value; + self + } +} diff --git a/crates/loongarch64/src/register/tcfg.rs b/crates/loongarch64/src/register/tcfg.rs new file mode 100644 index 0000000000..28c9f827a1 --- /dev/null +++ b/crates/loongarch64/src/register/tcfg.rs @@ -0,0 +1,61 @@ +use super::csr::Register; +use bit_field::BitField; +use core::arch::asm; + +// 定时器寄存器 +// 该寄存器是软件配置定时器的接口。定时器的有效位数由实现决定，因此该寄存器中 TimeVal 域的位 +// 宽也将随之变化。 +#[derive(Debug)] +pub struct Tcfg { + // [0] 使能位 + // [1] 循环控制位 + // [2-]计时器数值， 为4的整数倍 + bits: usize, +} + +impl Register for Tcfg { + fn read() -> Self { + let mut tcfg; + unsafe { asm!("csrrd {} , 0x41", out(reg) tcfg, ) } + Self { bits: tcfg } + } + fn write(&mut self) { + unsafe { asm!("csrwr {}, 0x41", in(reg) self.bits, ) } + } +} + +impl Tcfg { + pub fn get_enable(&self) -> bool { + //第0位 + !self.bits.get_bit(0) + } + pub fn set_enable(&mut self, enable: bool) -> &mut Self { + self.bits.set_bit(0, enable); + self + } + pub fn get_loop(&self) -> bool { + //第1位 + self.bits.get_bit(1) + } + pub fn set_loop(&mut self, loop_: bool) -> &mut Self { + self.bits.set_bit(1, loop_); + self + } + pub fn get_initval(&self) -> usize { + //第2位开始 + (self.bits >> 2) << 2 + } + pub fn set_initval(&mut self, val: usize) -> &mut Self { + // 设置计数值, 只能是4的整数倍 + // 在数值末尾会补上2bit0 + self.bits.set_bits(2.., val >> 2); + self + } + pub fn get_val(&self) -> usize { + self.bits + } + pub fn set_val(&mut self, val: usize) -> &mut Self { + self.bits = val; + self + } +} diff --git a/crates/loongarch64/src/register/ticlr.rs b/crates/loongarch64/src/register/ticlr.rs new file mode 100644 index 0000000000..7d87d8ee72 --- /dev/null +++ b/crates/loongarch64/src/register/ticlr.rs @@ -0,0 +1,33 @@ +use super::csr::{Register, CSR_TICLR}; +use bit_field::BitField; +use core::arch::asm; +pub struct Ticlr { + bits: u32, +} + +impl Register for Ticlr { + fn read() -> Self { + let mut ticlr; + // unsafe { asm!("csrrd {},{}", out(reg)ticlr,const CSR_TICLR) } + unsafe { asm!("csrrd {},0x44", out(reg)ticlr) } + Ticlr { bits: ticlr } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}", in(reg)self.bits,const CSR_TICLR) } + unsafe { asm!("csrwr {},0x44", in(reg)self.bits) } + } +} + +impl Ticlr { + pub fn set_val(&mut self, val: u32) -> &mut Self { + self.bits = val; + self + } + pub fn get_val(&self) -> u32 { + self.bits + } + pub fn clear_timer(&mut self) -> &mut Self { + self.bits.set_bit(0, true); + self + } +} diff --git a/crates/loongarch64/src/register/time.rs b/crates/loongarch64/src/register/time.rs new file mode 100644 index 0000000000..8acbd9bb9e --- /dev/null +++ b/crates/loongarch64/src/register/time.rs @@ -0,0 +1,30 @@ +use super::super::cpu::CPUCFG; +use core::arch::asm; +pub struct Time {} + +impl Time { + pub fn read() -> usize { + let mut counter: usize; + unsafe { + asm!( + "rdtime.d {},{}", + out(reg)counter, + out(reg)_, + ); + } + counter + } +} + +pub fn get_timer_freq() -> usize { + // 获取时钟晶振频率 + // 配置信息字index:4 + let base_freq = CPUCFG::read(4).get_bits(0, 31); + // 获取时钟倍频因子 + // 配置信息字index:5 位:0-15 + let mul = CPUCFG::read(5).get_bits(0, 15); + let div = CPUCFG::read(5).get_bits(16, 31); + // 计算时钟频率 + let cc_freq = base_freq * mul / div; + cc_freq +} diff --git a/crates/loongarch64/src/register/tval.rs b/crates/loongarch64/src/register/tval.rs new file mode 100644 index 0000000000..24e6638234 --- /dev/null +++ b/crates/loongarch64/src/register/tval.rs @@ -0,0 +1,21 @@ +use super::csr::{Register, CSR_TVAL}; +use core::arch::asm; +pub struct Tval { + bits: u32, +} + +impl Register for Tval { + fn read() -> Self { + let mut tval; + // unsafe { asm!("csrrd {},{}", out(reg)ticlr,const CSR_TICLR) } + unsafe { asm!("csrrd {},0x42", out(reg)tval) } + Tval { bits: tval } + } + fn write(&mut self) {} +} + +impl Tval { + pub fn get_val(&self) -> u32 { + self.bits + } +} diff --git a/crates/loongarch64/src/rtc.rs b/crates/loongarch64/src/rtc.rs new file mode 100644 index 0000000000..2fb9bf9fe7 --- /dev/null +++ b/crates/loongarch64/src/rtc.rs @@ -0,0 +1,80 @@ +use alloc::format; +use alloc::string::{String, ToString}; +use core::fmt::{Debug, Formatter}; +use rlibc::memcmp; +use crate::loongarch64::{ls7a_read_w, ls7a_write_w, LS7A_RTC_REG_BASE}; +use crate::println; +use bit_field::BitField; + +pub const RTC_YEAR: usize = 0x30; +pub const RTC_TOYREAD0: usize = 0x2c; //月日时分 +pub const RTC_CTRL: usize = 0x40; + +pub struct RtcTime { + pub year: u32, + pub month: u32, + pub day: u32, + pub hour: u32, + pub minute: u32, + pub second: u32, +} + +impl Debug for RtcTime { + fn fmt(&self, f: &mut Formatter<'_>) -> core::fmt::Result { + write!( + f, + "{}-{}-{} {}:{}:{}", + self.year, self.month, self.day, self.hour, self.minute, self.second + ) + } +} + +impl ToString for RtcTime { + fn to_string(&self) -> String { + format!( + "{}:{}:{}\n{}-{}-{}", + self.hour, self.minute, self.second, self.year, self.month, self.day + ) + } +} + +/// 编译器会报出找不到bcmp的错误，这里将其实现为memcmp +#[no_mangle] +pub unsafe extern "C" fn bcmp(s1: *const u8, s2: *const u8, n: usize) -> i32 { + memcmp(s1, s2, n) +} + + +pub fn rtc_time_read() -> RtcTime { + let value = ls7a_read_w(LS7A_RTC_REG_BASE + RTC_TOYREAD0); + let sec = (value >> 4) & 0x3f; + let min = (value >> 10) & 0x3f; + let mut hour = (value >> 16) & 0x1f; + let day = (value >> 21) & 0x1f; + let mon = (value >> 26) & 0x3f; + let year = ls7a_read_w(LS7A_RTC_REG_BASE + RTC_YEAR) + 1900; + hour = (hour + 8) % 24; + return RtcTime { + year, + month: mon, + day, + hour, + minute: min, + second: sec, + }; +} +pub fn check_rtc() { + let val = ls7a_read_w(LS7A_RTC_REG_BASE + RTC_CTRL); + println!( + "RTC enable:{}, TOY enable:{}", + val.get_bit(13), + val.get_bit(11) + ); +} + +pub fn rtc_init() { + let mut val = ls7a_read_w(LS7A_RTC_REG_BASE + RTC_CTRL); + val.set_bit(13, true); + val.set_bit(11, true); + ls7a_write_w(LS7A_RTC_REG_BASE + RTC_CTRL, val); +} diff --git a/crates/loongarch64/src/tlb/asid.rs b/crates/loongarch64/src/tlb/asid.rs new file mode 100644 index 0000000000..92579fa8a8 --- /dev/null +++ b/crates/loongarch64/src/tlb/asid.rs @@ -0,0 +1,40 @@ +use super::super::register::csr::Register; +use super::super::register::csr::CSR_ASID; +use bit_field::BitField; +use core::arch::asm; + +// 该寄存器中包含了用于访存操作和 TLB 指令的地址空间标识符（ASID）信息。ASID 的位宽随着架构规 +// 范的演进可能进一步增加，为方便软件明确 ASID 的位宽，将直接给出这一信息 +pub struct Asid { + bits: u32, +} + +impl Register for Asid { + fn read() -> Self { + let bits: u32; + // unsafe { asm!("csrrd {},{}",out(reg)bits,const CSR_ASID) } + unsafe { asm!("csrrd {},0x18",out(reg)bits) } + Self { bits } + } + fn write(&mut self) { + //unsafe { asm!("csrwr {},{}", in(reg)self.bits,const CSR_ASID) } + unsafe { asm!("csrwr {},0x18", in(reg)self.bits) } + } +} +impl Asid { + pub fn get_asid(&self) -> u32 { + self.bits.get_bits(0..10) + } + pub fn set_asid(&mut self, asid: u32) -> &mut Self { + self.bits.set_bits(0..10, asid); + self + } + + pub fn get_asid_width(&self) -> u32 { + self.bits.get_bits(16..=23) + } + pub fn set_asid_width(&mut self, asid_width: u32) -> &mut Self { + self.bits.set_bits(16..=23, asid_width); + self + } +} diff --git a/crates/loongarch64/src/tlb/mod.rs b/crates/loongarch64/src/tlb/mod.rs new file mode 100644 index 0000000000..7b60430cbd --- /dev/null +++ b/crates/loongarch64/src/tlb/mod.rs @@ -0,0 +1,35 @@ +//此模块负责管理LoongArch有关TLB和页表的寄存器与相关功能 +mod asid; +mod pgd; +mod pgdh; +mod pgdl; +pub mod pwch; +pub mod pwcl; +mod stlbps; +mod tlbehi; +mod tlbelo; +mod tlbentry; +mod tlbidx; +mod tlbrbadv; +mod tlbrehi; +mod tlbrelo; +mod tlbrera; +mod tlbrprmd; +mod tlbrsave; + +pub use asid::Asid; +pub use pgd::Pgd; +pub use pgdh::Pgdh; +pub use pgdl::Pgdl; +pub use pwch::Pwch; +pub use pwcl::Pwcl; +pub use stlbps::StlbPs; +pub use tlbehi::TlbEHi; +pub use tlbelo::{TLBEL, TLBELO}; +pub use tlbentry::TLBREntry; +pub use tlbidx::TlbIdx; +pub use tlbrbadv::TlbRBadv; +pub use tlbrehi::TlbREhi; +pub use tlbrelo::TlbRelo; +pub use tlbrera::TLBREra; +pub use tlbrprmd::TlbRPrmd; diff --git a/crates/loongarch64/src/tlb/pgd.rs b/crates/loongarch64/src/tlb/pgd.rs new file mode 100644 index 0000000000..6b57e9f10f --- /dev/null +++ b/crates/loongarch64/src/tlb/pgd.rs @@ -0,0 +1,28 @@ +// 该寄存器是一个只读寄存器，其内容是当前上下文中出错虚地址所对应的全局目录基址信息。该寄存 +// 器的只读信息，不仅用于 CSR 类指令的读返回值，也用于 LDDIR 指令访问全局目录时所需的基址信息 + +use super::super::register::csr::Register; +use super::super::register::csr::CSR_PGD; +use core::arch::asm; + +pub struct Pgd { + pub pgd: usize, +} + +impl Register for Pgd { + fn read() -> Self { + let bits: usize; + unsafe { + // asm!("csrrd {},{}",out(reg)bits,const CSR_PGD); + asm!("csrrd {},0x1b",out(reg)bits); + } + Self { pgd: bits } + } + fn write(&mut self) {} +} + +impl Pgd { + pub fn get_val(&self) -> usize { + self.pgd + } +} diff --git a/crates/loongarch64/src/tlb/pgdh.rs b/crates/loongarch64/src/tlb/pgdh.rs new file mode 100644 index 0000000000..8819d2224c --- /dev/null +++ b/crates/loongarch64/src/tlb/pgdh.rs @@ -0,0 +1,33 @@ +// 该寄存器用于配置高半地址空间的全局目录的基址。要求全局目录的基址一定是 4KB 边界地址对齐的， +// 所以该寄存器的最低 12 位软件不可配置，只读恒为 0。 + +use super::super::register::csr::Register; +use super::super::register::csr::CSR_PGDH; +use core::arch::asm; +pub struct Pgdh { + bits: usize, +} + +impl Register for Pgdh { + fn read() -> Self { + let bits: usize; + // unsafe { asm!("csrrd {},{}",out(reg)bits,const CSR_PGDH) } + unsafe { asm!("csrrd {},0x1a",out(reg)bits) } + Self { bits } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}",in(reg)self.bits,const CSR_PGDH) } + unsafe { asm!("csrwr {},0x1a",in(reg)self.bits) } + } +} +impl Pgdh { + pub fn get_val(&self) -> usize { + self.bits + } + pub fn set_val(&mut self, val: usize) -> &mut Self { + // 确保地址是 4KB 边界地址对齐的 + assert!(val & 0xFFF == 0); + self.bits = val; + self + } +} diff --git a/crates/loongarch64/src/tlb/pgdl.rs b/crates/loongarch64/src/tlb/pgdl.rs new file mode 100644 index 0000000000..3df901d941 --- /dev/null +++ b/crates/loongarch64/src/tlb/pgdl.rs @@ -0,0 +1,33 @@ +// 该寄存器用于配置低半地址空间的全局目录的基址。要求全局目录的基址一定是 4KB 边界地址对齐的， +// 所以该寄存器的最低 12 位软件不可配置，只读恒为 0 + +use super::super::register::csr::Register; +use super::super::register::csr::CSR_PGDL; +use core::arch::asm; +pub struct Pgdl { + bits: usize, +} + +impl Register for Pgdl { + fn read() -> Self { + let bits: usize; + // unsafe { asm!("csrrd {},{}",out(reg)bits,const CSR_PGDL) } + unsafe { asm!("csrrd {},0x19",out(reg)bits) } + Self { bits } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}",in(reg)self.bits,const CSR_PGDL) } + unsafe { asm!("csrwr {},0x19",in(reg)self.bits) } + } +} +impl Pgdl { + pub fn get_val(&self) -> usize { + self.bits + } + pub fn set_val(&mut self, val: usize) -> &mut Self { + // 确保地址是 4KB 边界地址对齐的 + assert!(val & 0xFFF == 0); + self.bits = val; + self + } +} diff --git a/crates/loongarch64/src/tlb/pwch.rs b/crates/loongarch64/src/tlb/pwch.rs new file mode 100644 index 0000000000..eb3d65ca8d --- /dev/null +++ b/crates/loongarch64/src/tlb/pwch.rs @@ -0,0 +1,51 @@ +use super::super::register::csr::Register; +use super::super::register::csr::CSR_PWCH; +use bit_field::BitField; +use core::arch::asm; +pub struct Pwch { + bits: u32, +} +impl Register for Pwch { + fn read() -> Self { + let bits: u32; + // unsafe { asm!("csrrd {},{}",out(reg)bits,const CSR_PWCH) } + unsafe { asm!("csrrd {},0x1d",out(reg)bits) } + Self { bits } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}",in(reg)self.bits,const CSR_PWCH) } + unsafe { asm!("csrwr {},0x1d",in(reg)self.bits) } + } +} +impl Pwch { + //次高一级目录的起始地址 + pub fn get_dir3_base(&self) -> u32 { + self.bits.get_bits(0..=5) + } + pub fn set_dir3_base(&mut self, dir2_base: u32) -> &mut Self { + self.bits.set_bits(0..=5, dir2_base); + self + } + // 次高一级目录的索引位数。0 表示没有这一级。 + pub fn get_dir3_width(&self) -> u32 { + self.bits.get_bits(6..=11) + } + pub fn set_dir3_width(&mut self, dir2_width: u32) -> &mut Self { + self.bits.set_bits(6..=11, dir2_width); + self + } + pub fn get_dir4_base(&self) -> u32 { + self.bits.get_bits(12..=17) + } + pub fn set_dir4_base(&mut self, dir3_base: u32) -> &mut Self { + self.bits.set_bits(12..=17, dir3_base); + self + } + pub fn get_dir4_width(&self) -> u32 { + self.bits.get_bits(18..=23) + } + pub fn set_dir4_width(&mut self, dir3_width: u32) -> &mut Self { + self.bits.set_bits(18..=23, dir3_width); + self + } +} diff --git a/crates/loongarch64/src/tlb/pwcl.rs b/crates/loongarch64/src/tlb/pwcl.rs new file mode 100644 index 0000000000..0b999e38c1 --- /dev/null +++ b/crates/loongarch64/src/tlb/pwcl.rs @@ -0,0 +1,99 @@ +// 该寄存器和 CSR.PWCH 寄存器中的信息在一起定义了操作系统中所采用的页表结构。这些信息将用于指 +// 示软件或硬件进行页表遍历 +// 在 LA32 架构下仅实现 CSR.PWCL。为此 PWCL 寄存器需包含刻画页表结构的所有信息，由此导致末级页 +// 表和最低两级目录的起始地址位置均不超过 32 位，该限制在 LA64 架构下依然存在 + +use super::super::register::csr::Register; +use super::super::register::csr::CSR_PWCL; +use bit_field::BitField; +use core::arch::asm; +pub struct Pwcl { + bits: u32, +} + +impl Register for Pwcl { + fn read() -> Self { + let bits: u32; + // unsafe { asm!("csrrd {},{}",out(reg)bits,const CSR_PWCL) } + unsafe { asm!("csrrd {},0x1c",out(reg)bits) } + Self { bits } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}",in(reg)self.bits,const CSR_PWCL) } + unsafe { asm!("csrwr {},0x1c",in(reg)self.bits) } + } +} +impl Pwcl { + // 末级页表的起始地址。 + pub fn get_ptbase(&self) -> u32 { + self.bits.get_bits(0..=4) + } + pub fn set_ptbase(&mut self, ptbase: u32) -> &mut Self { + self.bits.set_bits(0..=4, ptbase); + self + } + // 末级页表的索引位数 + pub fn get_ptwidth(&self) -> u32 { + self.bits.get_bits(5..=9) + } + pub fn set_ptwidth(&mut self, ptwidth: u32) -> &mut Self { + self.bits.set_bits(5..=9, ptwidth); + self + } + pub fn get_dir1_base(&self) -> u32 { + self.bits.get_bits(10..=14) + } + pub fn set_dir1_base(&mut self, dir1_base: u32) -> &mut Self { + self.bits.set_bits(10..=14, dir1_base); + self + } + // 最低一级目录的索引位数。0 表示没有这一级 + pub fn get_dir1_width(&self) -> u32 { + self.bits.get_bits(15..=19) + } + pub fn set_dir1_width(&mut self, dir1_width: u32) -> &mut Self { + self.bits.set_bits(15..=19, dir1_width); + self + } + pub fn get_dir2_base(&self) -> u32 { + self.bits.get_bits(20..=24) + } + pub fn set_dir2_base(&mut self, dir2_base: u32) -> &mut Self { + self.bits.set_bits(20..=24, dir2_base); + self + } + // 最低两级目录的索引位数。0 表示没有这一级 + pub fn get_dir2_width(&self) -> u32 { + self.bits.get_bits(25..=29) + } + pub fn set_dir2_width(&mut self, dir2_width: u32) -> &mut Self { + self.bits.set_bits(25..=29, dir2_width); + self + } + // 0 表示 64 比特，1 表示 128 比特，2 表示 192 比特，3 表示 256 比特。 + pub fn get_pte_width(&self) -> u32 { + let val = self.bits.get_bits(30..=31); + match val { + 0 => 64, + 1 => 128, + 2 => 192, + 3 => 256, + _ => panic!("invalid pte_width"), + } + } + pub fn set_pte_width(&mut self, pte_width: u32) -> &mut Self { + let val = match pte_width { + 64 => 0, + 128 => 1, + 192 => 2, + 256 => 3, + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3, + _ => panic!("invalid pte_width"), + }; + self.bits.set_bits(30..=31, val); + self + } +} diff --git a/crates/loongarch64/src/tlb/stlbps.rs b/crates/loongarch64/src/tlb/stlbps.rs new file mode 100644 index 0000000000..5825dfe976 --- /dev/null +++ b/crates/loongarch64/src/tlb/stlbps.rs @@ -0,0 +1,32 @@ +// 该寄存器用于配置 STLB 中页的大小 + +use super::super::register::csr::Register; +use super::super::register::csr::CSR_STLBPS; +use bit_field::BitField; +use core::arch::asm; +pub struct StlbPs { + bits: u32, +} + +impl Register for StlbPs { + fn read() -> Self { + let bits: u32; + // unsafe { asm!("csrrd {},{}",out(reg)bits,const CSR_STLBPS) } + unsafe { asm!("csrrd {},0x1e",out(reg)bits) } + Self { bits } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}",in(reg)self.bits,const CSR_STLBPS) } + unsafe { asm!("csrwr {},0x1e",in(reg)self.bits) } + } +} + +impl StlbPs { + pub fn get_page_size(&self) -> u32 { + self.bits.get_bits(0..=5) + } + pub fn set_page_size(&mut self, page_size: u32) -> &mut Self { + self.bits.set_bits(0..=5, page_size); + self + } +} diff --git a/crates/loongarch64/src/tlb/tlbehi.rs b/crates/loongarch64/src/tlb/tlbehi.rs new file mode 100644 index 0000000000..5b81a36a63 --- /dev/null +++ b/crates/loongarch64/src/tlb/tlbehi.rs @@ -0,0 +1,37 @@ +// 该寄存器包含 TLB 指令操作时与 TLB 表项高位部分虚页号相关的信息。因 TLB 表项高位所含的 VPPN 域 +// 的位宽与实现所支持的有效虚地址范围相关，故有关寄存器域的定义分开表述 + +use super::super::register::csr::Register; +use super::super::register::csr::CSR_TLBEHI; +use bit_field::BitField; +use core::arch::asm; + +pub struct TlbEHi { + bits: usize, +} +impl Register for TlbEHi { + fn read() -> Self { + let bits: usize; + // unsafe { asm!("csrrd {},{}",out(reg)bits,const CSR_TLBEHI) } + unsafe { asm!("csrrd {},0x11",out(reg)bits) } + TlbEHi { bits } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}",in(reg)self.bits,const CSR_TLBEHI) } + unsafe { asm!("csrwr {},0x11",in(reg)self.bits) } + } +} +impl TlbEHi { + // 执行 TLBRD 指令时，所读取 TLB 表项的 VPPN 域的值记录到这里。 + // 在 CSR.TLBRERA.IsTLBR=0 时，执行 TLBSRCH 指令时查询 TLB 所用 VPPN 值，以及执行 + // TLBWR 和 TLBFILL 指令时写入 TLB 表项的 VPPN 域的值来自于此。 + // 当触发 load 操作页无效例外、store 操作页无效例外、取指操作页无效例外、页修 + // 改例外、页不可读例外、页不可执行例外和页特权等级不合规例外时，触发例外的地址的[VALEN-1:13]位被记录到这里。 + pub fn get_vppn(&self, valen: usize) -> usize { + self.bits.get_bits(13..valen) + } + pub fn set_vppn(&mut self, valen: usize, vppn: usize) -> &mut Self { + self.bits.set_bits(13..valen, vppn); + self + } +} diff --git a/crates/loongarch64/src/tlb/tlbelo.rs b/crates/loongarch64/src/tlb/tlbelo.rs new file mode 100644 index 0000000000..2a40d6b272 --- /dev/null +++ b/crates/loongarch64/src/tlb/tlbelo.rs @@ -0,0 +1,168 @@ +use super::super::register::csr::CSR_TLBELO; +use super::super::PALEN; +use bit_field::BitField; +use core::arch::asm; +use core::fmt; +// TLBELO0 和 TLBELO1 两个寄存器包含了 TLB 指令操作时 TLB 表项低位部分物理页号等相关的信息。因龙 +// 芯架构下 TLB 采用双页结构，所以 TLB 表项的低位信息对应奇偶两个物理页表项，其中偶数页信息在 TLBELO0 +// 中，奇数页信息在 TLBELO1 中。 +pub trait TLBEL { + fn get_valid(&self) -> bool; + fn set_valid(&mut self, valid: bool) -> &mut Self; + fn get_dirty(&self) -> bool; + fn set_dirty(&mut self, dirty: bool) -> &mut Self; + fn get_plv(&self) -> usize; + fn set_plv(&mut self, plv: usize) -> &mut Self; + fn get_mem_access_type(&self) -> usize; + fn set_mem_access_type(&mut self, mem_access_type: usize) -> &mut Self; + fn get_global_flag(&self) -> bool; + fn set_global_flag(&mut self, global_flag: bool) -> &mut Self; + fn get_ppn(&self, paleln: usize) -> usize; + fn set_ppn(&mut self, palen: usize, ppn: usize) -> &mut Self; + fn get_not_readable(&self) -> bool; + fn set_not_readable(&mut self, not_readable: bool) -> &mut Self; + fn get_not_executable(&self) -> bool; + fn set_not_executable(&mut self, not_executable: bool) -> &mut Self; + fn get_rplv(&self) -> bool; + fn set_rplv(&mut self, rplv: bool) -> &mut Self; +} +pub struct TLBELO { + bits: usize, + index: usize, +} + +impl fmt::Debug for TLBELO { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!( + f, + "TlbElo{}: RPLV:{},NX:{},NR:{},PPN:{:#x},G:{},MAT:{},PLV:{},D:{},V:{}", + self.index, + self.get_rplv(), + self.get_not_executable(), + self.get_not_readable(), + self.get_ppn(PALEN), + self.get_global_flag(), + self.get_mem_access_type(), + self.get_plv(), + self.get_dirty(), + self.get_valid() + ) + } +} + +impl TLBELO { + pub fn read(index: usize) -> Self { + let bits: usize; + unsafe { + match index { + // 0 => asm!("csrrd {},{}",out(reg)bits,const CSR_TLBELO), + // 1 => asm!("csrrd {},{}",out(reg)bits,const CSR_TLBELO+1), + 0 => asm!("csrrd {},0x12",out(reg)bits), + 1 => asm!("csrrd {},0x13",out(reg)bits), + _ => panic!("TLBELO index out of range"), + } + } + Self { bits, index } + } + pub fn write(&mut self) { + unsafe { + match self.index { + // 0 => asm!("csrwr {},{}",in(reg)self.bits,const CSR_TLBELO), + // 1 => asm!("csrwr {},{}",in(reg)self.bits,const CSR_TLBELO+1), + 0 => asm!("csrwr {},0x12",in(reg)self.bits), + 1 => asm!("csrwr {},0x13",in(reg)self.bits), + _ => panic!("TLBELO index out of range"), + } + } + } +} + +impl TLBELO { + pub fn set_val(&mut self, val: usize) -> &mut Self { + self.bits = val; + self + } +} +impl TLBEL for TLBELO { + // 页表项的有效位（V） + fn get_valid(&self) -> bool { + self.bits.get_bit(0) + } + + fn set_valid(&mut self, valid: bool) -> &mut Self { + self.bits.set_bit(0, valid); + self + } + + fn get_dirty(&self) -> bool { + self.bits.get_bit(1) + } + + fn set_dirty(&mut self, dirty: bool) -> &mut Self { + self.bits.set_bit(1, dirty); + self + } + + fn get_plv(&self) -> usize { + self.bits.get_bits(2..=3) + } + + fn set_plv(&mut self, plv: usize) -> &mut Self { + self.bits.set_bits(2..=3, plv); + self + } + + fn get_mem_access_type(&self) -> usize { + self.bits.get_bits(4..=5) + } + + fn set_mem_access_type(&mut self, mem_access_type: usize) -> &mut Self { + self.bits.set_bits(4..=5, mem_access_type); + self + } + + fn get_global_flag(&self) -> bool { + self.bits.get_bit(6) + } + + fn set_global_flag(&mut self, global_flag: bool) -> &mut Self { + self.bits.set_bit(6, global_flag); + self + } + + fn get_ppn(&self, palen: usize) -> usize { + self.bits.get_bits(12..palen) + } + + fn set_ppn(&mut self, palen: usize, ppn: usize) -> &mut Self { + self.bits.set_bits(12..palen, ppn); + self + } + + fn get_not_readable(&self) -> bool { + self.bits.get_bit(61) + } + + fn set_not_readable(&mut self, not_readable: bool) -> &mut Self { + self.bits.set_bit(61, not_readable); + self + } + + fn get_not_executable(&self) -> bool { + self.bits.get_bit(62) + } + + fn set_not_executable(&mut self, not_executable: bool) -> &mut Self { + self.bits.set_bit(62, not_executable); + self + } + + fn get_rplv(&self) -> bool { + self.bits.get_bit(63) + } + + fn set_rplv(&mut self, rplv: bool) -> &mut Self { + self.bits.set_bit(63, rplv); + self + } +} diff --git a/crates/loongarch64/src/tlb/tlbentry.rs b/crates/loongarch64/src/tlb/tlbentry.rs new file mode 100644 index 0000000000..2c9130abc8 --- /dev/null +++ b/crates/loongarch64/src/tlb/tlbentry.rs @@ -0,0 +1,37 @@ +use super::super::register::csr::Register; +use super::super::register::csr::CSR_TLBRENTRY; +use core::arch::asm; + +// TLB重填例外入口地址 +pub struct TLBREntry { + bits: usize, +} + +impl Register for TLBREntry { + fn read() -> Self { + let bits: usize; + unsafe { + // asm!("csrrd {},{}", out(reg) bits,const CSR_TLBRENTRY); + asm!("csrrd {},0x88", out(reg) bits); + } + TLBREntry { bits } + } + fn write(&mut self) { + unsafe { + // asm!("csrwr {},{}", in(reg) self.bits,const CSR_TLBRENTRY); + asm!("csrwr {},0x88", in(reg) self.bits); + } + } +} + +impl TLBREntry { + pub fn get_val(&self) -> usize { + self.bits + } + pub fn set_val(&mut self, val: usize) -> &mut Self { + // 对齐到4kb + assert!(val & 0xFFF == 0); + self.bits = val; + self + } +} diff --git a/crates/loongarch64/src/tlb/tlbidx.rs b/crates/loongarch64/src/tlb/tlbidx.rs new file mode 100644 index 0000000000..30f2d61032 --- /dev/null +++ b/crates/loongarch64/src/tlb/tlbidx.rs @@ -0,0 +1,58 @@ +// 该寄存器包含 TLB 指令操作 TLB 时相关的索引值等信息。Index 域的位宽与实现相关，不 +// 过本架构所允许的 Index 位宽不超过 16 比特。 +// 该寄存器还包含 TLB 指令操作时与 TLB 表项中 PS、E 域相关的信息 + +use super::super::register::csr::Register; +use super::super::register::csr::CSR_TLBIDX; +use bit_field::BitField; +use core::arch::asm; +pub struct TlbIdx { + bits: u32, +} +impl Register for TlbIdx { + fn read() -> Self { + let bits: u32; + // unsafe { asm!("csrrd {},{}",out(reg)bits,const CSR_TLBIDX) } + unsafe { asm!("csrrd {},0x10",out(reg)bits) } + Self { bits } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}",in(reg)self.bits,const CSR_TLBIDX) } + unsafe { asm!("csrwr {},0x10",in(reg)self.bits) } + } +} +impl TlbIdx { + // 执行 TLBRD 和 TLBWR 指令时，访问 TLB 表项的索引值来自于此。 + // 执行 TLBSRCH 指令时，如果命中，则命中项的索引值记录到这里 + pub fn get_index(&self) -> u32 { + self.bits.get_bits(0..16) + } + pub fn set_index(&mut self, index: u32) -> &mut Self { + self.bits.set_bits(0..16, index); + self + } + // 执行 TLBRD 指令时，所读取 TLB 表项的 PS 域的值记录到这里。 + // 在 CSR.TLBRERA.IsTLBR=0 时，执行 TLBWR 和 TLBFILL 指令，写入的 TLB 表项的 PS + // 域的值来自于此。 + pub fn get_ps(&self) -> u32 { + self.bits.get_bits(24..=29) + } + pub fn set_ps(&mut self, ps: u32) -> &mut Self { + self.bits.set_bits(24..=29, ps); + self + } + // 该位为 1 表示该 TLB 表项为空（无效 TLB 表项），为 0 表示该 TLB 表项非空（有效 TLB + // 表项）。 + // 执行 TLBSRCH 时，如果有命中项该位记为 0，否则该位记为 1。 + // 执行 TLBRD 时，所读取 TLB 表项的 E 位信息取反后记录到这里。 + // 执行 TLBWR 或 TLBFILL 指令时，若 CSR.TLBRERA.IsTLBR=0，将该位的值取反后写入 + // 到被写 TLB 项的 E 位；若此时 CSR.TLBRERA.IsTLBR=1，那么被写入的 TLB 项的 E 位 + // 总是置为 1，与该位的值无关 + pub fn get_ne(&self) -> bool { + self.bits.get_bit(31) + } + pub fn set_ne(&mut self, ne: bool) -> &mut Self { + self.bits.set_bit(31, ne); + self + } +} diff --git a/crates/loongarch64/src/tlb/tlbrbadv.rs b/crates/loongarch64/src/tlb/tlbrbadv.rs new file mode 100644 index 0000000000..6f3947e0f8 --- /dev/null +++ b/crates/loongarch64/src/tlb/tlbrbadv.rs @@ -0,0 +1,30 @@ +use super::super::register::csr::Register; +use super::super::register::csr::CSR_TLBRBADV; +use core::arch::asm; +// 该寄存器用于记录触发 TLB 重填例外的出错虚地址 +pub struct TlbRBadv { + bits: usize, +} + +impl Register for TlbRBadv { + fn read() -> Self { + let mut bits; + // unsafe { asm!("csrrd {},{}", out(reg) bits,const CSR_TLBRBADV ) } + unsafe { asm!("csrrd {},0x89", out(reg) bits ) } + Self { bits } + } + fn write(&mut self) { + // unsafe { asm!("csrwr {},{}",in(reg) self.bits, const CSR_TLBRBADV) } + unsafe { asm!("csrwr {},0x89",in(reg) self.bits) } + } +} + +impl TlbRBadv { + pub fn get_val(&self) -> usize { + self.bits + } + pub fn set_val(&mut self, value: usize) -> &mut Self { + self.bits = value; + self + } +} diff --git a/crates/loongarch64/src/tlb/tlbrehi.rs b/crates/loongarch64/src/tlb/tlbrehi.rs new file mode 100644 index 0000000000..0130d47b2a --- /dev/null +++ b/crates/loongarch64/src/tlb/tlbrehi.rs @@ -0,0 +1,46 @@ +// 无论 CSR.TLBRERA.IsTLBR 等于何值，执行 TLBRD 指令都只更新 TLBEHI 寄存器 + +use super::super::register::csr::Register; +use super::super::register::csr::CSR_TLBREHI; +use bit_field::BitField; +use core::arch::asm; + +pub struct TlbREhi { + bits: u64, +} + +impl Register for TlbREhi { + fn read() -> Self { + let bits: u64; + unsafe { + // asm!("csrrd {},{}",out(reg)bits,const CSR_TLBREHI); + asm!("csrrd {},0x8E",out(reg)bits); + } + Self { bits } + } + fn write(&mut self) { + unsafe { + // asm!("csrwr {},{}",in(reg)self.bits,const CSR_TLBREHI); + asm!("csrwr {},0x8E",in(reg)self.bits); + } + } +} + +impl TlbREhi { + // TLB 重填例外专用的页大小值。即在 CSR.TLBRERA.IsTLBR=1 时，执行 TLBWR 和 TLBFILL + // 指令，写入的 TLB 表项的 PS 域的值来自于此。 + pub fn get_page_size(&self) -> u64 { + self.bits.get_bits(0..=5) + } + pub fn set_page_size(&mut self, page_size: u64) -> &mut Self { + self.bits.set_bits(0..=5, page_size); + self + } + pub fn get_vppn(&self, valen: usize) -> u64 { + self.bits.get_bits(13..valen) + } + pub fn set_vppn(&mut self, valen: usize, vppn: u64) -> &mut Self { + self.bits.set_bits(13..valen, vppn); + self + } +} diff --git a/crates/loongarch64/src/tlb/tlbrelo.rs b/crates/loongarch64/src/tlb/tlbrelo.rs new file mode 100644 index 0000000000..4f6def4857 --- /dev/null +++ b/crates/loongarch64/src/tlb/tlbrelo.rs @@ -0,0 +1,154 @@ +// TLBRELO0/1 两寄存器是处于 TLB 重填例外上下文时（此时 CSR.TLBRERA.IsTLBR=1），存放 TLB 指令操 +// 作时 TLB 表项低位部分物理页号等相关的信息。TLBRELO0/1 两寄存器的格式及各个域的含义分别与 +// TLBELO0/1 两寄存器一样 +// 无论 CSR.TLBRERA.IsTLBR 等于何值，执行 TLBRD 指令都只更新 TLBELO0/1 两寄存器。 +// 无论 CSR.TLBRERA.IsTLBR 等于何值，执行 LDPTE 指令都只更新 TLBRELO0/1 两寄存器 + +use super::super::register::csr::CSR_TLBRELO; +use super::super::PALEN; +use super::tlbelo::TLBEL; +use bit_field::BitField; +use core::arch::asm; +use core::fmt; +pub struct TlbRelo { + bits: usize, + index: usize, +} + +impl fmt::Debug for TlbRelo { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!( + f, + "TlbRelo{}: RPLV:{},NX:{},NR:{},PPN:{:#x},G:{},MAT:{},PLV:{},D:{},V:{}", + self.index, + self.get_rplv(), + self.get_not_executable(), + self.get_not_readable(), + self.get_ppn(PALEN), + self.get_global_flag(), + self.get_mem_access_type(), + self.get_plv(), + self.get_dirty(), + self.get_valid() + ) + } +} +impl TlbRelo { + pub fn read(index: usize) -> Self { + let bits: usize; + unsafe { + match index { + // 0 => asm!("csrrd {},{}",out(reg)bits,const CSR_TLBRELO), + // 1 => asm!("csrrd {},{}",out(reg)bits,const CSR_TLBRELO+1), + 0 => asm!("csrrd {},0x8C",out(reg)bits), + 1 => asm!("csrrd {},0x8D",out(reg)bits), + _ => panic!("TLBELO index out of range"), + } + } + Self { bits, index } + } + pub fn write(&mut self) { + unsafe { + match self.index { + // 0 => asm!("csrwr {},{}",in(reg)self.bits,const CSR_TLBRELO), + // 1 => asm!("csrwr {},{}",in(reg)self.bits,const CSR_TLBRELO+1), + 0 => asm!("csrwr {},0x8C",in(reg)self.bits), + 1 => asm!("csrwr {},0x8D",in(reg)self.bits), + _ => panic!("TLBELO index out of range"), + } + } + } +} +impl TLBEL for TlbRelo { + // 页表项的有效位（V） + fn get_valid(&self) -> bool { + self.bits.get_bit(0) + } + + fn set_valid(&mut self, valid: bool) -> &mut Self { + self.bits.set_bit(0, valid); + self + } + + fn get_dirty(&self) -> bool { + self.bits.get_bit(1) + } + + fn set_dirty(&mut self, dirty: bool) -> &mut Self { + self.bits.set_bit(1, dirty); + self + } + + fn get_plv(&self) -> usize { + self.bits.get_bits(2..=3) + } + + fn set_plv(&mut self, plv: usize) -> &mut Self { + self.bits.set_bits(2..=3, plv); + self + } + + fn get_mem_access_type(&self) -> usize { + self.bits.get_bits(4..=5) + } + + fn set_mem_access_type(&mut self, mem_access_type: usize) -> &mut Self { + self.bits.set_bits(4..=5, mem_access_type); + self + } + + fn get_global_flag(&self) -> bool { + self.bits.get_bit(6) + } + + fn set_global_flag(&mut self, global_flag: bool) -> &mut Self { + self.bits.set_bit(6, global_flag); + self + } + + fn get_ppn(&self, palen: usize) -> usize { + self.bits.get_bits(12..palen) + } + + fn set_ppn(&mut self, palen: usize, ppn: usize) -> &mut Self { + self.bits.set_bits(12..palen, ppn); + self + } + + fn get_not_readable(&self) -> bool { + self.bits.get_bit(61) + } + + fn set_not_readable(&mut self, not_readable: bool) -> &mut Self { + self.bits.set_bit(61, not_readable); + self + } + + fn get_not_executable(&self) -> bool { + self.bits.get_bit(62) + } + + fn set_not_executable(&mut self, not_executable: bool) -> &mut Self { + self.bits.set_bit(62, not_executable); + self + } + + fn get_rplv(&self) -> bool { + self.bits.get_bit(63) + } + + fn set_rplv(&mut self, rplv: bool) -> &mut Self { + self.bits.set_bit(63, rplv); + self + } +} + +impl TlbRelo { + pub fn get_val(&self) -> usize { + self.bits + } + pub fn set_val(&mut self, val: usize) -> &mut Self { + self.bits = val; + self + } +} diff --git a/crates/loongarch64/src/tlb/tlbrera.rs b/crates/loongarch64/src/tlb/tlbrera.rs new file mode 100644 index 0000000000..2b12a0b448 --- /dev/null +++ b/crates/loongarch64/src/tlb/tlbrera.rs @@ -0,0 +1,46 @@ +// 该寄存器保存 TLB 重填例外处理完毕之后的返回地址。除此之外，该寄存器还包含用于标识当前例外 +// 是 TLB 重填例外的标志位 + +use super::super::register::csr::Register; +use super::super::register::csr::CSR_TLBRERA; +use bit_field::BitField; +use core::arch::asm; +pub struct TLBREra { + bits: usize, +} + +impl Register for TLBREra { + fn read() -> Self { + let mut bits; + unsafe { + // asm!("csrrd {},{}", out(reg) bits,const CSR_TLBRERA); + asm!("csrrd {},0x8A", out(reg) bits); + } + TLBREra { bits } + } + fn write(&mut self) { + //写入era的内容 + unsafe { + // asm!("csrwr {},{}", in(reg) self.bits,const CSR_TLBRERA); + asm!("csrwr {},0x8A", in(reg) self.bits); + } + } +} + +impl TLBREra { + // 记录触发 TLB 重填例外的指令的 PC 的[GRLEN-1:2]位。当执行 ERTN 指令从 TLB 重填 + // 例外处理程序返回时（此时本寄存器 IsTLBR=1 且 CSR.ERRCTL.IsMERR=0），硬件自动 + // 将存放在此处的值最低位补上两比特 0 后作为最终的返回地址 + pub fn get_pc(&self) -> usize { + // 返回pc + self.bits.get_bits(2..) + } + pub fn get_is_tlbr(&self) -> bool { + // 返回是否是 TLB 重填例外 + self.bits.get_bit(0) + } + pub fn set_is_tlbr(&mut self, is_tlbr: bool) -> &mut Self { + self.bits.set_bit(0, is_tlbr); + self + } +} diff --git a/crates/loongarch64/src/tlb/tlbrprmd.rs b/crates/loongarch64/src/tlb/tlbrprmd.rs new file mode 100644 index 0000000000..d54ef6c528 --- /dev/null +++ b/crates/loongarch64/src/tlb/tlbrprmd.rs @@ -0,0 +1,59 @@ +// 当触发 TLB 重填例外时，硬件会将此时处理器核的特权等级、客户机模式、全局中断使能和监视点使 +// 能位保存至该寄存器中，用于例外返回时恢复处理器核的现场 + +use super::super::cpu::CpuMode; +use super::super::register::csr::Register; +use super::super::register::csr::CSR_TLBRPRMD; +use bit_field::BitField; +use core::arch::asm; +pub struct TlbRPrmd { + bits: u32, +} + +impl Register for TlbRPrmd { + fn read() -> Self { + let bits: u32; + unsafe { + // asm!("csrrd {},{}", out(reg) bits,const CSR_TLBRPRMD); + asm!("csrrd {},0x8f", out(reg) bits); + } + Self { bits } + } + fn write(&mut self) { + //写入era的内容 + unsafe { + // asm!("csrwr {},{}", in(reg) self.bits,const CSR_TLBRPRMD); + asm!("csrwr {},0x8f", in(reg) self.bits); + } + } +} + +impl TlbRPrmd { + pub fn get_pplv(&self) -> u32 { + self.bits.get_bits(0..2) + } + pub fn set_pplv(&mut self, pplv: CpuMode) -> &mut Self { + //设置特权级 + // 用于在进入用户程序时设置特权级 + self.bits.set_bits(0..2, pplv as u32); + self + } + // 记录例外发生前的crmd.ie + pub fn get_pie(&self) -> bool { + self.bits.get_bit(2) + } + // 设置中断使能 + // 用于在进入用户程序时设置中断使能 + pub fn set_pie(&mut self, pie: bool) -> &mut Self { + self.bits.set_bit(2, pie); + self + } + + pub fn get_pwe(&self) -> bool { + self.bits.get_bit(4) + } + pub fn set_pwe(&mut self, pwe: bool) -> &mut Self { + self.bits.set_bit(4, pwe); + self + } +} diff --git a/crates/loongarch64/src/tlb/tlbrsave.rs b/crates/loongarch64/src/tlb/tlbrsave.rs new file mode 100644 index 0000000000..8b13789179 --- /dev/null +++ b/crates/loongarch64/src/tlb/tlbrsave.rs @@ -0,0 +1 @@ + diff --git a/crates/percpu/src/imp.rs b/crates/percpu/src/imp.rs index 322867b717..99ca47d976 100644 --- a/crates/percpu/src/imp.rs +++ b/crates/percpu/src/imp.rs @@ -74,6 +74,8 @@ pub fn get_local_thread_pointer() -> usize { core::arch::asm!("mv {}, gp", out(reg) tp) } else if #[cfg(target_arch = "aarch64")] { core::arch::asm!("mrs {}, TPIDR_EL1", out(reg) tp) + }else if #[cfg(target_arch = "loongarch64")] { + core::arch::asm!("move {}, $tp", out(reg) tp) } } } @@ -108,6 +110,8 @@ pub fn set_local_thread_pointer(cpu_id: usize) { core::arch::asm!("mv gp, {}", in(reg) tp) } else if #[cfg(target_arch = "aarch64")] { core::arch::asm!("msr TPIDR_EL1, {}", in(reg) tp) + }else if #[cfg(target_arch = "loongarch64")] { + core::arch::asm!("move $tp, {}", in(reg) tp) } } } diff --git a/crates/percpu_macros/src/arch.rs b/crates/percpu_macros/src/arch.rs index 6d77eb6812..33c512bb82 100644 --- a/crates/percpu_macros/src/arch.rs +++ b/crates/percpu_macros/src/arch.rs @@ -33,6 +33,12 @@ pub fn gen_offset(symbol: &Ident) -> proc_macro2::TokenStream { out(reg) value, VAR = sym #symbol, ); + #[cfg(any(target_arch = "loongarch64"))] + ::core::arch::asm!( + "la.abs {0}, {VAR}", + out(reg) value, + VAR = sym #symbol, + ); } value } @@ -58,6 +64,8 @@ pub fn gen_current_ptr(symbol: &Ident, ty: &Type) -> proc_macro2::TokenStream { ::core::arch::asm!("mrs {}, TPIDR_EL1", out(reg) base); #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] ::core::arch::asm!("mv {}, gp", out(reg) base); + #[cfg(any(target_arch = "loongarch64"))] + ::core::arch::asm!("move {}, $tp", out(reg) base); (base + self.offset()) as *const #ty } }) diff --git a/modules/axhal/Cargo.toml b/modules/axhal/Cargo.toml index f29ecde07d..bf8c148d33 100644 --- a/modules/axhal/Cargo.toml +++ b/modules/axhal/Cargo.toml @@ -54,5 +54,9 @@ arm_gic = { path = "../../crates/arm_gic" } arm_pl011 = { path = "../../crates/arm_pl011" } dw_apb_uart = { path = "../../crates/dw_apb_uart" } +[target.'cfg(target_arch = "loongarch64")'.dependencies] +bit_field = "0.10.1" +loongarch64 = { path = "../../crates/loongarch64" } + [build-dependencies] axconfig = { path = "../axconfig" } diff --git a/modules/axhal/linker.lds.S b/modules/axhal/linker.lds.S index 73b7a7884d..97bb9fb0fc 100644 --- a/modules/axhal/linker.lds.S +++ b/modules/axhal/linker.lds.S @@ -64,7 +64,7 @@ SECTIONS . = ALIGN(4K); _edata = .; - .bss : ALIGN(4K) { + .bss : AT(.) ALIGN(4K) { boot_stack = .; *(.bss.stack) . = ALIGN(4K); diff --git a/modules/axhal/src/arch/loongarch64/context.rs b/modules/axhal/src/arch/loongarch64/context.rs new file mode 100644 index 0000000000..d3ee92d24a --- /dev/null +++ b/modules/axhal/src/arch/loongarch64/context.rs @@ -0,0 +1,106 @@ +use core::arch::asm; +use memory_addr::VirtAddr; + +/// Saved registers when a trap (interrupt or exception) occurs. +#[repr(C)] +#[derive(Debug, Default, Clone)] +pub struct TrapFrame { + /// All general registers. + pub regs: [usize; 32], + /// Current Mode Information + pub crmd: usize, + /// Pre-exception Mode Information + pub prmd: usize, + /// Extended Component Unit Enable + pub euen: usize, + /// Exception Configuration + pub ecfg: usize, + /// Exception Status + pub estat: usize, + /// Exception Return Address + pub era: usize, + /// Bad Virtual Address + pub badv: usize, +} + +/// Saved hardware states of a task. +/// +/// The context usually includes: +/// +/// - Callee-saved registers +/// - Stack pointer register +/// - Thread pointer register (for thread-local storage, currently unsupported) +/// - FP/SIMD registers +/// +/// On context switch, current task saves its context from CPU to memory, +/// and the next task restores its context from memory to CPU. +#[allow(missing_docs)] +#[repr(C)] +#[derive(Debug, Default)] +pub struct TaskContext { + pub ra: usize, // return address + pub sp: usize, // stack pointer + pub s: [usize; 10], // loongArch need to save 10 static registers from $r22 to $r31 +} + +impl TaskContext { + /// Creates a new default context for a new task. + pub const fn new() -> Self { + unsafe { core::mem::MaybeUninit::zeroed().assume_init() } + } + + /// Initializes the context for a new task, with the given entry point and + /// kernel stack. + pub fn init(&mut self, entry: usize, kstack_top: VirtAddr) { + self.sp = kstack_top.as_usize(); + self.ra = entry; + } + + /// Switches to another task. + /// + /// It first saves the current task's context from CPU to this place, and then + /// restores the next task's context from `next_ctx` to CPU. + pub fn switch_to(&mut self, next_ctx: &Self) { + unsafe { + // TODO: switch TLS + context_switch(self, next_ctx) + } + } +} + +#[naked] +unsafe extern "C" fn context_switch(_current_task: &mut TaskContext, _next_task: &TaskContext) { + asm!( + " + // save old context (callee-saved registers) + st.d $ra, $a0, 0 + st.d $sp, $a0, 1 * 8 + st.d $s0, $a0, 2 * 8 + st.d $s1, $a0, 3 * 8 + st.d $s2, $a0, 4 * 8 + st.d $s3, $a0, 5 * 8 + st.d $s4, $a0, 6 * 8 + st.d $s5, $a0, 7 * 8 + st.d $s6, $a0, 8 * 8 + st.d $s7, $a0, 9 * 8 + st.d $s8, $a0, 10 * 8 + st.d $fp, $a0, 11 * 8 + + // restore new context + ld.d $ra, $a1, 0 + ld.d $s0, $a1, 2 * 8 + ld.d $s1, $a1, 3 * 8 + ld.d $s2, $a1, 4 * 8 + ld.d $s3, $a1, 5 * 8 + ld.d $s4, $a1, 6 * 8 + ld.d $s5, $a1, 7 * 8 + ld.d $s6, $a1, 8 * 8 + ld.d $s7, $a1, 9 * 8 + ld.d $s8, $a1, 10 * 8 + ld.d $fp, $a1, 11 * 8 + ld.d $sp, $a1, 1 * 8 + + jr $ra", + options(noreturn), + ) +} diff --git a/modules/axhal/src/arch/loongarch64/mod.rs b/modules/axhal/src/arch/loongarch64/mod.rs new file mode 100644 index 0000000000..f6147379b7 --- /dev/null +++ b/modules/axhal/src/arch/loongarch64/mod.rs @@ -0,0 +1,117 @@ +#[macro_use] +//mod macros; + +mod context; +mod trap; + +use bit_field::BitField; +use core::arch::asm; +use loongarch64::register::{crmd::Crmd, csr::Register, eentry::Eentry}; + +use loongarch64::tlb::{Pgd, Pgdl, StlbPs, TLBREntry, TlbREhi}; +use memory_addr::{PhysAddr, VirtAddr}; + +pub use self::context::{TaskContext, TrapFrame}; + +/// Allows the current CPU to respond to interrupts. +#[inline] +pub fn enable_irqs() { + Crmd::read().set_ie(true).write() +} + +/// Makes the current CPU to ignore interrupts. +#[inline] +pub fn disable_irqs() { + Crmd::read().set_ie(false).write() +} + +/// Returns whether the current CPU is allowed to respond to interrupts. +#[inline] +pub fn irqs_enabled() -> bool { + Crmd::read().get_ie() +} + +/// Relaxes the current CPU and waits for interrupts. +/// +/// It must be called with interrupts enabled, otherwise it will never return. +#[inline] +pub fn wait_for_irqs() { + unsafe { loongarch64::asm::idle() } +} + +/// Halt the current CPU. +#[inline] +pub fn halt() { + unsafe { loongarch64::asm::idle() } // should never return + disable_irqs(); +} + +/// Reads the register that stores the current page table root. +/// +/// Returns the physical address of the page table root. +#[inline] +pub fn read_page_table_root() -> PhysAddr { + PhysAddr::from(Pgd::read().pgd) +} + +/// Writes the register to update the current page table root. +/// +/// # Safety +/// +/// This function is unsafe as it changes the virtual memory address space. +pub unsafe fn write_page_table_root(root_paddr: PhysAddr) { + let old_root = read_page_table_root(); + trace!("set page table root: {:#x} => {:#x}", old_root, root_paddr); + if old_root != root_paddr { + Pgdl::read().set_val(root_paddr.into()).write(); //设置新的页基址 + // Pgdh::read().set_val(root_paddr.into()).write(); //设置新的页基址 + } +} + +/// Flushes the TLB. +/// +/// If `vaddr` is [`None`], flushes the entire TLB. Otherwise, flushes the TLB +/// entry that maps the given virtual address. +#[inline] +pub fn flush_tlb(_vaddr: Option) { + unsafe { + /* + if let Some(vaddr) = vaddr { + asm!("invtlb 0x6,$r0,{}", in(reg) vaddr.as_usize()); + } else { + asm!("invtlb 0,$r0,$r0"); + }*/ + asm!("tlbflush"); + } +} + +/// Writes Exception Entry Base Address Register (`eentry`). +#[inline] +pub fn set_trap_vector_base(eentry: usize) { + // TODO!(记录状态并恢复) + Crmd::read().set_ie(false).write(); //关闭全局中断 + Eentry::read().set_eentry(eentry).write(); //设置例外入口 + Crmd::read().set_ie(true).write(); //开启全局中断 +} + +core::arch::global_asm!(include_str!("tlb.S")); + +extern "C" { + fn tlb_refill_handler(); +} + +/// Writes TLB Refill Exception Entry Base Address (`tlbrentry`). +#[inline] +pub fn init_tlb() { + StlbPs::read().set_page_size(0xc).write(); //设置TLB的页面大小为4KiB + TlbREhi::read().set_page_size(0xc).write(); //设置TLB的页面大小为4KiB + set_tlb_handler(tlb_refill_handler as usize); +} + +/// Writes TLB Refill Exception Entry Base Address (`tlbrentry`). +#[inline] +pub fn set_tlb_handler(tlb_refill_entry: usize) { + TLBREntry::read() + .set_val((tlb_refill_entry).get_bits(0..32)) + .write(); +} diff --git a/modules/axhal/src/arch/loongarch64/tlb.S b/modules/axhal/src/arch/loongarch64/tlb.S new file mode 100644 index 0000000000..c09f8382d5 --- /dev/null +++ b/modules/axhal/src/arch/loongarch64/tlb.S @@ -0,0 +1,105 @@ +#define INVTLB_ADDR_GFALSE_AND_ASID 5 +#define PAGE_SHIFT 12 +#define PTRS_PER_PGD_BITS (PAGE_SHIFT - 3) +#define PTRS_PER_PUD_BITS (PAGE_SHIFT - 3) +#define PTRS_PER_PMD_BITS (PAGE_SHIFT - 3) +#define PTRS_PER_PTE_BITS (PAGE_SHIFT - 3) + +/* Page table bits */ +#define _PAGE_VALID_SHIFT 0 +#define _PAGE_ACCESSED_SHIFT 0 /* Reuse Valid for Accessed */ +#define _PAGE_DIRTY_SHIFT 1 +#define _PAGE_PLV_SHIFT 2 /* 2~3, two bits */ +#define _CACHE_SHIFT 4 /* 4~5, two bits */ +#define _PAGE_GLOBAL_SHIFT 6 +#define _PAGE_HUGE_SHIFT 6 /* HUGE is a PMD bit */ +#define _PAGE_PRESENT_SHIFT 7 +#define _PAGE_WRITE_SHIFT 8 +#define _PAGE_MODIFIED_SHIFT 9 +#define _PAGE_PROTNONE_SHIFT 10 +#define _PAGE_SPECIAL_SHIFT 11 +#define _PAGE_HGLOBAL_SHIFT 12 /* HGlobal is a PMD bit */ +#define _PAGE_PFN_SHIFT 12 +#define _PAGE_SWP_EXCLUSIVE_SHIFT 23 +#define _PAGE_PFN_END_SHIFT 48 +#define _PAGE_NO_READ_SHIFT 61 +#define _PAGE_NO_EXEC_SHIFT 62 +#define _PAGE_RPLV_SHIFT 63 + +/* Used by software */ +#define _PAGE_PRESENT (_ULCAST_(1) << _PAGE_PRESENT_SHIFT) +#define _PAGE_WRITE (_ULCAST_(1) << _PAGE_WRITE_SHIFT) +#define _PAGE_ACCESSED (_ULCAST_(1) << _PAGE_ACCESSED_SHIFT) +#define _PAGE_MODIFIED (_ULCAST_(1) << _PAGE_MODIFIED_SHIFT) +#define _PAGE_PROTNONE (_ULCAST_(1) << _PAGE_PROTNONE_SHIFT) +#define _PAGE_SPECIAL (_ULCAST_(1) << _PAGE_SPECIAL_SHIFT) + +/* We borrow bit 23 to store the exclusive marker in swap PTEs. */ +#define _PAGE_SWP_EXCLUSIVE (_ULCAST_(1) << _PAGE_SWP_EXCLUSIVE_SHIFT) + +/* Used by TLB hardware (placed in EntryLo*) */ +#define _PAGE_VALID (_ULCAST_(1) << _PAGE_VALID_SHIFT) +#define _PAGE_DIRTY (_ULCAST_(1) << _PAGE_DIRTY_SHIFT) +#define _PAGE_PLV (_ULCAST_(3) << _PAGE_PLV_SHIFT) +#define _PAGE_GLOBAL (_ULCAST_(1) << _PAGE_GLOBAL_SHIFT) +#define _PAGE_HUGE (_ULCAST_(1) << _PAGE_HUGE_SHIFT) +#define _PAGE_HGLOBAL (_ULCAST_(1) << _PAGE_HGLOBAL_SHIFT) +#define _PAGE_NO_READ (_ULCAST_(1) << _PAGE_NO_READ_SHIFT) +#define _PAGE_NO_EXEC (_ULCAST_(1) << _PAGE_NO_EXEC_SHIFT) +#define _PAGE_RPLV (_ULCAST_(1) << _PAGE_RPLV_SHIFT) +#define _CACHE_MASK (_ULCAST_(3) << _CACHE_SHIFT) +#define _PFN_SHIFT (PAGE_SHIFT - 12 + _PAGE_PFN_SHIFT) + +#define _PAGE_USER (PLV_USER << _PAGE_PLV_SHIFT) +#define _PAGE_KERN (PLV_KERN << _PAGE_PLV_SHIFT) + +/* +.macro tlb_do_page_fault, write + SAVE_REGS + + csrrd $a2, 0x7 + move $a0, $sp + st.d $a2, $sp, 8*38 + li.d $a1, \write + bl do_page_fault + + LOAD_REGS + + ertn +.endm +*/ + +.macro LOAD_PTE + csrrd $t0, 0x1B // pgd + //lddir $t0, $t0, 4 + //bstrpick.d $t0, $t0, 63, 12 + //slli.d $t0, $t0, 12 + lddir $t0, $t0, 3 + bstrpick.d $t0, $t0, 63, 12 + slli.d $t0, $t0, 12 + lddir $t0, $t0, 2 + bstrpick.d $t0, $t0, 63, 12 + slli.d $t0, $t0, 12 + lddir $t0, $t0, 1 + bstrpick.d $t0, $t0, 63, 12 + slli.d $t0, $t0, 12 + ldpte $t0, 0 #取回偶数号页表项 + csrrd $t1, 0x8c // tlbrelo0, used to debug + ldpte $t0, 1 #取回奇数号页表项 + csrrd $t1, 0x8d // tlbrelo1, used to debug +.endm + +.section .text.tlbrefill +.balign 4096 +.global tlb_refill_handler +tlb_refill_handler: + csrwr $t0, 0x8B // tlbrsave + csrwr $t1, 0x30 // save + + LOAD_PTE + + tlbfill + csrrd $t0, 0x8B // tlbrsave + csrrd $t1, 0x30 // save + + ertn diff --git a/modules/axhal/src/arch/loongarch64/trap.S b/modules/axhal/src/arch/loongarch64/trap.S new file mode 100644 index 0000000000..ed905724db --- /dev/null +++ b/modules/axhal/src/arch/loongarch64/trap.S @@ -0,0 +1,153 @@ +.comm kernelsp, 0x1000, 0x1000 + +.macro SAVE_STATIC_REGS + st.d $s0, $sp, 8*23 + st.d $s1, $sp, 8*24 + st.d $s2, $sp, 8*25 + st.d $s3, $sp, 8*26 + st.d $s4, $sp, 8*27 + st.d $s5, $sp, 8*28 + st.d $s6, $sp, 8*29 + st.d $s7, $sp, 8*30 + st.d $s8, $sp, 8*31 +.endm + +.macro LOAD_STATIC_REGS + ld.d $s0, $sp, 8*23 + ld.d $s1, $sp, 8*24 + ld.d $s2, $sp, 8*25 + ld.d $s3, $sp, 8*26 + ld.d $s4, $sp, 8*27 + ld.d $s5, $sp, 8*28 + ld.d $s6, $sp, 8*29 + ld.d $s7, $sp, 8*30 + ld.d $s8, $sp, 8*31 +.endm + +.macro SAVE_ARGUMENT_REGS + st.d $a0, $sp, 8*4 + st.d $a1, $sp, 8*5 + st.d $a2, $sp, 8*6 + st.d $a3, $sp, 8*7 + st.d $a4, $sp, 8*8 + st.d $a5, $sp, 8*9 + st.d $a6, $sp, 8*10 + st.d $a7, $sp, 8*11 +.endm + +.macro LOAD_ARGUMENT_REGS + ld.d $a0, $sp, 8*4 + ld.d $a1, $sp, 8*5 + ld.d $a2, $sp, 8*6 + ld.d $a3, $sp, 8*7 + ld.d $a4, $sp, 8*8 + ld.d $a5, $sp, 8*9 + ld.d $a6, $sp, 8*10 + ld.d $a7, $sp, 8*11 +.endm + +.macro SAVE_TEMP_REGS + st.d $t0, $sp, 8*12 + st.d $t1, $sp, 8*13 + st.d $t2, $sp, 8*14 + st.d $t3, $sp, 8*15 + st.d $t4, $sp, 8*16 + st.d $t5, $sp, 8*17 + st.d $t6, $sp, 8*18 + st.d $t7, $sp, 8*19 + st.d $t8, $sp, 8*20 +.endm + +.macro LOAD_TEMP_REGS + ld.d $t0, $sp, 8*12 + ld.d $t1, $sp, 8*13 + ld.d $t2, $sp, 8*14 + ld.d $t3, $sp, 8*15 + ld.d $t4, $sp, 8*16 + ld.d $t5, $sp, 8*17 + ld.d $t6, $sp, 8*18 + ld.d $t7, $sp, 8*19 + ld.d $t8, $sp, 8*20 +.endm + +.macro SAVE_CSR_REGS + csrrd $t2, 0x1 + st.d $t2, $sp, 8*33 // prmd + csrrd $t2, 0x0 + st.d $t2, $sp, 8*32 // crmd + csrrd $t2, 0x2 + st.d $t2, $sp, 8*34 // euen + csrrd $t2, 0x4 + st.d $t2, $sp, 8*35 // ecfg + csrrd $t2, 0x5 + st.d $t2, $sp, 8*36 // estat +.endm + +.macro LOAD_SOME_REGS + ld.d $a0, $sp, 8*33 // prmd + andi $a0, $a0, 0x3 // extract pplv bit (previous privilege level) + beqz $a0, 8f + ld.d $r21, $sp, 8*21 // reserved reg +8: + ld.d $a0, $sp, 8*37 // era + addi.d $a0, $a0, 0x4 // era + 4 + csrwr $a0, 0x6 + ld.d $a0, $sp, 8*33 // prmd + csrwr $a0, 0x1 + ld.d $ra, $sp, 8*1 // ra + + LOAD_ARGUMENT_REGS + + ld.d $tp, $sp, 8*2 // thread pointer + ld.d $fp, $sp, 8*22 // frame pointer +.endm + + +.macro SAVE_REGS + addi.d $sp, $sp, -{trapframe_size} // allocate space + st.d $sp, $sp, 8*3 // sp + st.d $ra, $sp, 8*1 // ra + + SAVE_ARGUMENT_REGS + SAVE_TEMP_REGS + SAVE_STATIC_REGS + SAVE_CSR_REGS + + csrrd $ra, 0x6 + st.d $ra, $sp, 8*37 // era + + st.d $tp, $sp, 8*2 // thread pointer + st.d $r21, $sp, 8*21 // reserved reg + st.d $fp, $sp, 8*22 // frame pointer + + move $a0, $sp +.endm + + +.macro LOAD_REGS + ld.d $sp, $sp, 8*3 + LOAD_STATIC_REGS + + LOAD_TEMP_REGS + + LOAD_SOME_REGS + + //ld.d $sp, $sp, 8*3 // sp + addi.d $sp, $sp, {trapframe_size} + +.endm + + +.section .text +.balign 4096 +.global trap_vector_base +trap_vector_base: + SAVE_REGS + + bl loongarch64_trap_handler + + LOAD_REGS + + ertn + + diff --git a/modules/axhal/src/arch/loongarch64/trap.rs b/modules/axhal/src/arch/loongarch64/trap.rs new file mode 100644 index 0000000000..5a5957e61d --- /dev/null +++ b/modules/axhal/src/arch/loongarch64/trap.rs @@ -0,0 +1,34 @@ +use super::context::TrapFrame; +use loongarch64::register::csr::Register; + +use loongarch64::register::estat::{Estat, Exception, Interrupt, Trap}; +use loongarch64::register::ticlr::Ticlr; + +core::arch::global_asm!( + include_str!("trap.S"), + trapframe_size = const core::mem::size_of::(), +); + +fn handle_breakpoint(era: &mut usize) { + debug!("Exception(Breakpoint) @ {:#x} ", era); +} + +#[no_mangle] +fn loongarch64_trap_handler(tf: &mut TrapFrame) { + let cause = Estat::read().cause(); + match cause { + Trap::Exception(Exception::Breakpoint) => handle_breakpoint(&mut tf.era), + Trap::Interrupt(Interrupt::Timer) => { + Ticlr::read().clear_timer().write(); + let irq_num: usize = tf.estat.trailing_zeros() as usize; + crate::trap::handle_irq_extern(irq_num) + } + Trap::Interrupt(_) => { + let irq_num: usize = tf.estat.trailing_zeros() as usize; + crate::trap::handle_irq_extern(irq_num) + } + _ => { + panic!("Unhandled trap {:?} @ {:#x}:\n{:#x?}", cause, tf.era, tf); + } + } +} diff --git a/modules/axhal/src/arch/mod.rs b/modules/axhal/src/arch/mod.rs index b8bc0af3d0..7220281628 100644 --- a/modules/axhal/src/arch/mod.rs +++ b/modules/axhal/src/arch/mod.rs @@ -10,5 +10,8 @@ cfg_if::cfg_if! { } else if #[cfg(target_arch = "aarch64")]{ mod aarch64; pub use self::aarch64::*; + } else if #[cfg(target_arch = "loongarch64")]{ + mod loongarch64; + pub use self::loongarch64::*; } } diff --git a/modules/axhal/src/cpu.rs b/modules/axhal/src/cpu.rs index d0ee27a341..37c750329c 100644 --- a/modules/axhal/src/cpu.rs +++ b/modules/axhal/src/cpu.rs @@ -45,6 +45,10 @@ pub fn current_task_ptr() -> *const T { use tock_registers::interfaces::Readable; aarch64_cpu::registers::SP_EL0.get() as _ } + #[cfg(target_arch = "loongarch64")] + unsafe { + CURRENT_TASK_PTR.read_current_raw() as _ + } } /// Sets the pointer to the current task with preemption-safety. @@ -71,6 +75,10 @@ pub unsafe fn set_current_task_ptr(ptr: *const T) { use tock_registers::interfaces::Writeable; aarch64_cpu::registers::SP_EL0.set(ptr as u64) } + #[cfg(target_arch = "loongarch64")] + unsafe { + CURRENT_TASK_PTR.write_current_raw(ptr as usize) + } } #[allow(dead_code)] diff --git a/modules/axhal/src/platform/mod.rs b/modules/axhal/src/platform/mod.rs index a39151c47f..8437dcf623 100644 --- a/modules/axhal/src/platform/mod.rs +++ b/modules/axhal/src/platform/mod.rs @@ -22,7 +22,10 @@ cfg_if::cfg_if! { } else if #[cfg(all(target_arch = "aarch64", platform_family = "aarch64-bsta1000b"))] { mod aarch64_bsta1000b; pub use self::aarch64_bsta1000b::*; - } else { + } else if #[cfg(all(target_arch = "loongarch64", platform_family = "loongarch64-qemu-virt"))] { + mod qemu_virt_loongarch64; + pub use self::qemu_virt_loongarch64::*; + }else { mod dummy; pub use self::dummy::*; } diff --git a/modules/axhal/src/platform/qemu_virt_loongarch64/boot.rs b/modules/axhal/src/platform/qemu_virt_loongarch64/boot.rs new file mode 100644 index 0000000000..588cdfaf52 --- /dev/null +++ b/modules/axhal/src/platform/qemu_virt_loongarch64/boot.rs @@ -0,0 +1,96 @@ +use axconfig::TASK_STACK_SIZE; + +#[link_section = ".bss.stack"] +static mut BOOT_STACK: [u8; TASK_STACK_SIZE] = [0; TASK_STACK_SIZE]; +#[allow(unused)] +pub static mut SMP_BOOT_STACK_TOP: usize = 0; + +unsafe fn init_mmu() { + use loongarch64::register::csr::Register; + use loongarch64::tlb::Pwch; + use loongarch64::tlb::Pwcl; + + Pwcl::read() + .set_ptbase(12) //页表起始位置 + .set_ptwidth(9) //页表宽度为9位 + .set_dir1_base(21) //第一级页目录表起始位置 + .set_dir1_width(9) //第一级页目录表宽度为9位 + .set_dir2_base(30) //第二级页目录表起始位置 + .set_dir2_width(9) //第二级页目录表宽度为9位 + .write(); + Pwch::read() + .set_dir3_base(39) //第三级页目录表 + .set_dir3_width(8) //第三级页目录表宽度为9位 + //.set_dir4_base(48) //第四级页目录表 + .set_dir4_width(0) //第四级页目录表 + .write(); +} + +/// The earliest entry point for the primary CPU. +/// +/// We can't use bl to jump to higher address, so we use jirl to jump to higher address. +#[naked] +#[no_mangle] +#[link_section = ".text.boot"] +unsafe extern "C" fn _start() -> ! { + core::arch::asm!(" + ori $t0, $zero, 0x1 # CSR_DMW1_PLV0 + lu52i.d $t0, $t0, -2048 # UC, PLV0, 0x8000 xxxx xxxx xxxx + csrwr $t0, 0x180 # LOONGARCH_CSR_DMWIN0 + ori $t0, $zero, 0x11 # CSR_DMW1_MAT | CSR_DMW1_PLV0 + lu52i.d $t0, $t0, -1792 # CA, PLV0, 0x9000 xxxx xxxx xxxx + csrwr $t0, 0x181 # LOONGARCH_CSR_DMWIN1 + + bl {init_mmu} + + # Enable PG + li.w $t0, 0xb0 # PLV=0, IE=0, PG=1 + csrwr $t0, 0x0 # LOONGARCH_CSR_CRMD + li.w $t0, 0x00 # PLV=0, PIE=0, PWE=0 + csrwr $t0, 0x1 # LOONGARCH_CSR_PRMD + li.w $t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 + csrwr $t0, 0x2 # LOONGARCH_CSR_EUEN + + bl {init_tlb} + + la.global $sp, {boot_stack} + li.d $t0, {boot_stack_size} + add.d $sp, $sp, $t0 # setup boot stack + csrrd $a0, 0x20 # cpuid + la.global $t0, {entry} + jirl $zero,$t0,0 + ", + boot_stack_size = const TASK_STACK_SIZE, + boot_stack = sym BOOT_STACK, + init_mmu = sym init_mmu, + init_tlb = sym crate::arch::init_tlb, + entry = sym super::rust_entry, + options(noreturn), + ) +} + +/// The earliest entry point for secondary CPUs. +#[cfg(feature = "smp")] +#[naked] +#[no_mangle] +#[link_section = ".text.boot"] +unsafe extern "C" fn _start_secondary() -> ! { + core::arch::asm!(" + ori $t0, $zero, 0x1 # CSR_DMW1_PLV0 + lu52i.d $t0, $t0, -2048 # UC, PLV0, 0x8000 xxxx xxxx xxxx + csrwr $t0, 0x180 # LOONGARCH_CSR_DMWIN0 + ori $t0, $zero, 0x11 # CSR_DMW1_MAT | CSR_DMW1_PLV0 + lu52i.d $t0, $t0, -1792 # CA, PLV0, 0x9000 xxxx xxxx xxxx + csrwr $t0, 0x181 # LOONGARCH_CSR_DMWIN1 + la.abs $t0, {sm_boot_stack_top} + ld.d $sp, $t0,0 # read boot stack top + + csrrd $a0, 0x20 # cpuid + la.global $t0, {entry} + jirl $zero,$t0,0 + ", + sm_boot_stack_top = sym SMP_BOOT_STACK_TOP, + entry = sym super::rust_entry_secondary, + options(noreturn), + ) +} diff --git a/modules/axhal/src/platform/qemu_virt_loongarch64/console.rs b/modules/axhal/src/platform/qemu_virt_loongarch64/console.rs new file mode 100644 index 0000000000..1176b86a9b --- /dev/null +++ b/modules/axhal/src/platform/qemu_virt_loongarch64/console.rs @@ -0,0 +1,77 @@ +//! Uart 16550. + +use core::fmt::Write; +use spinlock::SpinNoIrq; + +const UART_ADDR: usize = 0x900000001FE001E0; + +static COM1: SpinNoIrq = SpinNoIrq::new(Uart::new(UART_ADDR)); + +pub struct Uart { + base_address: usize, +} + +impl Uart { + pub const fn new(base_address: usize) -> Self { + Uart { base_address } + } + + pub fn putchar(&mut self, c: u8) { + let mut ptr = self.base_address as *mut u8; + loop { + unsafe { + let c = ptr.add(5).read_volatile(); + if c & (1 << 5) != 0 { + break; + } + } + } + ptr = self.base_address as *mut u8; + unsafe { + ptr.add(0).write_volatile(c); + } + } + + pub fn getchar(&mut self) -> Option { + let ptr = self.base_address as *mut u8; + unsafe { + if ptr.add(5).read_volatile() & 1 == 0 { + // The DR bit is 0, meaning no data + None + } else { + // The DR bit is 1, meaning data! + Some(ptr.add(0).read_volatile()) + } + } + } +} +impl Write for Uart { + fn write_str(&mut self, s: &str) -> core::fmt::Result { + for c in s.bytes() { + self.putchar(c); + } + Ok(()) + } +} + +/// Writes a byte to the console. +pub fn putchar(c: u8) { + let mut uart = COM1.lock(); + match c { + b'\n' => { + uart.putchar(b'\r'); + uart.putchar(b'\n'); + } + c => uart.putchar(c), + } +} + +pub fn write_fmt(args: core::fmt::Arguments) { + use core::fmt::Write; + COM1.lock().write_fmt(args).unwrap(); +} + +/// Reads a byte from the console, or returns [`None`] if no input is available. +pub fn getchar() -> Option { + COM1.lock().getchar() +} diff --git a/modules/axhal/src/platform/qemu_virt_loongarch64/irq.rs b/modules/axhal/src/platform/qemu_virt_loongarch64/irq.rs new file mode 100644 index 0000000000..a3d95f18bf --- /dev/null +++ b/modules/axhal/src/platform/qemu_virt_loongarch64/irq.rs @@ -0,0 +1,64 @@ +use crate::irq::IrqHandler; +use lazy_init::LazyInit; +use loongarch64::register::csr::Register; +use loongarch64::register::tcfg::Tcfg; +pub(super) const CSR_ECFG_VS_SHIFT: usize = 16; +pub(super) const CSR_ECFG_LIE_TI_SHIFT: usize = 11; +pub(super) const TI_VEC: usize = 0x1 << CSR_ECFG_LIE_TI_SHIFT; +/// HWI mask +pub(super) const HWI_VEC: usize = 0x3fc; + +pub(super) const SWI_IRQ_NUM: usize = 0; + +/// The maximum number of IRQs. +pub const MAX_IRQ_COUNT: usize = 1024; + +/// The timer IRQ number +pub const TIMER_IRQ_NUM: usize = 11; + +static TIMER_HANDLER: LazyInit = LazyInit::new(); + +macro_rules! with_cause { + ($cause: expr, @TIMER => $timer_op: expr, @EXT => $ext_op: expr $(,)?) => { + match $cause { + TIMER_IRQ_NUM => $timer_op, + S_EXT => $ext_op, + _ => panic!("invalid trap cause: {:#x}", $cause), + } + }; +} +/// Enables or disables the given IRQ. +pub fn set_enable(vector: usize, enabled: bool) { + if vector == 11 { + if enabled { + Tcfg::read() + .set_enable(true) + .set_initval(800000000 as usize) + .set_loop(false) + .write(); + } + } +} + +/// Registers an IRQ handler for the given IRQ. +/// +/// It also enables the IRQ if the registration succeeds. It returns `false` if +/// the registration failed. +/// +pub fn register_handler(vector: usize, handler: IrqHandler) -> bool { + crate::irq::register_handler_common(vector, handler) +} + +/// Dispatches the IRQ. +/// +/// This function is called by the common interrupt handler. It looks +/// up in the IRQ handler table and calls the corresponding handler. If +/// necessary, it also acknowledges the interrupt controller after handling. +pub fn dispatch_irq(vector: usize) { + crate::irq::dispatch_irq_common(vector); +} + +pub(super) fn init_primary() { + // enable soft interrupts, timer interrupts, and external interrupts + // disable_irqs(); +} diff --git a/modules/axhal/src/platform/qemu_virt_loongarch64/mem.rs b/modules/axhal/src/platform/qemu_virt_loongarch64/mem.rs new file mode 100644 index 0000000000..bad6113c42 --- /dev/null +++ b/modules/axhal/src/platform/qemu_virt_loongarch64/mem.rs @@ -0,0 +1,6 @@ +use crate::mem::MemRegion; + +/// Returns platform-specific memory regions. +pub(crate) fn platform_regions() -> impl Iterator { + crate::mem::default_free_regions().chain(crate::mem::default_mmio_regions()) +} diff --git a/modules/axhal/src/platform/qemu_virt_loongarch64/misc.rs b/modules/axhal/src/platform/qemu_virt_loongarch64/misc.rs new file mode 100644 index 0000000000..2bda15cd4f --- /dev/null +++ b/modules/axhal/src/platform/qemu_virt_loongarch64/misc.rs @@ -0,0 +1,6 @@ +/// Shutdown the whole system, including all CPUs. +pub fn terminate() -> ! { + loop { + crate::arch::halt(); + } +} diff --git a/modules/axhal/src/platform/qemu_virt_loongarch64/mod.rs b/modules/axhal/src/platform/qemu_virt_loongarch64/mod.rs new file mode 100644 index 0000000000..c41893ffab --- /dev/null +++ b/modules/axhal/src/platform/qemu_virt_loongarch64/mod.rs @@ -0,0 +1,51 @@ +mod boot; +pub mod console; +pub mod mem; +pub mod misc; +pub mod time; + +#[cfg(feature = "irq")] +pub mod irq; + +#[cfg(feature = "smp")] +pub mod mp; + +extern "C" { + fn trap_vector_base(); + fn rust_main(cpu_id: usize, dtb: usize); + fn _sbss(); + fn _ebss(); + #[cfg(feature = "smp")] + fn rust_main_secondary(cpu_id: usize); +} + +#[no_mangle] +unsafe extern "C" fn rust_entry(cpu_id: usize, _dtb: usize) { + crate::mem::clear_bss(); + crate::cpu::init_primary(cpu_id); + crate::arch::set_trap_vector_base(trap_vector_base as usize); + rust_main(cpu_id, 0); +} + +#[cfg(feature = "smp")] +unsafe extern "C" fn rust_entry_secondary(cpu_id: usize) { + crate::arch::set_trap_vector_base(trap_vector_base as usize); + crate::cpu::init_secondary(cpu_id); + rust_main_secondary(cpu_id); +} + +/// Initializes the platform devices for the primary CPU. +/// +/// For example, the interrupt controller and external interrupts. +pub fn platform_init() { + // use loongarch64::register::csr::Register; + #[cfg(feature = "irq")] + { + self::irq::init_primary(); + self::time::init_primary(); + } +} + +/// Initializes the platform devices for secondary CPUs. +#[cfg(feature = "smp")] +pub fn platform_init_secondary() {} diff --git a/modules/axhal/src/platform/qemu_virt_loongarch64/mp.rs b/modules/axhal/src/platform/qemu_virt_loongarch64/mp.rs new file mode 100644 index 0000000000..c48fb4a49d --- /dev/null +++ b/modules/axhal/src/platform/qemu_virt_loongarch64/mp.rs @@ -0,0 +1,15 @@ +use crate::mem::{phys_to_virt, PhysAddr}; +use loongarch64::ipi::{csr_mail_send, send_ipi_single}; + +/// Starts the given secondary CPU with its boot stack. +pub fn start_secondary_cpu(hartid: usize, stack_top: PhysAddr) { + extern "C" { + fn _start_secondary(); + } + let stack_top_virt_addr = phys_to_virt(stack_top).as_usize(); + unsafe { + super::boot::SMP_BOOT_STACK_TOP = stack_top_virt_addr; + } + csr_mail_send(_start_secondary as u64, hartid, 0); + send_ipi_single(hartid, 1); +} diff --git a/modules/axhal/src/platform/qemu_virt_loongarch64/time.rs b/modules/axhal/src/platform/qemu_virt_loongarch64/time.rs new file mode 100644 index 0000000000..6398a3d168 --- /dev/null +++ b/modules/axhal/src/platform/qemu_virt_loongarch64/time.rs @@ -0,0 +1,45 @@ +// use loongarch64::register::csr::Register; +// use loongarch64::register::ticlr::Ticlr; +use loongarch64::register::time::Time; + +const NANOS_PER_TICK: u64 = crate::time::NANOS_PER_SEC / axconfig::TIMER_FREQUENCY as u64; + +/// Returns the current clock time in hardware ticks. +#[inline] +pub fn current_ticks() -> u64 { + Time::read() as u64 +} + +/// Converts hardware ticks to nanoseconds. +#[inline] +pub const fn ticks_to_nanos(ticks: u64) -> u64 { + ticks * NANOS_PER_TICK +} + +/// Converts nanoseconds to hardware ticks. +#[inline] +pub const fn nanos_to_ticks(nanos: u64) -> u64 { + nanos / NANOS_PER_TICK +} + +/// Set a one-shot timer. +/// +/// A timer interrupt will be triggered at the given deadline (in nanoseconds). +#[cfg(feature = "irq")] +pub fn set_oneshot_timer(deadline_ns: u64) { + use loongarch64::register::csr::Register; + use loongarch64::register::tcfg::Tcfg; + Tcfg::read() + .set_enable(true) + .set_loop(false) + .set_initval(nanos_to_ticks(deadline_ns) as usize) + .write(); //设置计时器的配置 +} +#[cfg(feature = "irq")] +pub(super) fn init_primary() { + { + use crate::arch::disable_irqs; + disable_irqs(); + Ticlr::read().clear_timer().write(); //清除时钟中断 + } +} diff --git a/platforms/loongarch64-qemu-virt.toml b/platforms/loongarch64-qemu-virt.toml new file mode 100644 index 0000000000..73474abbf5 --- /dev/null +++ b/platforms/loongarch64-qemu-virt.toml @@ -0,0 +1,35 @@ +# Architecture identifier. +arch = "loongarch64" +# Platform identifier. +platform = "loongarch64-qemu-virt" +# Platform family. +family = "loongarch64-qemu-virt" + +# Base address of the whole physical memory. +phys-memory-base = "0x0" +# Size of the whole physical memory. +phys-memory-size = "0x800_0000" # 128M +# Base physical address of the kernel image. +kernel-base-paddr = "0x000_1000" +# Base virtual address of the kernel image. +kernel-base-vaddr = "0x9000_0000_0000_1000" +# Linear mapping offset, for quick conversions between physical and virtual +# addresses. +phys-virt-offset = "0x9000_0000_0000_0000" +# MMIO regions with format (`base_paddr`, `size`). +mmio-regions = [ + ["0xfec0_0000", "0x1000"], # IO APIC + ["0xfed0_0000", "0x1000"], # HPET + ["0xfee0_0000", "0x1000"], # Local APIC +] +# VirtIO MMIO regions with format (`base_paddr`, `size`). +virtio-mmio-regions = [ + ["0x4004_0000", "0x1000"], # virtio-pci-common-virtio-net + ["0x4004_1000", "0x1000"], # virtio-pci-isr-virtio-net + ["0x4004_2000", "0x1000"], # virtio-pci-device-virtio-net + ["0x4004_3000", "0x1000"], # virtio-pci-notify-virtio-net +] +# Timer interrupt frequency in Hz. +timer-frequency = "1_000_000_000" # 10MHz + + diff --git a/scripts/make/cargo.mk b/scripts/make/cargo.mk index fc07ea2dae..e4aff599d4 100644 --- a/scripts/make/cargo.mk +++ b/scripts/make/cargo.mk @@ -23,6 +23,10 @@ ifeq ($(ARCH), x86_64) RUSTFLAGS += -C link-arg=--no-relax endif +ifeq ($(ARCH),loongarch64) + build_args += -Z build-std +endif + ifeq ($(MAKECMDGOALS), doc_check_missing) RUSTDOCFLAGS += -D missing-docs endif diff --git a/scripts/make/qemu.mk b/scripts/make/qemu.mk index 3ed4326140..64d4dd4c97 100644 --- a/scripts/make/qemu.mk +++ b/scripts/make/qemu.mk @@ -24,7 +24,18 @@ qemu_args-aarch64 := \ -machine virt \ -kernel $(OUT_BIN) +LOONGARCH_BIOS = tools/la64/loongarch_bios_0310.bin +qemu_args-loongarch64 := \ + -bios $(LOONGARCH_BIOS) \ + -kernel $(OUT_ELF) \ + -vga none \ + + +ifeq ($(ARCH), loongarch64) +qemu_args-y := -m 1G -smp $(SMP) $(qemu_args-$(ARCH)) +else qemu_args-y := -m 128M -smp $(SMP) $(qemu_args-$(ARCH)) +endif qemu_args-$(BLK) += \ -device virtio-blk-$(vdev-suffix),drive=disk0 \ @@ -67,11 +78,25 @@ else endif define run_qemu + $(call before_run_qemu) @printf " $(CYAN_C)Running$(END_C) on qemu...\n" $(call run_cmd,$(QEMU),$(qemu_args-y)) + $(call after_run_qemu) endef define run_qemu_debug @printf " $(CYAN_C)Debugging$(END_C) on qemu...\n" $(call run_cmd,$(QEMU),$(qemu_args-debug)) endef + +define before_run_qemu + $(if $(filter $(ARCH), loongarch64), \ + @cp tools/la64/efi-virtio.rom . \ + ) +endef + +define after_run_qemu + $(if $(filter $(ARCH), loongarch64), \ + @rm efi-virtio.rom \ + ) +endef \ No newline at end of file diff --git a/tools/la64/efi-virtio.rom b/tools/la64/efi-virtio.rom new file mode 100644 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