From 4f8faa60cb312e32d1158ee728602d86a1090743 Mon Sep 17 00:00:00 2001 From: Sebastian Holzapfel Date: Wed, 12 Jun 2024 17:43:52 +0200 Subject: [PATCH] gateware/sim: update testbenches for s/clk_fs/strobe --- gateware/drivers/ak4619.sv | 15 +++++------ gateware/sim/ak4619/tb_ak4619.py | 29 +++++++++------------- gateware/sim/cal/tb_cal.py | 21 +++++++++++----- gateware/sim/integration/tb_integration.py | 9 +++---- gateware/sim/transpose/tb_transpose.py | 22 ++++++++++------ gateware/sim/vca/tb_vca.py | 20 ++++++++++----- 6 files changed, 66 insertions(+), 50 deletions(-) diff --git a/gateware/drivers/ak4619.sv b/gateware/drivers/ak4619.sv index 1d64f51..56fcfef 100644 --- a/gateware/drivers/ak4619.sv +++ b/gateware/drivers/ak4619.sv @@ -71,18 +71,19 @@ assign bit_counter = clkdiv[5:1]; always_ff @(posedge clk_256fs) begin if (rst) begin + sdin1 <= 0; clkdiv <= 0; - dac_words = 0; - sample_out0 <= 0; - sample_out1 <= 0; - sample_out2 <= 0; - sample_out3 <= 0; + adc_words[0] <= 0; + adc_words[1] <= 0; + adc_words[2] <= 0; + adc_words[3] <= 0; + dac_words <= 0; end else if (strobe) begin // Synchronize clkdiv to the incoming sample strobe, latching // our inputs and outputs in the clock cycle that `strobe` is high. clkdiv <= 8'h0; - dac_words = {sample_in3, sample_in2, - sample_in1, sample_in0}; + dac_words <= {sample_in3, sample_in2, + sample_in1, sample_in0}; sample_out0 <= adc_words[0]; sample_out1 <= adc_words[1]; sample_out2 <= adc_words[2]; diff --git a/gateware/sim/ak4619/tb_ak4619.py b/gateware/sim/ak4619/tb_ak4619.py index fc229ce..7e18e34 100644 --- a/gateware/sim/ak4619/tb_ak4619.py +++ b/gateware/sim/ak4619/tb_ak4619.py @@ -19,6 +19,10 @@ async def test_ak4619_00(dut): clk_256fs = Clock(dut.clk_256fs, 83, units='ns') cocotb.start_soon(clk_256fs.start()) + dut.sample_in0.value = Force(0) + dut.sample_in1.value = Force(0) + dut.sample_in2.value = Force(0) + dut.sample_in3.value = Force(0) dut.strobe.value = 0 dut.sdout1.value = 0 dut.rst.value = 1 @@ -35,14 +39,13 @@ async def strobe(): dut.rst.value = 0 cocotb.start_soon(strobe()) - await i2s_clock_out_u32(dut.bick, dut.sdout1, TEST_L1) - await i2s_clock_out_u32(dut.bick, dut.sdout1, TEST_R1) await i2s_clock_out_u32(dut.bick, dut.sdout1, TEST_L0) await i2s_clock_out_u32(dut.bick, dut.sdout1, TEST_R0) + await i2s_clock_out_u32(dut.bick, dut.sdout1, TEST_L1) + await i2s_clock_out_u32(dut.bick, dut.sdout1, TEST_R1) - # Note: this edge is also where dac_words <= sample_in (sample.sv) + await FallingEdge(dut.strobe) - await RisingEdge(dut.clk_256fs) print("Data clocked from sdout1 present at sample_outX:") print(hex(dut.sample_out0.value.integer)) print(hex(dut.sample_out1.value.integer)) @@ -59,8 +62,7 @@ async def strobe(): dut.sample_in2.value = Force(TEST_L1 >> 16) dut.sample_in3.value = Force(TEST_R1 >> 16) - await FallingEdge(dut.lrck) - await FallingEdge(dut.lrck) + await RisingEdge(dut.strobe) result_l0 = await i2s_clock_in_u32(dut.bick, dut.sdin1) result_r0 = await i2s_clock_in_u32(dut.bick, dut.sdin1) @@ -73,14 +75,7 @@ async def strobe(): print(hex(result_l1)) print(hex(result_r1)) - assert result_l0 == TEST_L0 - assert result_r0 == TEST_R0 - assert result_l1 == TEST_L1 - assert result_r1 == TEST_R1 - - dut.sample_in0.value = Release() - dut.sample_in1.value = Release() - dut.sample_in2.value = Release() - dut.sample_in3.value = Release() - - await FallingEdge(dut.clk_fs) + assert result_l0 & 0xFFFFFF00 == TEST_L0 + assert result_r0 & 0xFFFFFF00 == TEST_R0 + assert result_l1 & 0xFFFFFF00 == TEST_L1 + assert result_r1 & 0xFFFFFF00 == TEST_R1 diff --git a/gateware/sim/cal/tb_cal.py b/gateware/sim/cal/tb_cal.py index 0efccfb..c055c0a 100644 --- a/gateware/sim/cal/tb_cal.py +++ b/gateware/sim/cal/tb_cal.py @@ -14,13 +14,24 @@ async def test_cal_00(dut): sample_width = 16 clk_256fs = Clock(dut.clk_256fs, 83, units='ns') - clk_fs = Clock(dut.clk_fs, 83*256, units='ns') cocotb.start_soon(clk_256fs.start()) - cocotb.start_soon(clk_fs.start(start_high=False)) # Simulate all jacks connected so the cal core doesn't zero them dut.jack.value = Force(0xFF) + # Add 1/256 sample strobe + dut.strobe.value = 0 + async def strobe(): + while True: + dut.strobe.value = 1 + await ClockCycles(dut.clk_256fs, 1) + dut.strobe.value = 0 + await ClockCycles(dut.clk_256fs, 255) + await RisingEdge(dut.clk_256fs) + await RisingEdge(dut.clk_256fs) + dut.rst.value = 0 + cocotb.start_soon(strobe()) + clampl = -2**(sample_width-1) + 1 clamph = 2**(sample_width-1) - 1; @@ -65,10 +76,8 @@ async def test_cal_00(dut): if expect > clamph: expect = clamph if expect < clampl: expect = clampl print(f"ch={channel}\t{int(value):6d}\t", end="") - await FallingEdge(dut.clk_fs) - await RisingEdge(dut.clk_fs) - await RisingEdge(dut.clk_fs) - await RisingEdge(dut.clk_fs) + await RisingEdge(dut.strobe) + await RisingEdge(dut.strobe) output = signed_from_bits(cal_outx.value, sample_width) print(f"=>\t{int(output):6d}\t(expect={expect})") cal_inx.value = Release() diff --git a/gateware/sim/integration/tb_integration.py b/gateware/sim/integration/tb_integration.py index a9666c5..c9d39a7 100644 --- a/gateware/sim/integration/tb_integration.py +++ b/gateware/sim/integration/tb_integration.py @@ -29,18 +29,15 @@ async def test_integration_00(dut): await RisingEdge(dut.clk_256fs) dut.sysmgr_instance.pll_lock.value = 1 - await FallingEdge(dut.strobe) - await FallingEdge(dut.strobe) - ak4619 = dut.eurorack_pmod1.ak4619_instance + await FallingEdge(dut.strobe) + N = 20 for i in range(N): - v = bits_from_signed(0x00FF, sample_width)#int(16000*math.sin((2*math.pi*i)/N)), sample_width) - - await FallingEdge(ak4619.lrck) + v = bits_from_signed(int(16000*math.sin((2*math.pi*i)/N)), sample_width) await i2s_clock_out_u32(ak4619.bick, ak4619.sdout1, v << 16) await i2s_clock_out_u32(ak4619.bick, ak4619.sdout1, v << 16) diff --git a/gateware/sim/transpose/tb_transpose.py b/gateware/sim/transpose/tb_transpose.py index 253caf6..80fa743 100644 --- a/gateware/sim/transpose/tb_transpose.py +++ b/gateware/sim/transpose/tb_transpose.py @@ -16,12 +16,18 @@ async def test_transpose_00(dut): sample_width = 16 - clock = Clock(dut.sample_clk, 5, units='us') - cocotb.start_soon(clock.start()) - - # Not needed at the moment as we aren't pipelining things - #clock = Clock(dut.clk, 83, units='ns') - #cocotb.start_soon(clock.start()) + clk_256fs = Clock(dut.clk, 83, units='ns') + cocotb.start_soon(clk_256fs.start()) + + # Add 1/256 sample strobe + dut.strobe.value = 0 + async def strobe(): + while True: + dut.strobe.value = 1 + await ClockCycles(dut.clk, 1) + dut.strobe.value = 0 + await ClockCycles(dut.clk, 255) + cocotb.start_soon(strobe()) dut.sample_in.value = 0 dut.pitch.value = 5000*4 @@ -29,7 +35,7 @@ async def test_transpose_00(dut): # Clock in some zeroes so the delay lines are full of zeroes. for i in range(1024): - await RisingEdge(dut.sample_clk) + await RisingEdge(dut.strobe) # Stimulate the pitch shifter with a sine wave and make sure # the output does not have any discontinuities @@ -38,7 +44,7 @@ async def test_transpose_00(dut): breaknext = False for i in range(2048): - await RisingEdge(dut.sample_clk) + await RisingEdge(dut.strobe) data_in = int(1000*math.sin(i / 100)) diff --git a/gateware/sim/vca/tb_vca.py b/gateware/sim/vca/tb_vca.py index 6afcc48..8937da4 100644 --- a/gateware/sim/vca/tb_vca.py +++ b/gateware/sim/vca/tb_vca.py @@ -14,17 +14,25 @@ async def test_vca_00(dut): sample_width=16 - clock = Clock(dut.sample_clk, 5, units='us') - cocotb.start_soon(clock.start()) - clock = Clock(dut.clk, 83, units='ns') - cocotb.start_soon(clock.start()) + clk_256fs = Clock(dut.clk, 83, units='ns') + cocotb.start_soon(clk_256fs.start()) + + # Add 1/256 sample strobe + dut.strobe.value = 0 + async def strobe(): + while True: + dut.strobe.value = 1 + await ClockCycles(dut.clk, 1) + dut.strobe.value = 0 + await ClockCycles(dut.clk, 255) + cocotb.start_soon(strobe()) ins = [dut.sample_in0, dut.sample_in1, dut.sample_in2, dut.sample_in3] outs = [dut.sample_out0, dut.sample_out1, dut.sample_out2, dut.sample_out3] for i in range(10): - await RisingEdge(dut.sample_clk) + await RisingEdge(dut.strobe) data_in = [] for inx in ins: @@ -32,7 +40,7 @@ async def test_vca_00(dut): data_in.append(random_sample) inx.value = bits_from_signed(random_sample, sample_width) - await RisingEdge(dut.sample_clk) + await RisingEdge(dut.strobe) data_out = [signed_from_bits(out.value, sample_width) for out in outs]