From c297f7a592671644b8e67e365a91989748d9645b Mon Sep 17 00:00:00 2001
From: Sebastian Holzapfel <me@sebholzapfel.com>
Date: Sat, 23 Sep 2023 10:03:55 +0200
Subject: [PATCH] fix indexing bug, gaps are there again

---
 firmware/litex-fw/src/log.rs  | 2 +-
 firmware/litex-fw/src/main.rs | 5 +----
 sim.py                        | 4 ++--
 3 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/firmware/litex-fw/src/log.rs b/firmware/litex-fw/src/log.rs
index b693e95..5a7591f 100644
--- a/firmware/litex-fw/src/log.rs
+++ b/firmware/litex-fw/src/log.rs
@@ -76,7 +76,7 @@ fn default_handler() {
         if offset == 0x1f {
             for i in 0x10..0x20 {
                 unsafe {
-                    BUF_IN_CP[i] = *buf.add(i+0x10);
+                    BUF_IN_CP[i] = *buf.add(i);
                 }
             }
         }
diff --git a/firmware/litex-fw/src/main.rs b/firmware/litex-fw/src/main.rs
index 6088b6c..74812b0 100644
--- a/firmware/litex-fw/src/main.rs
+++ b/firmware/litex-fw/src/main.rs
@@ -8,9 +8,6 @@ use litex_hal::uart::UartError;
 use litex_pac as pac;
 use riscv_rt::entry;
 use riscv;
-use core::sync::atomic::fence;
-use core::sync::atomic::compiler_fence;
-use core::sync::atomic::Ordering;
 use core::arch::asm;
 
 mod log;
@@ -47,7 +44,7 @@ fn main() -> ! {
 
     for i in 0..BUF_SZ_WORDS {
         unsafe {
-            BUF_OUT[i] = i as u32;
+            BUF_OUT[i] = 256*((i as u32));
         }
     }
 
diff --git a/sim.py b/sim.py
index 44be49b..6a5281f 100755
--- a/sim.py
+++ b/sim.py
@@ -59,8 +59,8 @@ def add_eurorack_pmod(soc):
     soc.comb += [
         # ADC -> CDC
         cdc_in0.sink.valid.eq(1),
-        cdc_in0.sink.payload.data.eq(0xDEADBEEF),
-        #cdc_in0.sink.payload.data.eq(eurorack_pmod.cal_in0),
+        #cdc_in0.sink.payload.data.eq(0xDEADBEEF),
+        cdc_in0.sink.payload.data.eq(eurorack_pmod.cal_in0),
         # CDC -> DAC
         cdc_out0.source.ready.eq(1),
         eurorack_pmod.cal_out0.eq(cdc_out0.source.payload.data)