works in simulation with some hacks

.gitignore

@@ -3,3 +3,5 @@ build/
 firmware/deps/generated-litex-pac/src/*
 .aider*
 *.fbi
+*.vcd
+*.sv

.gitmodules

@@ -76,3 +76,9 @@
 [submodule "firmware/deps/ssd1322"]
 	path = firmware/deps/ssd1322
 	url = [email protected]:schnommus/ssd1322.git
+[submodule "deps/litescope"]
+	path = deps/litescope
+	url = https://github.com/enjoy-digital/litescope
+[submodule "deps/pythondata-misc-tapcfg"]
+	path = deps/pythondata-misc-tapcfg
+	url = https://github.com/litex-hub/pythondata-misc-tapcfg.git

example-colorlight-i5.py

@@ -120,11 +120,8 @@ def into_mirror(soc, eurorack_pmod):
     ]
 
 def into_shifter(soc, eurorack_pmod):
-
     N_VOICES = 4
-
     create_voices(soc, eurorack_pmod, N_VOICES)
-
     add_dma_router(soc, eurorack_pmod, output_capable=False)
 
 def add_oled(soc):

firmware/polyvec/src/main.rs

@@ -267,6 +267,7 @@ impl State {
             }
         } else {
         */
+        /*
             let pmod1 = &peripherals.EURORACK_PMOD1;
             let pmod2 = &peripherals.EURORACK_PMOD2;
             let pmod3 = &peripherals.EURORACK_PMOD3;
@@ -353,6 +354,7 @@ impl State {
                 }
             }
 
+            */
             /*
         }
             */

rtl/dsp.py

@@ -146,7 +146,7 @@ def __init__(self, mac, dw=32, fbits=16):
 
         # Saturation thresholds
         SAT_HI = Constant(float_to_fp(1.0), dtype)
-        SAT_LO = -Constant(float_to_fp(1.0), dtype)
+        SAT_LO = Constant(-float_to_fp(1.0), dtype)
 
         fsm = FSM(reset_state="WAIT-SINK-VALID")
         self.submodules += fsm
@@ -178,13 +178,7 @@ def fsm_mac(this_state, next_state,
         fsm_mac("MAC-RESONANCE", "SATURATION",
                 self.x - self.y, self.resonance, self.x, self.rezz)
         fsm.act("SATURATION",
-            If(self.rezz > SAT_HI,
-                NextValue(self.sat, SAT_HI),
-            ).Elif(self.rezz < SAT_LO,
-                NextValue(self.sat, SAT_LO),
-            ).Else(
-                NextValue(self.sat, self.rezz),
-            ),
+            NextValue(self.sat, self.rezz),
             NextState("MAC-LADDER0"),
         )
         fsm_mac("MAC-LADDER0", "MAC-LADDER1",
@@ -508,7 +502,7 @@ def create_voices(soc, eurorack_pmod, n_voices=4):
     # Route DC block outputs to CDC entry
     for n in range(n_voices):
         soc.comb += getattr(cdc_vout0.sink.payload, f"out{n}").eq(multi_lpf.dc_blocks[n].source.sample)
-        soc.comb += multi_lpf.dc_blocks[n].source.ready.eq(cdc_vout0.sink.ready)
+        soc.comb += multi_lpf.dc_blocks[n].source.ready.eq(cdc_vout0.sink.valid)
 
     # Route CDC exit to eurorack-pmod
     soc.comb += cdc_vout0.source.ready.eq(1),

rtl/eurorack_pmod_wrapper.py

@@ -12,7 +12,7 @@
         )
 
 class EurorackPmod(Module, AutoCSR):
-    def __init__(self, platform, pads, w=16, output_csr_read_only=True, drive_shared_pads=None, external_reset=None):
+    def __init__(self, platform, pads, w=16, output_csr_read_only=True, drive_shared_pads=None, external_reset=None, sim=False):
         self.w = w
         self.cal_mem_file = os.path.join(SOURCES_ROOT, "cal/cal_mem.hex")
         self.codec_cfg_file = os.path.join(SOURCES_ROOT, "drivers/ak4619-cfg.hex")
@@ -179,22 +179,27 @@ def __init__(self, platform, pads, w=16, output_csr_read_only=True, drive_shared
 
 
         # FIXME: For now these tristate implementations are ECP5 specific.
-
-        self.specials += Instance("TRELLIS_IO",
-            p_DIR = "BIDIR",
-            i_B   = pads.i2c_scl,
-            i_I   = 0,
-            o_O   = self.i2c_scl_i,
-            i_T   = ~self.i2c_scl_oe
-        )
-
-        self.specials += Instance("TRELLIS_IO",
-            p_DIR = "BIDIR",
-            i_B   = pads.i2c_sda,
-            i_I   = 0,
-            o_O   = self.i2c_sda_i,
-            i_T   = ~self.i2c_sda_oe
-        )
+        if not sim:
+            self.specials += Instance("TRELLIS_IO",
+                p_DIR = "BIDIR",
+                i_B   = pads.i2c_scl,
+                i_I   = 0,
+                o_O   = self.i2c_scl_i,
+                i_T   = ~self.i2c_scl_oe
+            )
+
+            self.specials += Instance("TRELLIS_IO",
+                p_DIR = "BIDIR",
+                i_B   = pads.i2c_sda,
+                i_I   = 0,
+                o_O   = self.i2c_sda_i,
+                i_T   = ~self.i2c_sda_oe
+            )
+        else:
+            self.comb += [
+                pads.i2c_sda.eq(~self.i2c_sda_oe),
+                pads.i2c_scl.eq(~self.i2c_scl_oe),
+            ]
 
         # Exposed CSRs
 

sim.py

@@ -0,0 +1,69 @@
+#!/usr/bin/env python3
+
+import lxbuildenv
+
+from litex.tools.litex_sim import main
+
+from litex.build.generic_platform import *
+from litex.soc.cores.clock import *
+from litex.soc.cores.dma import *
+from litex.soc.interconnect import wishbone
+from litex.soc.interconnect.stream import ClockDomainCrossing
+from litex.soc.interconnect.csr_eventmanager import *
+
+from rtl.eurorack_pmod_wrapper import EurorackPmod
+from rtl.dsp import create_voices
+
+CLK_FREQ_SYS = 5e6
+CLK_FREQ_256FS = 1e6
+CLK_FREQ_FS = CLK_FREQ_256FS / 256
+
+_io_extra_clockers = [
+    ("clocker_256fs", 0, Pins(1)),
+]
+
+_io_eurorack_pmod = [
+    ("eurorack_pmod_clk0", 0,
+        Subsignal("mclk",    Pins(1)),
+        Subsignal("bick",    Pins(1)),
+        Subsignal("lrck",    Pins(1)),
+        Subsignal("pdn",     Pins(1)),
+        IOStandard("LVCMOS33")
+    ),
+    ("eurorack_pmod0", 0,
+        Subsignal("i2c_sda", Pins(1)),
+        Subsignal("i2c_scl", Pins(1)),
+        Subsignal("sdin1",   Pins(1)),
+        Subsignal("sdout1",  Pins(1)),
+    ),
+]
+def sim_soc_extension(sim_config, soc):
+
+    # Add 256Fs PLL simulation
+    soc.platform.add_extension(_io_extra_clockers)
+    sim_config.add_clocker("clocker_256fs", freq_hz=int(CLK_FREQ_256FS))
+    soc.cd_clk_256fs = ClockDomain()
+    soc.comb += [
+        soc.cd_clk_256fs.clk.eq(soc.platform.request("clocker_256fs")),
+    ]
+
+    # Create 1*Fs clock domain using a division register
+    soc.cd_clk_fs = ClockDomain()
+    clkdiv_fs = Signal(8)
+    soc.sync.clk_256fs += clkdiv_fs.eq(clkdiv_fs+1)
+    soc.comb += soc.cd_clk_fs.clk.eq(clkdiv_fs[-1])
+
+    # Instantiate EurorackPmod
+    soc.platform.add_extension(_io_eurorack_pmod)
+    shared_pads = soc.platform.request("eurorack_pmod_clk0")
+    pmod0_pads = soc.platform.request("eurorack_pmod0")
+    pmod0 = EurorackPmod(soc.platform, pmod0_pads, drive_shared_pads=shared_pads, sim=True)
+    soc.add_module("eurorack_pmod0", pmod0)
+
+    N_VOICES=4
+    create_voices(soc, pmod0, N_VOICES)
+
+    sim_config.add_module("i2s", ["eurorack_pmod0", "eurorack_pmod_clk0"])
+
+if __name__ == "__main__":
+    main(sys_clk_freq=CLK_FREQ_SYS, soc_extension_hook=sim_soc_extension)