Elobration error in vivado in wishbone_arbiter.vhdl

[sasi8985]

ERROR: [XSIM 43-4187] File "C:/Users/NALLURI SASI KIRAN/Desktop/microwatt-master/wishbone_arbiter.vhdl" Line 41 : The "Vhdl 2008 Sequential Conditional Signal Assignment" is not supported yet for simulation.
ERROR: [XSIM 43-4187] File "C:/Users/NALLURI SASI KIRAN/Desktop/microwatt-master/litedram/extras/litedram-wrapper-l2.vhdl" Line 474 : The "Vhdl 2008 Condition Operator" is not supported yet for simulation.

[umarcor]

See #293 (comment).