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Hi @gogulfresh , I just took a look at the modification it involves.
It is doable but would require a refactor of the code, so I'm not going to do it.
However, feel free to do a Pull Request.
If you want to go that route, you will have to modify plugin/verilog_instance.py.
I just added test.sv in the repo so you can make sure your modifications don't break anything.
Hi!
Is it possible to add an option thus the comments from the original port list are kept?
Thanks!
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