From 9baeb2ead48fe8922166e6d3c072791db26edd0c Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Thu, 12 Dec 2024 09:18:13 +0100 Subject: [PATCH] Add tests Signed-off-by: Ryszard Rozak --- test_regress/t/t_class_eq_wild.py | 18 ++++++++++++++++++ test_regress/t/t_class_eq_wild.v | 22 ++++++++++++++++++++++ test_regress/t/t_inside_queue_elem.py | 18 ++++++++++++++++++ test_regress/t/t_inside_queue_elem.v | 18 ++++++++++++++++++ 4 files changed, 76 insertions(+) create mode 100755 test_regress/t/t_class_eq_wild.py create mode 100644 test_regress/t/t_class_eq_wild.v create mode 100755 test_regress/t/t_inside_queue_elem.py create mode 100644 test_regress/t/t_inside_queue_elem.v diff --git a/test_regress/t/t_class_eq_wild.py b/test_regress/t/t_class_eq_wild.py new file mode 100755 index 0000000000..d4f9864418 --- /dev/null +++ b/test_regress/t/t_class_eq_wild.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_eq_wild.v b/test_regress/t/t_class_eq_wild.v new file mode 100644 index 0000000000..98f5d7f973 --- /dev/null +++ b/test_regress/t/t_class_eq_wild.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +class A; +endclass + +module t (/*AUTOARG*/); + + initial begin + A a1 = new; + A a2 = new; + if (a1 ==? a2) $stop; + if (!a1 !=? a2) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_inside_queue_elem.py b/test_regress/t/t_inside_queue_elem.py new file mode 100755 index 0000000000..d4f9864418 --- /dev/null +++ b/test_regress/t/t_inside_queue_elem.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside_queue_elem.v b/test_regress/t/t_inside_queue_elem.v new file mode 100644 index 0000000000..2854757bde --- /dev/null +++ b/test_regress/t/t_inside_queue_elem.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + initial begin + int q[$] = {1, 2}; + if (!(1 inside {q[0], q[1]})) $stop; + if (3 inside {q[0], q[1]}) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule