diff --git a/test_regress/t/t_pattern_method.py b/test_regress/t/t_pattern_method.py
new file mode 100755
index 0000000000..d4f9864418
--- /dev/null
+++ b/test_regress/t/t_pattern_method.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_pattern_method.v b/test_regress/t/t_pattern_method.v
new file mode 100644
index 0000000000..8d660efdbd
--- /dev/null
+++ b/test_regress/t/t_pattern_method.v
@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+   function int get_first(int arg[2]);
+   return arg[0];
+   endfunction
+endclass
+
+module t (/*AUTOARG*/);
+
+   initial begin
+      Cls c = new;
+      int a = c.get_first('{32'd1, 32'd2});
+      if (a != 1) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule