From ea566dc11018ac47bacbae05a45f7041856c00bb Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Fri, 1 Nov 2024 00:14:26 +0000
Subject: [PATCH] Update revisions caliptra-rtl 26cda9bd [RTL] Remove QSPI/UART
 and merge AXI module tweaks from FPGA testing (#619)

---
 deps.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps.json b/deps.json
index dc308ef..fca9c7c 100644
--- a/deps.json
+++ b/deps.json
@@ -1 +1 @@
-{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "fb49826c16aab4902f2bedb5456f2f9ec118a97a"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "ad30bae95f921c7356abebaf9f1f65230c5c7b9f"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "2bcf063ceb5c06fb4d4af6089a0d437ed4c5ee66"}]}
\ No newline at end of file
+{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "fb49826c16aab4902f2bedb5456f2f9ec118a97a"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "ad30bae95f921c7356abebaf9f1f65230c5c7b9f"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "26cda9bd019248a0516427facb2602a9274f1d17"}]}
\ No newline at end of file