From 2699d3ea910f45071a8655ee59c1e4a156431500 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Fri, 22 Sep 2023 00:09:14 +0000
Subject: [PATCH] Update revisions Cores-VeeR-EL2 5d3e906c Merge pull request
 #118 from antmicro/mkurc/dma-tests 6d82e5ee Fixed rng seed for
 microarchitectural tests db61bacf Added collection of microarchitectural test
 logs and waveforms and uploading them as artifacts ab3cd73f Added DMA tests
 to GH actions CI 89305b9e Deduplicated code, isolated common sequence
 definitions c0a76e98 Added external=True to run() in noxfile.py e1c88c27
 Fixed incorrect address range checking in scoreboards 42603917 Increased wait
 time for AXI response e29316c0 Added nox session for DMA tests 5077c870
 Python code linting and formatting 17f02bea Added tests for the debugging
 interface, isolated some shared code e750ae16 Added a test for ECC error
 handling 507a697d Added address decoding error test 2233c999 Fixed address
 alignment 7d2ed758 Fixed the monitor for the memory bus 28ad6a8c Support for
 overlapped AXI read transactions, read test for the DMA b6f57403 Support for
 overlapped AXI write transactions to excercise DMA FIFO bd7a955a Added
 independent ICCM and DCCM busy assertion. fce0d112 Complete write test for
 ICCM and DCCM write through the DMA port 84b90bb1 Initial implementation of
 AXI4 Lite BFM and monitor 60633a1c Initial DMA module test for its state
 after reset 6cf2aa72 Merge pull request #116 from antmicro/mkurc/pic-tests
 de87df8c Adjust GitHub actions CI for microarchitectural tests 0ae72aec Moved
 pic-gw to pic_gw 41d36129 PIC: implement tests 1f66dc36 PIC Gateway:
 implement tests 1071a973 Add PIC tests to noxfile

---
 deps.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps.json b/deps.json
index a38b779..890fcec 100644
--- a/deps.json
+++ b/deps.json
@@ -1 +1 @@
-{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "dccad9e6a39b196261e1ba4586eb8a1711783fed"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "c2f37c0d0dfc871245a78ba447887907de0bcbb7"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "440a21d2ce0173139273cf7261a66f490bc630f6"}]}
\ No newline at end of file
+{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "dccad9e6a39b196261e1ba4586eb8a1711783fed"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "5d3e906cc6aa0e7801a4fd61ec4fc033fd3f06a1"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "440a21d2ce0173139273cf7261a66f490bc630f6"}]}
\ No newline at end of file