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Build and run Pipeline Manager server application. + +``` +./build_server.sh +cd kenning-pipeline-manager +./run +``` + +2. Run Topwrap's client application, that will connect to a running Pipeline Manager server app. + +``` +python -m fpga_topwrap kpm_client [-h ip_addr] [-p port] FILES +``` + +Topwrap will then try to connect to the server running on `ip_addr:port` and send a specification generated from `FILES`, which should be IP core description yamls. + +If `-h` or `-p` options are not specified, ip address `127.0.0.1` and port `9000` will be chosen by default. + +(generating-ip-yamls)= + +## Generating IP core description YAMLs + +You can also use Topwrap to generate ip core description yamls from HDL sources, +that can be later used in your `project.yml`: + +``` +python -m fpga_topwrap parse HDL_FILES +``` + +In HDL source files, ports that belong to the same interface (e.g. wishbone or AXI), +have often a common prefix, which corresponds to the interface name. If such naming +convention is followed in the HDL sources, Topwrap can also divide ports into user-specified +interfaces, or automatically deduce interfaces names when generating yaml file: + +``` +python -m fpga_topwrap parse --iface wishbone --iface s_axi HDL_FILES + +python -m fpga_topwrap parse --iface-deduce HDL_FILES +``` + +To get help, use: + +``` +python -m fpga_topwrap [build|kpm_client|parse] --help +``` diff --git a/_sources/description_files.md.txt b/_sources/description_files.md.txt new file mode 100644 index 00000000..5bf243bc --- /dev/null +++ b/_sources/description_files.md.txt @@ -0,0 +1,250 @@ +(description-files)= + +# Description files + +(design-description)= + +## Design Description + +To create a complete, fully synthesizable design, a proper design file is needed. +It's used to specify IP cores, set their parameters' values, describe hierarchies for the project, +connect the IPs and hierarchies, and pick external ports (those which will be connected to physical I/O). + +You can see example design files in `examples` directory. The structure is as below: + +```yaml +ips: + # specify relations between IPs names in the design yaml + # and IP cores description yamls and modules + {ip_instance_name}: + file: {path_to_yaml_file_of_the_ip} + module: {name_of_the_HDL_module} + ... + +design: + hierarchies: # specify hierarchies designs + {hierarchy_name_1}: + design: + parameters: + ... + ports: # ports connections internal to this hierarchy + ... + interfaces: # interfaces connections internal to this hierarchy + ... + {nested_hierarchy_name}: + ... + external: + # external ports and/or interfaces of this hierarchy; these can be + # referenced in the upper-level `ports`, `interfaces` or `external` section + ... + {hierarchy_name_2}: + ... + + parameters: # specify IPs parameter values to be overridden + {ip_instance_name}: + {param_name} : {param_value} + ... + + ports: + # specify incoming ports connections of an IP named `ip1_name` + {ip1_name}: + {port1_name} : [{ip2_name}, {port2_name}] + ... + # specify incoming ports connections of a hierarchy named `hier_name` + {hier_name}: + {port1_name} : [{ip_name}, {port2_name}] + ... + # specify external ports connections + {ip_instance_name}: + {port_name} : ext_port_name + ... + + interfaces: + # specify incoming interfaces connections of `ip1_name` IP + {ip1_name}: + {iface1_name} : [{ip2_name}, {iface2_name}] + ... + # specify incoming interfaces connections of `hier_name` hierarchy + {hier_name}: + {iface1_name} : [{ip_name}, {iface2_name}] + ... + # specify external interfaces connections + {ip_instance_name}: + {iface_name} : ext_iface_name + ... + +external: # specify names of external ports and interfaces of the top module + ports: + out: + - {ext_port_name} + inout: + - {ext_port_name} + interfaces: + in: + - {ext_iface_name} +``` + +In order for an IP to be present in the generated design, it must be specified in `ports` or `interfaces` sections as a key. This means that even if it has no incoming connections from any other IP or hierarchy, the `ports` or `interfaces` sections must contain `ip_name: {}` entry. + +The design description yaml format allows creating hierarchical designs. In order to create a hierarchy, it suffices to add its name as a key in the `design` section and describe the hierarchy design "recursively" by using the same keys and values (`ports`, `parameters` etc.) as in the top-level design (see above). Hierarchies can be nested recursively, which means that you can create a hierarchy inside another one. + +Note that IPs and hierarchies names cannot be duplicated on the same hierarchy level. For example, the `design` section cannot contain two identical keys, but it's correct to have `ip_name` key in this section and `ip_name` in the `design` section of some hierarchy. + +(ip-description)= + +## IP description files + +Every IP wrapped by Topwrap needs a description file in YAML format. + +The ports of an IP should be placed in global `signals` node, followed by the direction of `in`, `out` or `inout`. +Here's an example description of ports of Clock Crossing IP: + +```yaml +# file: clock_crossing.yaml +signals: + in: + - clkA + - A + - clkB + out: + - B +``` + +The previous example is enough to make use of any IP. However, in order to benefit from connecting whole interfaces at once, ports must belong to a named interface like in this example: + +```yaml +#file: axis_width_converter.yaml +s_axis: + interface: AXIStream + mode: slave + signals: + in: + TDATA: [s_axis_tdata, 63, 0] + TKEEP: [s_axis_tkeep, 7, 0] + TVALID: s_axis_tvalid + TLAST: s_axis_tlast + TID: [s_axis_tid, 7, 0] + TDEST: [s_axis_tdest, 7, 0] + TUSER: s_axis_tuser + out: + TREADY: s_axis_tready + +m_axis: + interface: AXIStream + mode: master + signals: + in: + TREADY: m_axis_tready + out: + TDATA: [m_axis_tdata, 31, 0] + TKEEP: [m_axis_tkeep, 3, 0] + TVALID: m_axis_tvalid + TLAST: m_axis_tlast + TID: [m_axis_tid, 7, 0] + TDEST: [m_axis_tdest, 7, 0] + TUSER: m_axis_tuser +signals: # These ports don't belong to any interface + in: + - clk + - rst +``` + +Names `s_axis` and `m_axis` will be used to group the selected ports. +Each signal in an interface has a name which must match with the signal it's supposed to be connected to, for example `TDATA: port_name` will be connected to `TDATA: other_port_name`. + +Note that you don't have to write IP core description yamls by hand. You can use Topwrap's `parse` command (see {ref}`Generating IP core description YAMLs `) in order to generate yamls from HDL source files and then adjust the yaml to your needs. + +### Port widths + +The width of every port defaults to `1`. +You can specify the width using this notation: + +```yaml +s_axis: + interface: AXIStream + mode: slave + signals: + in: + TDATA: [s_axis_tdata, 63, 0] # 64 bits + ... + TVALID: s_axis_tvalid # defaults to 1 bit + +signals: + in: + - [gpio_io_i, 31, 0] # 32 bits +``` + +### Parameterization + +Port widths don't have to be hardcoded - you can use parameters to describe an IP core in a generic way. +Values specified in IP core yamls can be overriden in a design description file (see {ref}`Design Description `). + +```yaml +parameters: + DATA_WIDTH: 8 + KEEP_WIDTH: (DATA_WIDTH+7)/8 + ID_WIDTH: 8 + DEST_WIDTH: 8 + USER_WIDTH: 1 + +s_axis: + interface: AXI4Stream + mode: slave + signals: + in: + TDATA: [s_axis_tdata, DATA_WIDTH-1, 0] + TKEEP: [s_axis_tkeep, KEEP_WIDTH-1, 0] + ... + TID: [s_axis_tid, ID_WIDTH-1, 0] + TDEST: [s_axis_tdest, DEST_WIDTH-1, 0] + TUSER: [s_axis_tuser, USER_WIDTH-1, 0] +``` + +Parameters values can be integers or math expressions, which are evaluated using `numexpr.evaluate()`. + +(port-slicing)= + +### Port slicing + +You can also slice a port, to use some bits of the port as a signal that belongs to an interface. +The example below means: + +`Port m_axi_bid of the IP core is 36 bits wide. Use bits 23..12 as the BID signal of AXI master named m_axi_1` + +```yaml +m_axi_1: + interface: AXI + mode: master + signals: + in: + BID: [m_axi_bid, 35, 0, 23, 12] +``` + +(interface-description-files)= + +## Interface Description files + +Topwrap can use predefined interfaces which are descibed in YAML-formatted files. +The interfaces you use don't have to be predefined, but it's possible to perform checks +on whether all the mandatory signals are connected, when you use an interface definition. + +You can see an example file below: + +```yaml +name: AXI4Stream +port_prefix: AXIS +signals: + required: + - TVALID + - TDATA + - TLAST + - TREADY + optional: + - TID + - TDEST + - TKEEP + - TSTRB + - TUSER +``` + +The name of an interface has to be unique. We also specify a prefix which will be used as a shortened identifier. diff --git a/_sources/developers_guide/examples.md.txt b/_sources/developers_guide/examples.md.txt new file mode 100644 index 00000000..7b6600eb --- /dev/null +++ b/_sources/developers_guide/examples.md.txt @@ -0,0 +1,21 @@ +## Examples + +:::{note} +Basic usage of examples is explained in the {ref}`getting-started` section. +::: + +Examples provided with this project should cover from very simple designs to complex fully synthesizable cores. +They should be sorted by increasing complexity and number of used features, e.g: +- 101: minimal base design +- 102: introduce user to parameters +- 103: introduce user to slicing +- 104: introduce user to interfaces +- 105: etc. + +Developers are encouraged to create/add new examples in the same spirit. +Simple examples are used to teach how to use this tool and demonstrate its features. +Real-world use cases are also welcome to prove that the implementation is mature enough to handle practical designs. + +:::{note} +The goal of this project is not to create a library of cores and/or their functional validation. This need is fulfilled by projects like FuseSoC, SVUnit, etc. +::: diff --git a/_sources/developers_guide/setup.md.txt b/_sources/developers_guide/setup.md.txt new file mode 100644 index 00000000..40a36629 --- /dev/null +++ b/_sources/developers_guide/setup.md.txt @@ -0,0 +1,10 @@ +# Setup + +It is recommended for developers to keep code style and frequently run tests. +In order to setup the developer's environment install python packages from `requirements.dev.txt`, which shall include `nox` and `pre-commit`: + +```bash +python -m venv venv +source venv/bin/activate +pip install -r requirements.dev.txt +``` diff --git a/_sources/developers_guide/style.md.txt b/_sources/developers_guide/style.md.txt new file mode 100644 index 00000000..7f0f2499 --- /dev/null +++ b/_sources/developers_guide/style.md.txt @@ -0,0 +1,58 @@ +# Code style + +Automatic formatting and linting of the code can be performed with either `nox` or `pre-commit`. + +## Lint with nox + +After successful setup, `nox` sessions can be executed to perform lint checks: + +```bash +nox -s isort black flake8 +``` + +:::{note} +pre-commit can also be run from nox: + +```bash +nox -s pre_commit +``` +::: +## Lint with pre-commit + +Alternatively, you can use pre-commit to perform the same job. +`Pre-commit` hooks need to be installed: + +```bash +pre-commit install +``` + +Now, each use of `git commit` in the shell will trigger actions defined in the `.pre-commit-config.yaml` file. +Pre-commit can be easily disabled with a similar command: + +```bash +pre-commit uninstall +``` + +If you wish to run `pre-commit` asynchronously, then use: + +```bash +pre-commit run --all-files +``` + +:::{note} +`pre-commit` by default also runs `nox` with `isort`,`flake8` and `black` sessions: +::: + +## Tools + +Tools used in project for maintaing code style: +* `Nox` is a tool, which simplifies management of Python testing. +[Visit nox website](https://nox.thea.codes/en/stable/) +* `Pre-commit` is a framework for managing and maintaining multi-language pre-commit hooks. +[Visit pre-commit website](https://pre-commit.com/) +* `Black` is a code formatter. +[Visit black website](https://black.readthedocs.io/en/stable/) +* `Flake8` is a tool capable of linting, styling fixes and complexity analysis. +[Visit flake8 website](https://flake8.pycqa.org/en/latest/) +* `Isort` is a Python utility to sort imports alphabetically. +[Visit isort website](https://pycqa.github.io/isort/) diff --git a/_sources/developers_guide/tests.md.txt b/_sources/developers_guide/tests.md.txt new file mode 100644 index 00000000..991d4d12 --- /dev/null +++ b/_sources/developers_guide/tests.md.txt @@ -0,0 +1,18 @@ +# Tests + +Topwrap functionality is validated with tests, leveraging the `pytest` library. + + +## Test execution + +Tests are located in the `tests` directory. +All tests can be run with `nox` by specifying the tests session: + +```bash +nox -s tests +``` + +Tests can also be launched without `nox` by executing: +```bash +pytest +``` diff --git a/_sources/elaboratable_wrapper.md.txt b/_sources/elaboratable_wrapper.md.txt new file mode 100644 index 00000000..4033430b --- /dev/null +++ b/_sources/elaboratable_wrapper.md.txt @@ -0,0 +1,12 @@ +# ElaboratableWrapper class + +{class}`ElaboratableWrapper` encapsulates an Amaranth's Elaboratable and exposes an interface compatible with other wrappers which allows making connections with them. +Supplied elaboratable must contain a `signature` property and a conforming interface as specified by [Amaranth docs](https://amaranth-lang.org/rfcs/0002-interfaces.html). +Ports' directionality, their names and widths are inferred from it. + +```{eval-rst} +.. autoclass:: fpga_topwrap.elaboratable_wrapper.ElaboratableWrapper + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/fusesoc.md.txt b/_sources/fusesoc.md.txt new file mode 100644 index 00000000..f63a8201 --- /dev/null +++ b/_sources/fusesoc.md.txt @@ -0,0 +1,38 @@ +# FuseSoC + +Toprwap uses FuseSoC to automate project generation and build process. + +A `Core` file is needed in order to generate a project. The file can be generated from a template using {class}`FuseSocBuilder` class. The `Core` file contains information about source files and synthesis tools. + +## Core file template + +A template for the core file is bundled with Topwrap (`templates/core.yaml.j2`). +You may need to edit the file to change the backend tool, set additional `Hooks` and change the FPGA part name or other parameters. +By default, {class}`FuseSocBuilder` searches for the template file in the directory you work in, so you should first copy the template into the project's location. + +## Using the FuseSocBuilder + +Here's an example of how to generate a simple project: + +```python +from fpga_topwrap.fuse_helper import FuseSocBuilder +fuse = FuseSocBuilder() + +# add source of the IPs used in the project +fuse.add_source('DMATop.v', 'verilogSource') + +# add source of the top file +fuse.add_source('top.v', 'verilogSource') + +# specify the names of the Core file and the directory where sources are stored +# generate the project +fuse.build('build/top.core', 'sources') +``` + +Now you can run FuseSoC to generate bitstream and program FPGA: + +```bash +fusesoc --cores-root build run project_1 +``` + +This requires having the suitable backend tool in your `PATH` (Vivado, for example). diff --git a/_sources/future_enhancements.md.txt b/_sources/future_enhancements.md.txt new file mode 100644 index 00000000..b54278de --- /dev/null +++ b/_sources/future_enhancements.md.txt @@ -0,0 +1,44 @@ +(future-enhancements)= + +# Future enhancements + +(hierarchical-block-designs)= +## Creating hierarchical block designs + +Currently, Topwrap supports only creating "flat" designs; one can add IP cores and create connections between them, but there is no way of organizing specific parts of the design into hierarchies. Having such a facility implemented would make it easier to create complex designs. + +Moreover, this feature is closely related to subgraphs, which will be supported shortly in Pipeline Manager. In the future, we'd also like to provide a possibility to create hierarchical designs in the Pipeline Manager, which would be a huge improvement in terms of organizing complex designs. + +(bus-management)= +## Bus management + +Another goal we'd like to achieve is to enable users to create full-featured designs with processors by providing proper support for bus management. +This should include features such as: + +* ability to specify the address of a peripheral device on the bus +* support for the most popular buses or the ones that we use (AXI, wishbone, Tile-link) + +This will require writing or creating bus arbiters (round-robin, crossbar) and providing a mechanism for connecting master(s) and slave(s) together. +As a result, the user should be able to create complex SoC with Topwrap. + +(improve-recreating-design)= +## Improve the process of recreating a design from a YAML file + +One of the main features that are supported by Topwrap and Pipeline Manager is exporting and importing user-created design to or from a design description YAML. However, during these conversions, information about the positions of user-added nodes is not preserved. This is cumbersome in the case of complicated designs since the imported nodes cannot be placed in the optimal positions. + +Therefore, one of our objectives is to provide a convenient way of creating and restoring user-created designs in Pipeline Manager, so that the user doesn't have to worry about node positions when importing a design to Pipeline Manager. + +(systemverilog-parsing)= +## Support for parsing SystemVerilog sources + +Information about IP cores is stored in {ref}`IP core description YAMLs `. These files can be generated automatically from HDL source files - currently Verilog and VHDL are supported. Our goal is to provide the possiblity of generating such YAMLs from SystemVerilog too. + +(pm-hdl-parsing)= +## Provide a way to parse HDL sources from the Pipeline Manager level + +Another issue related to HDL parsing is that the user has to manually parse HDL sources to obtain the IP core description YAMLs. Then the files need to be provided as command-line parameters when launching the Topwrap Pipeline Manager client application. Therefore, we aim to provide a way of parsing HDL files and including them in the editor directly from the Pipeline Manager level. + +(toplevel-vhdl)= +## Ability to produce top-level wrappers in VHDL + +Topwrap now uses Amaranth to generate top-level design in Verilog. We would also like to add the ability to produce such designs in VHDL. diff --git a/_sources/getting_started.md.txt b/_sources/getting_started.md.txt new file mode 100644 index 00000000..605714b8 --- /dev/null +++ b/_sources/getting_started.md.txt @@ -0,0 +1,175 @@ +(getting-started)= + +# Getting started + +## Installation + +1. Install required system packages: + + ``` + apt install -y git g++ make python3 python3-pip antlr4 libantlr4-runtime-dev yosys + ``` + +2. It is highly recommended to run the following steps in a Python virtual environment (e.g. [venv](https://docs.python.org/3/library/venv.html)). + +3. Install base requirements: + + ``` + pip3 install -r requirements.txt + ``` + +4. Build the Topwrap package: + + ``` + python3 setup.py build + ``` + +5. Install the Topwrap package: + + ``` + python3 setup.py install + ``` + +(example-usage)= + +## Example usage + +This section demonstrates the basic usage of Topwrap to generate IP wrappers and a top module. + +1. Create {class}`IPWrapper` objects for every IP Core you want to use: + +```yaml +ips: + dma: + file: ips/DMATop.yaml + module: DMATop + disp: + file: ips/axi_dispctrl_v1_0.yaml + module: axi_dispctrl_v1_0 +``` + +`file` and `module` are mandatory fields providing the IP description and the name of the HDL module. +You can optionally set parameter values for IP cores: + +```yaml +axi_interconnect0: + file: axi_interconnect.yaml + module: axi_interconnect + parameters: + S_COUNT: 1 + M_COUNT: 3 + ADDR_WIDTH: 32 + DATA_WIDTH: 32 + ID_WIDTH: 12 + M_BASE_ADDR: 0x43c2000043c1000043c00000 + M_ADDR_WIDTH: + value: 0x100000001000000010 + width: 96 +``` + +3. Connect desired ports of the IP cores: + +```yaml +ports: + dma: + clock: [some_other_ip, clk_out] + reset: [reset_core, reset0] + axi_interconnect0: + clk: [some_other_ip, clk_out] +``` + +4. Connect desired interfaces of the IP cores: + +```yaml +interfaces: + dma: + s_axi: [axi_interconnect0, m_axi_0] + axi_interconnect0: + m_axi: [some_other_ip, 's_axi'] +``` + +5. Specify external ports or interfaces of the top module and connect them with chosen IP cores' ports or interfaces: + +```yaml +ports: + dma: + io_irq_readerDone: readerDone + io_irq_writerDone: writerDone + +... + +external: + ports: + out: + - readerDone + - writerDone + interfaces: + ... +``` + +6. Create a Core file template for FuseSoC, or use a default one bundled with Topwrap. + +You may want to modify the file to add dependencies, source files, or change the target board. +The file should be named `core.yaml.j2`. You can find an example template in `examples/hdmi` directory of the project. +If you don't create any template a default template bundled with Topwrap will be used (stored in `templates` directory). + +7. Place any additional source files in a directory, which we will be calling `sources` here. + +8. Run Topwrap: + + ``` + python -m fpga_topwrap build --design project.yml --sources sources + ``` + +### Example PWM design + +There's an example setup in `examples/pwm`. + +In order to generate the top module, run: + +``` +make generate +``` + +In order to generate bitstream, add Vivado to your path and run: + +``` +make +``` + +The FPGA design utilizes an AXI-mapped PWM IP Core. +You can access its registers starting from address `0x4000000` (that's the base address of `AXI_GP0` on ZYNQ). +Each IP Core used in the project is declared in `ips` section in `project.yml` file. +`ports` section allows to connect individual ports of IP Cores, and `interfaces` is used analogously for connecting whole interfaces. +Finally, you can specify which ports will be used as external I/O in `external` section. + +To connect the I/O signals to specific FPGA pins, you need proper mappings in a constraints file. See `zynq.xdc` used in the setup and modify it accordingly. + +```{image} img/pwm.png +``` + +### Example HDMI design + +There's an example setup stored in `examples/hdmi`. + +You can generate bitstream for desired target: + +> - Snickerdoodle Black: +> +> ``` +> make snickerdoodle +> ``` +> +> - Zynq Video Board: +> +> ``` +> make zvb +> ``` + +If you wish to generate HDL sources without running Vivado, you can use: + +``` +make generate +``` + +You can find more information in README of the example setup. diff --git a/_sources/helpers.md.txt b/_sources/helpers.md.txt new file mode 100644 index 00000000..905eceb6 --- /dev/null +++ b/_sources/helpers.md.txt @@ -0,0 +1,27 @@ +# Helpers + +```{eval-rst} +.. autoclass:: fpga_topwrap.interface.InterfaceDef + :members: + + .. automethod:: __init__ +``` + +```{eval-rst} +.. autofunction:: fpga_topwrap.interface.get_interface_by_name +``` + +```{eval-rst} +.. autofunction:: fpga_topwrap.interface.get_interface_by_prefix +``` + +```{eval-rst} +.. autoclass:: fpga_topwrap.config.Config + :members: + + .. automethod:: __init__ +``` + +```{eval-rst} +.. autofunction:: fpga_topwrap.util.check_interface_compliance +``` diff --git a/_sources/index.md.txt b/_sources/index.md.txt new file mode 100644 index 00000000..1523a538 --- /dev/null +++ b/_sources/index.md.txt @@ -0,0 +1,32 @@ +# Welcome to Topwrap! + +```{toctree} +:caption: Documentation +:maxdepth: 2 +introduction +getting_started +description_files +cli +pipeline_manager +wrapper_port +ipwrapper +ipconnect +elaboratable_wrapper +helpers +fusesoc +``` + +```{toctree} +:caption: Developer's Guide +:maxdepth: 2 +developers_guide/setup +developers_guide/style +developers_guide/tests +developers_guide/examples +``` + +```{toctree} +:caption: Future enhancements +:maxdepth: 1 +future_enhancements +``` diff --git a/_sources/introduction.md.txt b/_sources/introduction.md.txt new file mode 100644 index 00000000..c20bab14 --- /dev/null +++ b/_sources/introduction.md.txt @@ -0,0 +1,16 @@ +# Introduction + +Topwrap is a tool for generating HDL wrappers for simple blocks as well as digital systems and can be used for creating complex SoCs from single blocks contained in wrappers. + + +## Wrappers +These wrappers standardize names of ports that belong to an interfaces (e.g. UART, AXI etc.) + +```{image} img/wrapper.png +``` +## Top module +Top modules connect IPs and/or Wrappers by either ports\` names or interfaces\` names to ease connecting multi-wire interfaces without the need to connect each wire separately. + +```{image} img/ipconnect.png +``` + diff --git a/_sources/ipconnect.md.txt b/_sources/ipconnect.md.txt new file mode 100644 index 00000000..787f0e9e --- /dev/null +++ b/_sources/ipconnect.md.txt @@ -0,0 +1,26 @@ +# IPConnect class + +Topwrap uses {class}`IPConnect` to encapsulate IP Cores in a module, and connect their wires and interfaces. + +After the object is created, IPs can be added using {code}`add_ip` method: + +```python +# create a wrapper for an IP +dma := IPWrapper('DMATop.yaml', ip_name='DMATop'), + +ipc = IPConnect() +ip.add_ip(dma) + +# add other IPs +``` + +IPs are connected using {code}`make_connections` function. +Ports and interfaces can be set as external input/output/inout with {code}`make_external_ports_interfaces` and retrieved with {code}`get_ports`. +For a wider example of using the {class}`IPConnect` see {ref}`Getting Started ` + +```{eval-rst} +.. autoclass:: fpga_topwrap.ipconnect.IPConnect + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/ipwrapper.md.txt b/_sources/ipwrapper.md.txt new file mode 100644 index 00000000..a6ac463f --- /dev/null +++ b/_sources/ipwrapper.md.txt @@ -0,0 +1,11 @@ +# IPWrapper class + +{class}`IPWrapper` is the main class used to instantiate an IP Core and generate HDL wrapper. +It's used to standardize names of ports that belong to interfaces to ease connecting multiple IPs. + +```{eval-rst} +.. autoclass:: fpga_topwrap.ipwrapper.IPWrapper + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/pipeline_manager.md.txt b/_sources/pipeline_manager.md.txt new file mode 100644 index 00000000..4eb6c820 --- /dev/null +++ b/_sources/pipeline_manager.md.txt @@ -0,0 +1,95 @@ +(kenning-pipeline-manager)= + +# Kenning Pipeline Manager + +Topwrap can make use of [Kenning Pipeline Manager](https://github.com/antmicro/kenning-pipeline-manager) to visualize the process of creating block design. + +## Run Topwrap with Pipeline Manager + +1. Build and run Pipeline Manager server + + In order to start creating block design in Pipeline Manager, you need to first build and run a server application - here is a brief instruction on how to achieve this (the process of building and installation of Pipeline Manager is described in detail in its [documentation](https://antmicro.github.io/kenning-pipeline-manager/project-readme.html#building-and-running)): + + ``` + ./build_server.sh + cd kenning-pipeline-manager + ./run + ``` + + After executing the above-mentioned commands, the Pipeline Manager server is waiting for an external application (i.e. Topwrap) to connect on `127.0.0.1:9000` and you can connect to the web GUI frontend in your browser on `http://127.0.0.1:5000`. + +2. Establish connection with Topwrap + + Once the Pipeline Manager server is running, you can now launch Topwrap's client application in order to connect to the server. You need to specify: + * IP address (`127.0.0.1` is default) + * listening port (`9000` is default) + * yamls describing IP cores, that will be used in the block design + + An example command, that runs Topwrap's client, may look like this: + ``` + python -m fpga_topwrap kpm_client -h 127.0.0.1 -p 9000 \ + fpga_topwrap/ips/axi/axi_axil_adapter.yaml \ + examples/pwm/ipcores/{litex_pwm.yml,ps7.yaml} + ``` + +3. Create block design in Pipeline Manager + + Upon successful connection to a Pipeline Manager server, Topwrap will generate and send to the server a specification describing the structure of previously selected IP cores. After that, you are free to create a custom block design by means of: + * adding IP core instances to the block design. Each Pipeline Manager's node has `delete` and `rename` options, which make it possible to remove the selected node and change its name respectively. This means that you can create multiple instances of the same IP core. + * adjusting IP cores' parameters values. Each node may have input boxes in which you can enter parameters' values (default parameter values are added while adding an IP core to the block design): + ```{image} img/node_parameters.png + ``` + * connecting IP cores' ports and interfaces. Only connections between ports or interfaces of matching types are allowed. This is automatically checked by Pipeline Manager, as the types of nodes' ports and interfaces are contained in the loaded specification, so Pipeline Manager will prevent you from connecting non-matching interfaces (e.g. *AXI4* with *AXI4Lite* or a port with an interface). A green line will be displayed if a connection is possible to create, or a red line elsewhere: + ```{image} img/invalid_connection.png + ``` + * specifying external ports or interfaces in the top module. This can be done by adding `External Input`, `External Output` or `External Inout` metanodes and creating connections between them and chosen ports or interfaces. Note that you should adjust the name of the external port or interface in a textbox inside selected metanode. In the example below, output port `pwm` of `litex_pwm_top` IP core will be made external in the generated top module and the external port name will be set to `ext_pwm`: + ```{image} img/external_port.png + ``` + Note, that you don't always have to create a new block design by hand - you can use a {ref}`design import ` feature to load an existing block design from a description in Topwrap's yaml format. + + An example block design in Pipeline Manager for the PWM project may look like this: + + ```{image} img/pwm_design.png + ``` + +## Pipeline Manager features + +While creating a custom block design, you can make use of the following Pipeline Manager's features: +* export (save) design to a file +* import (load) design from a file +* validate design +* build design + +(export-design)= + +### Export design to yaml description file + +Created block design can be saved to a {ref}`design description file ` in yaml format, using Pipeline Manager's `Save file` option. The design description file name will be generated automatically based on current timestamp. + +(import-design)= + +### Import design from yaml description file + +Topwrap also supports conversion in the opposite way - block design in Pipeline Manager can be generated from a yaml design description file using `Load file` feature. + +(validate-design)= + +### Design validation + +Pipeline Manager is capable of performing some basic checks at runtime such as interface type checking while creating a connection. However you can also run more complex tests by using Pipeline Manager's `Validate` option. Topwrap will then respond with a validity confirmation or error messages. The rules you need to follow in order to keep your block design valid are: +* multiple IP cores with the same name are not allowed (except from external metanodes). +* parameters values can be integers of different bases (e.g. `0x28`, `40` or `0b101000`) or arithmetic expressions, that are later evaluated using [numexpr.evaluate()](https://numexpr.readthedocs.io/en/latest/api.html#numexpr.evaluate) function (e.g. `(AXI_DATA_WIDTH+1)/4` is a valid parameter value assuming that a parameter named `AXI_DATA_WIDTH` exists in the same IP core). You can also write a parameter value in a Verilog format (e.g. `8'b00011111` or `8'h1F`) - in such case it will be interpreted as a fixed-width bit vector. +* a single port or interface cannot be external and connected to another IP core at the same time. +* connections between two external metanodes are not allowed. +* all the created external output or inout ports must have unique names. Only multiple input ports of IP cores can be driven be the same external signal. + +Topwrap can also generate warnings if: +* some ports or interfaces remain unconnected. +* multiple ports are connected to an `External Input` metanode with an empty `External Name` property. +If a block design validation returns a warning, it means that the block design can be successfully built, but it is recommended to follow the suggestion and resolve a particular issue. + +(build-design)= + +### Building design + +Once the design has been created and tested for validity, you can build design using `Run` feature. If the design does not contain any errors, this will result in creating a top module, similarly when using Topwrap's `fpga_topwrap build` command. diff --git a/_sources/wrapper_port.md.txt b/_sources/wrapper_port.md.txt new file mode 100644 index 00000000..42c1d01f --- /dev/null +++ b/_sources/wrapper_port.md.txt @@ -0,0 +1,24 @@ +# Wrapper Port + +Class {class}`WrapperPort` is an extension to Amaranth's {class}`Signal`. +It wraps a port, adding a new name and optionally slicing the signal. +It adds these attributes: + +```python +WrapperPort.internal_name # name of the port in internal source to be wrapped +WrapperPort.direction # DIR_FANIN, DIR_FANOUT or DIR_NONE +WrapperPort.interface_name # name of the group of ports (interface) +WrapperPort.bounds # range of bits that belong to the port + # and range which is sliced from the port +``` + +See {ref}`Port slicing ` to know more about `bounds`. + +This is used in {code}`IPWrapper` class implementation and there should be no need to use {class}`WrapperPort` individually. + +```{eval-rst} +.. autoclass:: fpga_topwrap.amaranth_helpers.WrapperPort + :members: + + .. automethod:: __init__ +``` diff --git a/_static/fonts/0053ba6958e79f26751eabb555bd73d0.woff2 b/_static/fonts/0053ba6958e79f26751eabb555bd73d0.woff2 new file mode 100644 index 00000000..ab301009 Binary files /dev/null and b/_static/fonts/0053ba6958e79f26751eabb555bd73d0.woff2 differ diff --git a/_static/fonts/029e176ad602329b4434892101db9cf3.woff2 b/_static/fonts/029e176ad602329b4434892101db9cf3.woff2 new file mode 100644 index 00000000..09e03c95 Binary files /dev/null and b/_static/fonts/029e176ad602329b4434892101db9cf3.woff2 differ diff --git a/_static/fonts/07ff82964967feebb9c96288e0e0df05.woff2 b/_static/fonts/07ff82964967feebb9c96288e0e0df05.woff2 new file mode 100644 index 00000000..d338178b Binary files /dev/null and b/_static/fonts/07ff82964967feebb9c96288e0e0df05.woff2 differ diff --git a/_static/fonts/0948409a22b5979aa7e1ec20da9e61f1.woff2 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2007-2023 by the Sphinx team, see AUTHORS. + * :license: BSD, see LICENSE for details. + * + */ + +var stopwords = ["a", "and", "are", "as", "at", "be", "but", "by", "for", "if", "in", "into", "is", "it", "near", "no", "not", "of", "on", "or", "such", "that", "the", "their", "then", "there", "these", "they", "this", "to", "was", "will", "with"]; + + +/* Non-minified version is copied as a separate JS file, is available */ + +/** + * Porter Stemmer + */ +var Stemmer = function() { + + var step2list = { + ational: 'ate', + tional: 'tion', + enci: 'ence', + anci: 'ance', + izer: 'ize', + bli: 'ble', + alli: 'al', + entli: 'ent', + eli: 'e', + ousli: 'ous', + ization: 'ize', + ation: 'ate', + ator: 'ate', + alism: 'al', + iveness: 'ive', + fulness: 'ful', + ousness: 'ous', + aliti: 'al', + iviti: 'ive', + biliti: 'ble', + logi: 'log' + }; + + var step3list = { + icate: 'ic', + ative: '', + alize: 'al', + iciti: 'ic', + ical: 'ic', + ful: '', + ness: '' + }; + + var c = "[^aeiou]"; // consonant + var v = "[aeiouy]"; // vowel + var C = c + "[^aeiouy]*"; // consonant sequence + var V = v + "[aeiou]*"; // vowel sequence + + var mgr0 = "^(" + C + ")?" + V + C; // [C]VC... is m>0 + var meq1 = "^(" + C + ")?" + V + C + "(" + V + ")?$"; // [C]VC[V] is m=1 + var mgr1 = "^(" + C + ")?" + V + C + V + C; // [C]VCVC... is m>1 + var s_v = "^(" + C + ")?" + v; // vowel in stem + + this.stemWord = function (w) { + var stem; + var suffix; + var firstch; + var origword = w; + + if (w.length < 3) + return w; + + var re; + var re2; + var re3; + var re4; + + firstch = w.substr(0,1); + if (firstch == "y") + w = firstch.toUpperCase() + w.substr(1); + + // Step 1a + re = /^(.+?)(ss|i)es$/; + re2 = /^(.+?)([^s])s$/; + + if (re.test(w)) + w = w.replace(re,"$1$2"); + else if (re2.test(w)) + w = w.replace(re2,"$1$2"); + + // Step 1b + re = /^(.+?)eed$/; + re2 = /^(.+?)(ed|ing)$/; + if (re.test(w)) { + var fp = re.exec(w); + re = new RegExp(mgr0); + if (re.test(fp[1])) { + re = /.$/; + w = w.replace(re,""); + } + } + else if (re2.test(w)) { + var fp = re2.exec(w); + stem = fp[1]; + re2 = new RegExp(s_v); + if (re2.test(stem)) { + w = stem; + re2 = /(at|bl|iz)$/; + re3 = new RegExp("([^aeiouylsz])\\1$"); + re4 = new RegExp("^" + C + v + "[^aeiouwxy]$"); + if (re2.test(w)) + w = w + "e"; + else if (re3.test(w)) { + re = /.$/; + w = w.replace(re,""); + } + else if (re4.test(w)) + w = w + "e"; + } + } + + // Step 1c + re = /^(.+?)y$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(s_v); + if (re.test(stem)) + w = stem + "i"; + } + + // Step 2 + re = /^(.+?)(ational|tional|enci|anci|izer|bli|alli|entli|eli|ousli|ization|ation|ator|alism|iveness|fulness|ousness|aliti|iviti|biliti|logi)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step2list[suffix]; + } + + // Step 3 + re = /^(.+?)(icate|ative|alize|iciti|ical|ful|ness)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step3list[suffix]; + } + + // Step 4 + re = /^(.+?)(al|ance|ence|er|ic|able|ible|ant|ement|ment|ent|ou|ism|ate|iti|ous|ive|ize)$/; + re2 = /^(.+?)(s|t)(ion)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(mgr1); + if (re.test(stem)) + w = stem; + } + else if (re2.test(w)) { + var fp = re2.exec(w); + stem = fp[1] + fp[2]; + re2 = new RegExp(mgr1); + if (re2.test(stem)) + w = stem; + } + + // Step 5 + re = /^(.+?)e$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(mgr1); + re2 = new RegExp(meq1); + re3 = new RegExp("^" + C + v + "[^aeiouwxy]$"); + if (re.test(stem) || (re2.test(stem) && !(re3.test(stem)))) + w = stem; + } + re = /ll$/; + re2 = new RegExp(mgr1); + if (re.test(w) && re2.test(w)) { + re = /.$/; + w = w.replace(re,""); + } + + // and turn initial Y back to y + if (firstch == "y") + w = firstch.toLowerCase() + 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.state-title{fill:var(--md-mermaid-label-fg-color)!important;font-family:var(--md-mermaid-font-family)}g.stateGroup .composit{fill:var(--md-mermaid-label-bg-color)}.nodeLabel{color:var(--md-mermaid-label-fg-color);font-family:var(--md-mermaid-font-family)}.node circle.state-end,.node circle.state-start,.start-state{fill:var(--md-mermaid-edge-color);stroke:none}.end-state-inner,.end-state-outer{fill:var(--md-mermaid-edge-color)}.end-state-inner,.node circle.state-end{stroke:var(--md-mermaid-label-bg-color)}.transition{stroke:var(--md-mermaid-edge-color)}[id^=state-fork] rect,[id^=state-join] rect{fill:var(--md-mermaid-edge-color)!important;stroke:none!important}.statediagram-cluster.statediagram-cluster .inner{fill:var(--md-default-bg-color)}.statediagram-cluster rect{fill:var(--md-mermaid-node-bg-color);stroke:var(--md-mermaid-node-fg-color)}.statediagram-state rect.divider{fill:var(--md-default-fg-color--lightest);stroke:var(--md-default-fg-color--lighter)}defs #statediagram-barbEnd{stroke:var(--md-mermaid-edge-color)}.entityBox{fill:var(--md-mermaid-label-bg-color);stroke:var(--md-mermaid-node-fg-color)}.entityLabel{fill:var(--md-mermaid-label-fg-color);font-family:var(--md-mermaid-font-family)}.relationshipLabelBox{fill:var(--md-mermaid-label-bg-color);fill-opacity:1;background-color:var(--md-mermaid-label-bg-color);opacity:1}.relationshipLabel{fill:var(--md-mermaid-label-fg-color)}.relationshipLine{stroke:var(--md-mermaid-edge-color)}defs #ONE_OR_MORE_END *,defs #ONE_OR_MORE_START *,defs #ONLY_ONE_END *,defs #ONLY_ONE_START *,defs #ZERO_OR_MORE_END *,defs #ZERO_OR_MORE_START *,defs #ZERO_OR_ONE_END *,defs #ZERO_OR_ONE_START *{stroke:var(--md-mermaid-edge-color)!important}.actor,defs #ZERO_OR_MORE_END circle,defs #ZERO_OR_MORE_START circle{fill:var(--md-mermaid-label-bg-color)}.actor{stroke:var(--md-mermaid-node-fg-color)}text.actor>tspan{fill:var(--md-mermaid-label-fg-color);font-family:var(--md-mermaid-font-family)}line{stroke:var(--md-default-fg-color--lighter)}.messageLine0,.messageLine1{stroke:var(--md-mermaid-edge-color)}.loopText>tspan,.messageText,.noteText>tspan{font-family:var(--md-mermaid-font-family)!important}#arrowhead path,.loopText>tspan,.messageText,.noteText>tspan{fill:var(--md-mermaid-edge-color);stroke:none}.loopLine{stroke:var(--md-mermaid-node-fg-color)}.labelBox,.loopLine{fill:var(--md-mermaid-node-bg-color)}.labelBox{stroke:none}.labelText,.labelText>span{fill:var(--md-mermaid-node-fg-color);font-family:var(--md-mermaid-font-family)}";var tn,vs=0,gs=ce();function ys(){return typeof mermaid=="undefined"||mermaid instanceof Element?qo(`${gs.base}_static/mermaid/mermaid.min.js`):C(void 0)}function mi(e){return e.classList.remove("mermaid"),tn||(tn=ys().pipe(M(()=>mermaid.initialize({startOnLoad:!1,themeCSS:pi,sequence:{actorFontSize:"16px",messageFontSize:"16px",noteFontSize:"16px"}})),d(()=>{}),X(1))),tn.subscribe(()=>{e.classList.add("mermaid");let t=`__mermaid_${vs++}`,r=O("div",{class:"mermaid"});mermaid.mermaidAPI.render(t,e.textContent,n=>{let o=r.attachShadow({mode:"closed"});o.innerHTML=n,e.replaceWith(r)})}),tn.pipe(d(()=>({ref:e})))}function xs(e,{target$:t,print$:r}){let n=!0;return P(t.pipe(d(o=>o.closest("details:not([open])")),A(o=>e===o),d(()=>({action:"open",reveal:!0}))),r.pipe(A(o=>o||!n),M(()=>n=e.open),d(o=>({action:o?"open":"close"}))))}function di(e,t){return I(()=>{let r=new L;return r.subscribe(({action:n,reveal:o})=>{e.toggleAttribute("open",n==="open"),o&&e.scrollIntoView()}),xs(e,t).pipe(M(n=>r.next(n)),R(()=>r.complete()),d(n=>V({ref:e},n)))})}var hi=O("table");function bi(e){return e.replaceWith(hi),hi.replaceWith(ni(e)),C({ref:e})}function ws(e){let t=D(":scope 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f=Tt(o);r.hidden=c.x<16,n.hidden=c.x>f.width-s.width-16}),P(x(r,"click").pipe(d(()=>-1)),x(n,"click").pipe(d(()=>1))).pipe(te(a)).subscribe(c=>{let{width:s}=Se(o);o.scrollBy({left:s*c,behavior:"smooth"})}),Z("content.tabs.link")&&i.pipe(Pe(1),me(t)).subscribe(([{active:c},{offset:s}])=>{let f=c.innerText.trim();if(c.hasAttribute("data-md-switching"))c.removeAttribute("data-md-switching");else{let u=e.offsetTop-s.y;for(let p of D("[data-tabs]"))for(let m of D(":scope > input",p)){let h=B(`label[for="${m.id}"]`);if(h!==c&&h.innerText.trim()===f){h.setAttribute("data-md-switching",""),m.click();break}}window.scrollTo({top:e.offsetTop-u});let l=__md_get("__tabs")||[];__md_set("__tabs",[...new Set([f,...l])])}}),ws(e).pipe(M(c=>i.next(c)),R(()=>i.complete()),d(c=>V({ref:e},c)))}).pipe(Ze(se))}function gi(e,{viewport$:t,target$:r,print$:n}){return P(...D("pre:not(.mermaid) > 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I(()=>G([de(e),Ss(t)])).pipe(d(([{height:r},n])=>({height:r,hidden:n})),Q((r,n)=>r.height===n.height&&r.hidden===n.hidden),X(1))}function wi(e,{header$:t,main$:r}){return I(()=>{let n=new L,o=n.pipe(ue(1));return n.pipe(J("active"),St(t)).subscribe(([{active:i},{hidden:a}])=>{e.classList.toggle("md-header--shadow",i&&!a),e.hidden=a}),r.subscribe(n),t.pipe(te(o),d(i=>V({ref:e},i)))})}function Os(e,{viewport$:t,header$:r}){return mr(e,{viewport$:t,header$:r}).pipe(d(({offset:{y:n}})=>{let{height:o}=Se(e);return{active:n>=o}}),J("active"))}function Ei(e,t){return I(()=>{let r=new L;r.subscribe(({active:o})=>{e.classList.toggle("md-header__title--active",o)});let n=ie("article h1, .objdesc > dt .descname");return typeof n=="undefined"?k:Os(n,t).pipe(M(o=>r.next(o)),R(()=>r.complete()),d(o=>V({ref:e},o)))})}function Si(e,{viewport$:t,header$:r}){let n=r.pipe(d(({height:i})=>i),Q()),o=n.pipe(_(()=>de(e).pipe(d(({height:i})=>({top:e.offsetTop,bottom:e.offsetTop+i})),J("bottom"))));return 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o=ie("link[rel=icon]");typeof o!="undefined"&&(o.href=o.href);let i=hr().pipe(d(l=>l.map(p=>`${new URL(p,n.base)}`)),_(l=>x(document.body,"click").pipe(A(p=>!p.metaKey&&!p.ctrlKey),_(p=>{if(p.target instanceof Element){let m=p.target.closest("a");if(m&&!m.target){let h=new URL(m.href);if(h.search="",h.hash="",h.pathname!==location.pathname&&l.includes(h.toString()))return p.preventDefault(),C({url:new URL(m.href)})}}return je}))),pe()),a=x(window,"popstate").pipe(A(l=>l.state!==null),d(l=>({url:new URL(location.href),offset:l.state})),pe());P(i,a).pipe(Q((l,p)=>l.url.href===p.url.href),d(({url:l})=>l)).subscribe(t);let c=t.pipe(J("pathname"),_(l=>pr(l.href).pipe(le(()=>(lr(l),je)))),pe());i.pipe(rr(c)).subscribe(({url:l})=>{history.pushState({},"",`${l}`)});let s=new DOMParser;c.pipe(_(l=>l.text()),d(l=>s.parseFromString(l,"text/html"))).subscribe(e);let f=new Set,u=new Set;for(let l of D("script",document))l.src?f.add(new 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h=m.outerHTML;if(!u.has(h)){let b=document.createElement("script");for(let w of m.getAttributeNames())b.setAttribute(w,m.getAttribute(w));b.textContent=m.textContent,document.body.appendChild(b),u.add(h)}}}))).subscribe(),e.pipe(Pe(1),d(()=>_e("container")),_(l=>D("script",l)),mt(l=>{let p=O("script");if(l.src){for(let m of l.getAttributeNames())p.setAttribute(m,l.getAttribute(m));return l.replaceWith(p),new U(m=>{p.onload=()=>m.complete()})}else return p.textContent=l.textContent,l.replaceWith(p),k})).subscribe(),P(i,a).pipe(rr(e)).subscribe(({url:l,offset:p})=>{l.hash&&!p?No(l.hash):window.scrollTo(0,(p==null?void 0:p.y)||0)}),r.pipe(Wr(i),He(250),J("offset")).subscribe(({offset:l})=>{history.replaceState(l,"")}),P(i,a).pipe(Ne(2,1),A(([l,p])=>l.url.pathname===p.url.pathname),d(([,l])=>l)).subscribe(({offset:l})=>{window.scrollTo(0,(l==null?void 0:l.y)||0)})}var $i=Je(rn());function Ii(e,t){let r=new RegExp(e.separator,"img"),n=(o,i,a)=>`${i}${a}`;return o=>{o=o.replace(/[\s*+\-:~^]+/g," ").trim();let i=new RegExp(`(^|${e.separator})(${o.replace(/[|\\{}()[\]^$+*?.-]/g,"\\$&").replace(r,"|")})`,"img");return a=>(t?(0,$i.default)(a):a).replace(i,n).replace(/<\/mark>(\s+)]*>/img,"$1")}}function ji({document$:e}){var a;let t=ce(),r=t.version.staticVersions?C(t.version.staticVersions):Ge(new URL((a=t.version.versionPath)!=null?a:"../versions.json",t.base)),n=new URL("..",t.base),o=c=>new URL(c,n).toString().replace(/\/*$/,""),i=r.pipe(d(c=>{let s=t.base.toString().replace(/\/*$/,"");return c.find(({version:f,aliases:u})=>o(f)===s||u.find(l=>o(l)===s))||c[0]}));r.pipe(d(c=>new Map(c.map(s=>[`${new URL(`../${s.version}/`,t.base)}`,s]))),_(c=>x(document.body,"click").pipe(A(s=>!s.metaKey&&!s.ctrlKey),me(i),_(([s,f])=>{if(s.target instanceof Element){let u=s.target.closest("a");if(u&&!u.target&&c.has(u.href)){let l=u.href;return!s.target.closest(".md-version")&&c.get(l)===f?k:(s.preventDefault(),C(l))}}return k}),_(s=>{let{version:f}=c.get(s);return hr(new URL(s)).pipe(d(u=>{let p=Oe().href.replace(t.base,"");return u.includes(p.split("#")[0])?new URL(`../${f}/${p}`,t.base):new URL(s)}))})))).subscribe(c=>lr(c)),G([r,i]).subscribe(([c,s])=>{B(".md-header__topic").appendChild(oi(c,s))}),e.pipe(_(()=>i)).subscribe(c=>{var f;let s=__md_get("__outdated",sessionStorage);if(s===null){let u=((f=t.version)==null?void 0:f.default)||"latest";s=!c.aliases.includes(u),__md_set("__outdated",s,sessionStorage)}if(s)for(let u of ee("outdated"))u.hidden=!1})}function Fi(e,{location$:t}){let r={lang:[],separator:"\\s+"};return G([t.pipe(z(Oe()),A(n=>!!n.searchParams.get("h")))]).pipe(d(([n])=>Ii(r,!0)(n.searchParams.get("h"))),d(n=>{var a;let o=new Map,i=document.createNodeIterator(e,NodeFilter.SHOW_TEXT);for(let c=i.nextNode();c;c=i.nextNode())if((a=c.parentElement)!=null&&a.offsetHeight){let s=c.textContent,f=n(s);f.length>s.length&&o.set(c,f)}for(let[c,s]of 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r=`https://api.github.com/repos/${e}/${t}`;return Ir(Ge(`${r}/releases/latest`).pipe(le(()=>k),d(n=>({version:n.tag_name})),De({})),Ge(r).pipe(le(()=>k),d(n=>({stars:n.stargazers_count,forks:n.forks_count})),De({}))).pipe(d(([n,o])=>V(V({},n),o)))}else{let r=`https://api.github.com/users/${e}`;return Ge(r).pipe(d(n=>({repositories:n.public_repos})),De({}))}}function Vi(e,t){let r=`https://${e}/api/v4/projects/${encodeURIComponent(t)}`;return Ge(r).pipe(le(()=>k),d(({star_count:n,forks_count:o})=>({stars:n,forks:o})),De({}))}function Ni(e){let[t]=e.match(/(git(?:hub|lab))/i)||[];switch(t.toLowerCase()){case"github":let[,r,n]=e.match(/^.+github\.com\/([^/]+)\/?([^/]+)?/i);return Ui(r,n);case"gitlab":let[,o,i]=e.match(/^.+?([^/]*gitlab[^/]+)\/(.+?)\/?$/i);return Vi(o,i);default:return k}}var Ws;function zs(e){return Ws||(Ws=I(()=>{let t=__md_get("__source",sessionStorage);if(t)return C(t);if(ee("consent").length){let n=__md_get("__consent");if(!(n&&n.github))return k}return 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t=this.parentNode;if(t){e.length===0&&t.removeChild(this);for(let r=e.length-1;r>=0;r--){let n=e[r];typeof n!="object"?n=document.createTextNode(n):n.parentNode&&n.parentNode.removeChild(n),r?t.insertBefore(this.previousSibling,n):t.replaceChild(n,this)}}}));document.documentElement.classList.remove("no-js");document.documentElement.classList.add("js");var nt=So(),vr=jo(),rt=Do(),un=Io(),ge=Jo(),gr=Yr("(min-width: 960px)"),Gi=Yr("(min-width: 1220px)"),Ji=Wo(),Gs=ce(),pn=new L;ki({alert$:pn});Z("navigation.instant")&&Pi({document$:nt,location$:vr,viewport$:ge});var Yi;((Yi=Gs.version)==null?void 0:Yi.provider)==="mike"&&ji({document$:nt});P(vr,rt).pipe(ke(125)).subscribe(()=>{Ye("drawer",!1),Ye("search",!1)});un.pipe(A(({mode:e})=>e==="global")).subscribe(e=>{switch(e.type){case"p":case",":let t=ie("[href][rel=prev]");typeof t!="undefined"&&t.click();break;case"n":case".":let r=ie("[href][rel=next]");typeof r!="undefined"&&r.click();break}});qi({document$:nt,tablet$:gr});Ki({document$:nt});Bi({viewport$:ge,tablet$:gr});var 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Command-line Interface

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Building design

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To run Topwrap, use:

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python -m fpga_topwrap build --design project.yml
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Where project.yml should be your file with description of the top module.

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You can specify a directory to be scanned for additional sources:

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python -m fpga_topwrap build --sources src --design project.yml
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To implement the design for a specific FPGA chip, provide the part name:

+
python -m fpga_topwrap build --sources src --design project.yml --part 'xc7z020clg400-3'
+
+
+

Connect Topwrap to Pipeline Manager

+

If you want to use Pipeline Manager as a UI for creating block design, you need to:

+
    +

  1. Build and run Pipeline Manager server application.

    2. +
+
./build_server.sh
+cd kenning-pipeline-manager
+./run
+
+
+
    +

  1. Run Topwrap’s client application, that will connect to a running Pipeline Manager server app.

    2. +
+
python -m fpga_topwrap kpm_client [-h ip_addr] [-p port] FILES
+
+
+

Topwrap will then try to connect to the server running on ip_addr:port and send a specification generated from FILES, which should be IP core description yamls.

+

If -h or -p options are not specified, ip address 127.0.0.1 and port 9000 will be chosen by default.

+

Generating IP core description YAMLs

+

You can also use Topwrap to generate ip core description yamls from HDL sources, +that can be later used in your project.yml:

+
python -m fpga_topwrap parse HDL_FILES
+
+
+

In HDL source files, ports that belong to the same interface (e.g. wishbone or AXI), +have often a common prefix, which corresponds to the interface name. If such naming +convention is followed in the HDL sources, Topwrap can also divide ports into user-specified +interfaces, or automatically deduce interfaces names when generating yaml file:

+
python -m fpga_topwrap parse --iface wishbone --iface s_axi HDL_FILES
+
+python -m fpga_topwrap parse --iface-deduce HDL_FILES
+
+
+

To get help, use:

+
python -m fpga_topwrap [build|kpm_client|parse] --help
+
+
+ + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/description_files.html b/description_files.html new file mode 100644 index 00000000..15200c00 --- /dev/null +++ b/description_files.html @@ -0,0 +1,994 @@ + + + + + + + + + + + + + + + + Description files - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Description files

+

Design Description

+

To create a complete, fully synthesizable design, a proper design file is needed. +It’s used to specify IP cores, set their parameters’ values, describe hierarchies for the project, +connect the IPs and hierarchies, and pick external ports (those which will be connected to physical I/O).

+

You can see example design files in examples directory. The structure is as below:

+
ips:
+  # specify relations between IPs names in the design yaml
+  # and IP cores description yamls and modules
+  {ip_instance_name}:
+    file: {path_to_yaml_file_of_the_ip}
+    module: {name_of_the_HDL_module}
+  ...
+
+design:
+  hierarchies: # specify hierarchies designs
+    {hierarchy_name_1}:
+      design:
+        parameters:
+          ...
+        ports: # ports connections internal to this hierarchy
+          ...
+        interfaces: # interfaces connections internal to this hierarchy
+          ...
+        {nested_hierarchy_name}:
+          ...
+      external:
+        # external ports and/or interfaces of this hierarchy; these can be
+        # referenced in the upper-level `ports`, `interfaces` or `external` section
+        ...
+    {hierarchy_name_2}:
+      ...
+  
+  parameters: # specify IPs parameter values to be overridden
+    {ip_instance_name}:
+      {param_name} : {param_value}
+      ...
+
+  ports:
+    # specify incoming ports connections of an IP named `ip1_name`
+    {ip1_name}:
+      {port1_name} : [{ip2_name}, {port2_name}]
+      ...
+    # specify incoming ports connections of a hierarchy named `hier_name`
+    {hier_name}:
+      {port1_name} : [{ip_name}, {port2_name}]
+      ...
+    # specify external ports connections
+    {ip_instance_name}:
+      {port_name} : ext_port_name
+    ...
+
+  interfaces:
+    # specify incoming interfaces connections of `ip1_name` IP
+    {ip1_name}:
+      {iface1_name} : [{ip2_name}, {iface2_name}]
+      ...
+    # specify incoming interfaces connections of `hier_name` hierarchy
+    {hier_name}:
+      {iface1_name} : [{ip_name}, {iface2_name}]
+      ...
+    # specify external interfaces connections
+    {ip_instance_name}:
+      {iface_name} : ext_iface_name
+    ...
+
+external: # specify names of external ports and interfaces of the top module
+  ports:
+    out:
+      - {ext_port_name}
+    inout:
+      - {ext_port_name}
+  interfaces:
+    in:
+      - {ext_iface_name}
+
+
+

In order for an IP to be present in the generated design, it must be specified in ports or interfaces sections as a key. This means that even if it has no incoming connections from any other IP or hierarchy, the ports or interfaces sections must contain ip_name: {} entry.

+

The design description yaml format allows creating hierarchical designs. In order to create a hierarchy, it suffices to add its name as a key in the design section and describe the hierarchy design “recursively” by using the same keys and values (ports, parameters etc.) as in the top-level design (see above). Hierarchies can be nested recursively, which means that you can create a hierarchy inside another one.

+

Note that IPs and hierarchies names cannot be duplicated on the same hierarchy level. For example, the design section cannot contain two identical keys, but it’s correct to have ip_name key in this section and ip_name in the design section of some hierarchy.

+

IP description files

+

Every IP wrapped by Topwrap needs a description file in YAML format.

+

The ports of an IP should be placed in global signals node, followed by the direction of in, out or inout. +Here’s an example description of ports of Clock Crossing IP:

+
# file: clock_crossing.yaml
+signals:
+    in:
+        - clkA
+        - A
+        - clkB
+    out:
+        - B
+
+
+

The previous example is enough to make use of any IP. However, in order to benefit from connecting whole interfaces at once, ports must belong to a named interface like in this example:

+
#file: axis_width_converter.yaml
+s_axis:
+    interface: AXIStream
+    mode: slave
+    signals:
+        in:
+            TDATA: [s_axis_tdata, 63, 0]
+            TKEEP: [s_axis_tkeep, 7, 0]
+            TVALID: s_axis_tvalid
+            TLAST: s_axis_tlast
+            TID: [s_axis_tid, 7, 0]
+            TDEST: [s_axis_tdest, 7, 0]
+            TUSER: s_axis_tuser
+        out:
+            TREADY: s_axis_tready
+
+m_axis:
+    interface: AXIStream
+    mode: master
+    signals:
+        in:
+            TREADY: m_axis_tready
+        out:
+            TDATA: [m_axis_tdata, 31, 0]
+            TKEEP: [m_axis_tkeep, 3, 0]
+            TVALID: m_axis_tvalid
+            TLAST: m_axis_tlast
+            TID: [m_axis_tid, 7, 0]
+            TDEST: [m_axis_tdest, 7, 0]
+            TUSER: m_axis_tuser
+signals: # These ports don't belong to any interface
+    in:
+        - clk
+        - rst
+
+
+

Names s_axis and m_axis will be used to group the selected ports. +Each signal in an interface has a name which must match with the signal it’s supposed to be connected to, for example TDATA: port_name will be connected to TDATA: other_port_name.

+

Note that you don’t have to write IP core description yamls by hand. You can use Topwrap’s parse command (see Generating IP core description YAMLs) in order to generate yamls from HDL source files and then adjust the yaml to your needs.

+

Port widths

+

The width of every port defaults to 1. +You can specify the width using this notation:

+
s_axis:
+    interface: AXIStream
+    mode: slave
+    signals:
+        in:
+            TDATA: [s_axis_tdata, 63, 0] # 64 bits
+            ...
+            TVALID: s_axis_tvalid # defaults to 1 bit
+
+signals:
+    in:
+        - [gpio_io_i, 31, 0] # 32 bits
+
+
+

Parameterization

+

Port widths don’t have to be hardcoded - you can use parameters to describe an IP core in a generic way. +Values specified in IP core yamls can be overriden in a design description file (see Design Description).

+
parameters:
+    DATA_WIDTH: 8
+    KEEP_WIDTH: (DATA_WIDTH+7)/8
+    ID_WIDTH: 8
+    DEST_WIDTH: 8
+    USER_WIDTH: 1
+
+s_axis:
+    interface: AXI4Stream
+    mode: slave
+    signals:
+        in:
+            TDATA: [s_axis_tdata, DATA_WIDTH-1, 0]
+            TKEEP: [s_axis_tkeep, KEEP_WIDTH-1, 0]
+            ...
+            TID: [s_axis_tid, ID_WIDTH-1, 0]
+            TDEST: [s_axis_tdest, DEST_WIDTH-1, 0]
+            TUSER: [s_axis_tuser, USER_WIDTH-1, 0]
+
+
+

Parameters values can be integers or math expressions, which are evaluated using numexpr.evaluate().

+

Port slicing

+

You can also slice a port, to use some bits of the port as a signal that belongs to an interface. +The example below means:

+

Port m_axi_bid of the IP core is 36 bits wide. Use bits 23..12 as the BID signal of AXI master named m_axi_1

+
m_axi_1:
+    interface: AXI
+    mode: master
+    signals:
+        in:
+            BID: [m_axi_bid, 35, 0, 23, 12]
+
+
+

Interface Description files

+

Topwrap can use predefined interfaces which are descibed in YAML-formatted files. +The interfaces you use don’t have to be predefined, but it’s possible to perform checks +on whether all the mandatory signals are connected, when you use an interface definition.

+

You can see an example file below:

+
name: AXI4Stream
+port_prefix: AXIS
+signals:
+    required:
+        - TVALID
+        - TDATA
+        - TLAST
+        - TREADY
+    optional:
+        - TID
+        - TDEST
+        - TKEEP
+        - TSTRB
+        - TUSER
+
+
+

The name of an interface has to be unique. We also specify a prefix which will be used as a shortened identifier.

+ + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/examples.html b/developers_guide/examples.html new file mode 100644 index 00000000..4fe47d47 --- /dev/null +++ b/developers_guide/examples.html @@ -0,0 +1,735 @@ + + + + + + + + + + + + + + + + Examples - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Examples

+
+

Note

+

Basic usage of examples is explained in the Getting started section.

+
+

Examples provided with this project should cover from very simple designs to complex fully synthesizable cores. +They should be sorted by increasing complexity and number of used features, e.g:

+
    +

  • 101: minimal base design

    • +

  • 102: introduce user to parameters

    • +

  • 103: introduce user to slicing

    • +

  • 104: introduce user to interfaces

    • +

  • 105: etc.

    • +
+

Developers are encouraged to create/add new examples in the same spirit. +Simple examples are used to teach how to use this tool and demonstrate its features. +Real-world use cases are also welcome to prove that the implementation is mature enough to handle practical designs.

+
+

Note

+

The goal of this project is not to create a library of cores and/or their functional validation. This need is fulfilled by projects like FuseSoC, SVUnit, etc.

+
+ + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/setup.html b/developers_guide/setup.html new file mode 100644 index 00000000..a1dd213d --- /dev/null +++ b/developers_guide/setup.html @@ -0,0 +1,722 @@ + + + + + + + + + + + + + + + + Setup - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Setup

+

It is recommended for developers to keep code style and frequently run tests. +In order to setup the developer’s environment install python packages from requirements.dev.txt, which shall include nox and pre-commit:

+
python -m venv venv
+source venv/bin/activate
+pip install -r requirements.dev.txt
+
+
+ + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/style.html b/developers_guide/style.html new file mode 100644 index 00000000..b516f3f5 --- /dev/null +++ b/developers_guide/style.html @@ -0,0 +1,805 @@ + + + + + + + + + + + + + + + + Code style - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Code style

+

Automatic formatting and linting of the code can be performed with either nox or pre-commit.

+

Lint with nox

+

After successful setup, nox sessions can be executed to perform lint checks:

+
nox -s isort black flake8
+
+
+
+

Note

+

pre-commit can also be run from nox:

+
nox -s pre_commit
+
+
+
+

Lint with pre-commit

+

Alternatively, you can use pre-commit to perform the same job. +Pre-commit hooks need to be installed:

+
pre-commit install
+
+
+

Now, each use of git commit in the shell will trigger actions defined in the .pre-commit-config.yaml file. +Pre-commit can be easily disabled with a similar command:

+
pre-commit uninstall
+
+
+

If you wish to run pre-commit asynchronously, then use:

+
pre-commit run --all-files
+
+
+
+

Note

+

pre-commit by default also runs nox with isort,flake8 and black sessions:

+
+

Tools

+

Tools used in project for maintaing code style:

+ + + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/tests.html b/developers_guide/tests.html new file mode 100644 index 00000000..5eb458fb --- /dev/null +++ b/developers_guide/tests.html @@ -0,0 +1,756 @@ + + + + + + + + + + + + + + + + Tests - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + + + + + + +

Tests

+

Topwrap functionality is validated with tests, leveraging the pytest library.

+

Test execution

+

Tests are located in the tests directory. +All tests can be run with nox by specifying the tests session:

+
nox -s tests
+
+
+

Tests can also be launched without nox by executing:

+
pytest
+
+
+ + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
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+ + + + + + + + \ No newline at end of file diff --git a/elaboratable_wrapper.html b/elaboratable_wrapper.html new file mode 100644 index 00000000..42090e78 --- /dev/null +++ b/elaboratable_wrapper.html @@ -0,0 +1,718 @@ + + + + + + + + + + + + + + + + ElaboratableWrapper class - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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ElaboratableWrapper class

+

ElaboratableWrapper encapsulates an Amaranth’s Elaboratable and exposes an interface compatible with other wrappers which allows making connections with them. +Supplied elaboratable must contain a signature property and a conforming interface as specified by Amaranth docs. +Ports’ directionality, their names and widths are inferred from it.

+ + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/fpga-topwrap.pdf b/fpga-topwrap.pdf new file mode 100644 index 00000000..0b245eed Binary files /dev/null and b/fpga-topwrap.pdf differ diff --git a/fusesoc.html b/fusesoc.html new file mode 100644 index 00000000..52ed8fdb --- /dev/null +++ b/fusesoc.html @@ -0,0 +1,779 @@ + + + + + + + + + + + + + + + + FuseSoC - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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FuseSoC

+

Toprwap uses FuseSoC to automate project generation and build process.

+

A Core file is needed in order to generate a project. The file can be generated from a template using FuseSocBuilder class. The Core file contains information about source files and synthesis tools.

+

Core file template

+

A template for the core file is bundled with Topwrap (templates/core.yaml.j2). +You may need to edit the file to change the backend tool, set additional Hooks and change the FPGA part name or other parameters. +By default, FuseSocBuilder searches for the template file in the directory you work in, so you should first copy the template into the project’s location.

+

Using the FuseSocBuilder

+

Here’s an example of how to generate a simple project:

+
from fpga_topwrap.fuse_helper import FuseSocBuilder
+fuse = FuseSocBuilder()
+
+# add source of the IPs used in the project
+fuse.add_source('DMATop.v', 'verilogSource')
+
+# add source of the top file
+fuse.add_source('top.v', 'verilogSource')
+
+# specify the names of the Core file and the directory where sources are stored
+# generate the project
+fuse.build('build/top.core', 'sources')
+
+
+

Now you can run FuseSoC to generate bitstream and program FPGA:

+
fusesoc --cores-root build run project_1
+
+
+

This requires having the suitable backend tool in your PATH (Vivado, for example).

+ + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
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+ + + + + + + + \ No newline at end of file diff --git a/future_enhancements.html b/future_enhancements.html new file mode 100644 index 00000000..7a53acf3 --- /dev/null +++ b/future_enhancements.html @@ -0,0 +1,786 @@ + + + + + + + + + + + + + + + + Future enhancements - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Future enhancements

+

Creating hierarchical block designs

+

Currently, Topwrap supports only creating “flat” designs; one can add IP cores and create connections between them, but there is no way of organizing specific parts of the design into hierarchies. Having such a facility implemented would make it easier to create complex designs.

+

Moreover, this feature is closely related to subgraphs, which will be supported shortly in Pipeline Manager. In the future, we’d also like to provide a possibility to create hierarchical designs in the Pipeline Manager, which would be a huge improvement in terms of organizing complex designs.

+

Bus management

+

Another goal we’d like to achieve is to enable users to create full-featured designs with processors by providing proper support for bus management. +This should include features such as:

+
    +

  • ability to specify the address of a peripheral device on the bus

    • +

  • support for the most popular buses or the ones that we use (AXI, wishbone, Tile-link)

    • +
+

This will require writing or creating bus arbiters (round-robin, crossbar) and providing a mechanism for connecting master(s) and slave(s) together. +As a result, the user should be able to create complex SoC with Topwrap.

+

Improve the process of recreating a design from a YAML file

+

One of the main features that are supported by Topwrap and Pipeline Manager is exporting and importing user-created design to or from a design description YAML. However, during these conversions, information about the positions of user-added nodes is not preserved. This is cumbersome in the case of complicated designs since the imported nodes cannot be placed in the optimal positions.

+

Therefore, one of our objectives is to provide a convenient way of creating and restoring user-created designs in Pipeline Manager, so that the user doesn’t have to worry about node positions when importing a design to Pipeline Manager.

+

Support for parsing SystemVerilog sources

+

Information about IP cores is stored in IP core description YAMLs. These files can be generated automatically from HDL source files - currently Verilog and VHDL are supported. Our goal is to provide the possiblity of generating such YAMLs from SystemVerilog too.

+

Provide a way to parse HDL sources from the Pipeline Manager level

+

Another issue related to HDL parsing is that the user has to manually parse HDL sources to obtain the IP core description YAMLs. Then the files need to be provided as command-line parameters when launching the Topwrap Pipeline Manager client application. Therefore, we aim to provide a way of parsing HDL files and including them in the editor directly from the Pipeline Manager level.

+

Ability to produce top-level wrappers in VHDL

+

Topwrap now uses Amaranth to generate top-level design in Verilog. We would also like to add the ability to produce such designs in VHDL.

+ + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/genindex.html b/genindex.html new file mode 100644 index 00000000..4af3d779 --- /dev/null +++ b/genindex.html @@ -0,0 +1,670 @@ + + + + + + + + + + + + + + + + None - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + Last update: + 2024-01-10 + + +
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+ +
+ Copyright © Antmicro, 2024. + +
+ + ecc30b8f + @ main + +
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+ + + + + + + + + + \ No newline at end of file diff --git a/getting_started.html b/getting_started.html new file mode 100644 index 00000000..42a735f5 --- /dev/null +++ b/getting_started.html @@ -0,0 +1,920 @@ + + + + + + + + + + + + + + + + Getting started - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Getting started

+

Installation

+
    +

  1. Install required system packages:

    +
    apt install -y git g++ make python3 python3-pip antlr4 libantlr4-runtime-dev yosys
+
    +
    +
    2. +

  2. It is highly recommended to run the following steps in a Python virtual environment (e.g. venv).

    3. +

  3. Install base requirements:

    +
    pip3 install -r requirements.txt
+
    +
    +
    4. +

  4. Build the Topwrap package:

    +
    python3 setup.py build
+
    +
    +
    5. +

  5. Install the Topwrap package:

    +
    python3 setup.py install
+
    +
    +
    6. +
+

Example usage

+

This section demonstrates the basic usage of Topwrap to generate IP wrappers and a top module.

+
    +

  1. Create IPWrapper objects for every IP Core you want to use:

    2. +
+
ips:
+  dma:
+    file: ips/DMATop.yaml
+    module: DMATop
+  disp:
+    file: ips/axi_dispctrl_v1_0.yaml
+    module: axi_dispctrl_v1_0
+
+
+

file and module are mandatory fields providing the IP description and the name of the HDL module. +You can optionally set parameter values for IP cores:

+
axi_interconnect0:
+  file: axi_interconnect.yaml
+  module: axi_interconnect
+  parameters:
+    S_COUNT: 1
+    M_COUNT: 3
+    ADDR_WIDTH: 32
+    DATA_WIDTH: 32
+    ID_WIDTH: 12
+    M_BASE_ADDR: 0x43c2000043c1000043c00000
+    M_ADDR_WIDTH:
+        value: 0x100000001000000010
+        width: 96
+
+
+
    +

  1. Connect desired ports of the IP cores:

    2. +
+
ports:
+  dma:
+    clock: [some_other_ip, clk_out]
+    reset: [reset_core, reset0]
+  axi_interconnect0:
+    clk: [some_other_ip, clk_out]
+
+
+
    +

  1. Connect desired interfaces of the IP cores:

    2. +
+
interfaces:
+  dma:
+    s_axi: [axi_interconnect0, m_axi_0]
+  axi_interconnect0:
+    m_axi: [some_other_ip, 's_axi']
+
+
+
    +

  1. Specify external ports or interfaces of the top module and connect them with chosen IP cores’ ports or interfaces:

    2. +
+
ports:
+  dma:
+    io_irq_readerDone: readerDone
+    io_irq_writerDone: writerDone
+
+...
+
+external:
+  ports:
+    out:
+    - readerDone
+    - writerDone
+  interfaces:
+    ...
+
+
+
    +

  1. Create a Core file template for FuseSoC, or use a default one bundled with Topwrap.

    2. +
+

You may want to modify the file to add dependencies, source files, or change the target board. +The file should be named core.yaml.j2. You can find an example template in examples/hdmi directory of the project. +If you don’t create any template a default template bundled with Topwrap will be used (stored in templates directory).

+
    +

  1. Place any additional source files in a directory, which we will be calling sources here.

    2. +

  2. Run Topwrap:

    +
    python -m fpga_topwrap build --design project.yml --sources sources
+
    +
    +
    3. +
+

Example PWM design

+

There’s an example setup in examples/pwm.

+

In order to generate the top module, run:

+
make generate
+
+
+

In order to generate bitstream, add Vivado to your path and run:

+
make
+
+
+

The FPGA design utilizes an AXI-mapped PWM IP Core. +You can access its registers starting from address 0x4000000 (that’s the base address of AXI_GP0 on ZYNQ). +Each IP Core used in the project is declared in ips section in project.yml file. +ports section allows to connect individual ports of IP Cores, and interfaces is used analogously for connecting whole interfaces. +Finally, you can specify which ports will be used as external I/O in external section.

+

To connect the I/O signals to specific FPGA pins, you need proper mappings in a constraints file. See zynq.xdc used in the setup and modify it accordingly.

+_images/pwm.png +

Example HDMI design

+

There’s an example setup stored in examples/hdmi.

+

You can generate bitstream for desired target:

+
+
    +

  • Snickerdoodle Black:

    +
    make snickerdoodle
+
    +
    +
    • +

  • Zynq Video Board:

    +
    make zvb
+
    +
    +
    • +
+
+

If you wish to generate HDL sources without running Vivado, you can use:

+
make generate
+
+
+

You can find more information in README of the example setup.

+ + +
+
+ + + Last update: + 2024-01-10 + + +
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+ + + + + + + + \ No newline at end of file diff --git a/helpers.html b/helpers.html new file mode 100644 index 00000000..543a2c14 --- /dev/null +++ b/helpers.html @@ -0,0 +1,715 @@ + + + + + + + + + + + + + + + + Helpers - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Helpers

+ + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/index.html b/index.html new file mode 100644 index 00000000..788e9141 --- /dev/null +++ b/index.html @@ -0,0 +1,755 @@ + + + + + + + + + + + + + + + + FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Welcome to Topwrap!

+
+

Documentation

+ +
+
+

Developer's Guide

+ +
+
+

Future enhancements

+ +
+ + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
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+ +
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+ + + + + + + + \ No newline at end of file diff --git a/introduction.html b/introduction.html new file mode 100644 index 00000000..ef066cbb --- /dev/null +++ b/introduction.html @@ -0,0 +1,759 @@ + + + + + + + + + + + + + + + + Introduction - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Introduction

+

Topwrap is a tool for generating HDL wrappers for simple blocks as well as digital systems and can be used for creating complex SoCs from single blocks contained in wrappers.

+

Wrappers

+

These wrappers standardize names of ports that belong to an interfaces (e.g. UART, AXI etc.)

+_images/wrapper.png +

Top module

+

Top modules connect IPs and/or Wrappers by either ports` names or interfaces` names to ease connecting multi-wire interfaces without the need to connect each wire separately.

+_images/ipconnect.png + + +
+
+ + + Last update: + 2024-01-10 + + +
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+ + + + + + + + \ No newline at end of file diff --git a/ipconnect.html b/ipconnect.html new file mode 100644 index 00000000..9545275f --- /dev/null +++ b/ipconnect.html @@ -0,0 +1,729 @@ + + + + + + + + + + + + + + + + IPConnect class - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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IPConnect class

+

Topwrap uses IPConnect to encapsulate IP Cores in a module, and connect their wires and interfaces.

+

After the object is created, IPs can be added using add_ip method:

+
# create a wrapper for an IP
+dma := IPWrapper('DMATop.yaml', ip_name='DMATop'),
+
+ipc = IPConnect()
+ip.add_ip(dma)
+
+# add other IPs
+
+
+

IPs are connected using make_connections function. +Ports and interfaces can be set as external input/output/inout with make_external_ports_interfaces and retrieved with get_ports. +For a wider example of using the IPConnect see Getting Started

+ + +
+
+ + + Last update: + 2024-01-10 + + +
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+ +
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+ + + + + + + + \ No newline at end of file diff --git a/ipwrapper.html b/ipwrapper.html new file mode 100644 index 00000000..a7fe2548 --- /dev/null +++ b/ipwrapper.html @@ -0,0 +1,717 @@ + + + + + + + + + + + + + + + + IPWrapper class - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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IPWrapper class

+

IPWrapper is the main class used to instantiate an IP Core and generate HDL wrapper. +It’s used to standardize names of ports that belong to interfaces to ease connecting multiple IPs.

+ + +
+
+ + + Last update: + 2024-01-10 + + +
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+ + + + + + + + \ No newline at end of file diff --git a/objects.inv b/objects.inv new file mode 100644 index 00000000..8495f2ed Binary files /dev/null and b/objects.inv differ diff --git a/pipeline_manager.html b/pipeline_manager.html new file mode 100644 index 00000000..674c0ee3 --- /dev/null +++ b/pipeline_manager.html @@ -0,0 +1,861 @@ + + + + + + + + + + + + + + + + Kenning Pipeline Manager - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Kenning Pipeline Manager

+

Topwrap can make use of Kenning Pipeline Manager to visualize the process of creating block design.

+

Run Topwrap with Pipeline Manager

+
    +

  1. Build and run Pipeline Manager server

    +

    In order to start creating block design in Pipeline Manager, you need to first build and run a server application - here is a brief instruction on how to achieve this (the process of building and installation of Pipeline Manager is described in detail in its documentation):

    +
    ./build_server.sh
+cd kenning-pipeline-manager
+./run
+
    +
    +

    After executing the above-mentioned commands, the Pipeline Manager server is waiting for an external application (i.e. Topwrap) to connect on 127.0.0.1:9000 and you can connect to the web GUI frontend in your browser on http://127.0.0.1:5000.

    +
    2. +

  2. Establish connection with Topwrap

    +

    Once the Pipeline Manager server is running, you can now launch Topwrap’s client application in order to connect to the server. You need to specify:

    +
      +

    • IP address (127.0.0.1 is default)

      • +

    • listening port (9000 is default)

      • +

    • yamls describing IP cores, that will be used in the block design

      • +
    +

    An example command, that runs Topwrap’s client, may look like this:

    +
    python -m fpga_topwrap kpm_client -h 127.0.0.1 -p 9000 \
+    fpga_topwrap/ips/axi/axi_axil_adapter.yaml \
+    examples/pwm/ipcores/{litex_pwm.yml,ps7.yaml}
+
    +
    +
    3. +

  3. Create block design in Pipeline Manager

    +

    Upon successful connection to a Pipeline Manager server, Topwrap will generate and send to the server a specification describing the structure of previously selected IP cores. After that, you are free to create a custom block design by means of:

    +
      +

    • adding IP core instances to the block design. Each Pipeline Manager’s node has delete and rename options, which make it possible to remove the selected node and change its name respectively. This means that you can create multiple instances of the same IP core.

      • +

    • adjusting IP cores’ parameters values. Each node may have input boxes in which you can enter parameters’ values (default parameter values are added while adding an IP core to the block design):

      • +
    +_images/node_parameters.png +
      +

    • connecting IP cores’ ports and interfaces. Only connections between ports or interfaces of matching types are allowed. This is automatically checked by Pipeline Manager, as the types of nodes’ ports and interfaces are contained in the loaded specification, so Pipeline Manager will prevent you from connecting non-matching interfaces (e.g. AXI4 with AXI4Lite or a port with an interface). A green line will be displayed if a connection is possible to create, or a red line elsewhere:

      • +
    +_images/invalid_connection.png +
      +

    • specifying external ports or interfaces in the top module. This can be done by adding External Input, External Output or External Inout metanodes and creating connections between them and chosen ports or interfaces. Note that you should adjust the name of the external port or interface in a textbox inside selected metanode. In the example below, output port pwm of litex_pwm_top IP core will be made external in the generated top module and the external port name will be set to ext_pwm:

      • +
    +_images/external_port.png +

    Note, that you don’t always have to create a new block design by hand - you can use a design import feature to load an existing block design from a description in Topwrap’s yaml format.

    +

    An example block design in Pipeline Manager for the PWM project may look like this:

    +_images/pwm_design.png +
    4. +
+

Pipeline Manager features

+

While creating a custom block design, you can make use of the following Pipeline Manager’s features:

+
    +

  • export (save) design to a file

    • +

  • import (load) design from a file

    • +

  • validate design

    • +

  • build design

    • +
+

Export design to yaml description file

+

Created block design can be saved to a design description file in yaml format, using Pipeline Manager’s Save file option. The design description file name will be generated automatically based on current timestamp.

+

Import design from yaml description file

+

Topwrap also supports conversion in the opposite way - block design in Pipeline Manager can be generated from a yaml design description file using Load file feature.

+

Design validation

+

Pipeline Manager is capable of performing some basic checks at runtime such as interface type checking while creating a connection. However you can also run more complex tests by using Pipeline Manager’s Validate option. Topwrap will then respond with a validity confirmation or error messages. The rules you need to follow in order to keep your block design valid are:

+
    +

  • multiple IP cores with the same name are not allowed (except from external metanodes).

    • +

  • parameters values can be integers of different bases (e.g. 0x28, 40 or 0b101000) or arithmetic expressions, that are later evaluated using numexpr.evaluate() function (e.g. (AXI_DATA_WIDTH+1)/4 is a valid parameter value assuming that a parameter named AXI_DATA_WIDTH exists in the same IP core). You can also write a parameter value in a Verilog format (e.g. 8'b00011111 or 8'h1F) - in such case it will be interpreted as a fixed-width bit vector.

    • +

  • a single port or interface cannot be external and connected to another IP core at the same time.

    • +

  • connections between two external metanodes are not allowed.

    • +

  • all the created external output or inout ports must have unique names. Only multiple input ports of IP cores can be driven be the same external signal.

    • +
+

Topwrap can also generate warnings if:

+
    +

  • some ports or interfaces remain unconnected.

    • +

  • multiple ports are connected to an External Input metanode with an empty External Name property. +If a block design validation returns a warning, it means that the block design can be successfully built, but it is recommended to follow the suggestion and resolve a particular issue.

    • +
+

Building design

+

Once the design has been created and tested for validity, you can build design using Run feature. If the design does not contain any errors, this will result in creating a top module, similarly when using Topwrap’s fpga_topwrap build command.

+ + +
+
+ + + Last update: + 2024-01-10 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
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+ + + + + + + + \ No newline at end of file diff --git a/searchindex.js b/searchindex.js new file mode 100644 index 00000000..c12b1327 --- /dev/null +++ b/searchindex.js @@ -0,0 +1 @@ +Search.setIndex({"titles": ["Command-line Interface", "Description files", "Examples", "Setup", "Code style", "Tests", "ElaboratableWrapper class", "FuseSoC", "Future enhancements", "Getting started", "Helpers", "Welcome to Topwrap!", "Introduction", "IPConnect class", "IPWrapper class", "Kenning Pipeline Manager", "Wrapper Port"], "terms": {"To": [0, 1, 9], "run": [0, 3, 4, 5, 7, 9, 11], "us": [0, 1, 2, 4, 8, 9, 11, 12, 13, 14, 15, 16], "python": [0, 3, 4, 9, 15], "m": [0, 3, 9, 15], "fpga_topwrap": [0, 7, 9, 15], "project": [0, 1, 2, 4, 7, 9, 15], "yml": [0, 9, 15], "where": [0, 7], "should": [0, 1, 2, 7, 8, 9, 15, 16], "your": [0, 1, 7, 9, 15], "file": [0, 4, 9, 11], "top": [0, 1, 7, 9, 11, 15], "modul": [0, 1, 9, 11, 13, 15], "you": [0, 1, 4, 7, 9, 15], "can": [0, 1, 4, 5, 7, 8, 9, 12, 13, 15], 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mode 100644 index 00000000..4a20bac3 --- /dev/null +++ b/wrapper_port.html @@ -0,0 +1,727 @@ + + + + + + + + + + + + + + + + Wrapper Port - FPGA Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Wrapper Port

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Class WrapperPort is an extension to Amaranth’s Signal. +It wraps a port, adding a new name and optionally slicing the signal. +It adds these attributes:

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WrapperPort.internal_name     # name of the port in internal source to be wrapped
+WrapperPort.direction         # DIR_FANIN, DIR_FANOUT or DIR_NONE
+WrapperPort.interface_name    # name of the group of ports (interface)
+WrapperPort.bounds            # range of bits that belong to the port
+                              # and range which is sliced from the port
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+

See Port slicing to know more about bounds.

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This is used in IPWrapper class implementation and there should be no need to use WrapperPort individually.

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