diff --git a/libcpuid/cpuid_main.c b/libcpuid/cpuid_main.c
index 2ae80be9..791e18dd 100644
--- a/libcpuid/cpuid_main.c
+++ b/libcpuid/cpuid_main.c
@@ -1448,9 +1448,10 @@ const char* cpu_purpose_str(cpu_purpose_t purpose)
 {
 	const struct { cpu_purpose_t purpose; const char* name; }
 	matchtable[] = {
-		{ PURPOSE_GENERAL,     "general"     },
-		{ PURPOSE_PERFORMANCE, "performance" },
-		{ PURPOSE_EFFICIENCY,  "efficiency"  },
+		{ PURPOSE_GENERAL,       "general"              },
+		{ PURPOSE_PERFORMANCE,   "performance"          },
+		{ PURPOSE_EFFICIENCY,    "efficiency"           },
+		{ PURPOSE_LP_EFFICIENCY, "low-power efficiency" },
 	};
 	unsigned i, n = COUNT_OF(matchtable);
 	if (n != NUM_CPU_PURPOSES) {
diff --git a/libcpuid/libcpuid.h b/libcpuid/libcpuid.h
index 037e29fc..1ef7e229 100644
--- a/libcpuid/libcpuid.h
+++ b/libcpuid/libcpuid.h
@@ -155,11 +155,12 @@ typedef enum {
  * @brief CPU purpose
  */
 typedef enum {
-	PURPOSE_GENERAL = 0,  /*!< general purpose CPU */
-	PURPOSE_PERFORMANCE,  /*!< performance CPU */
-	PURPOSE_EFFICIENCY,   /*!< efficiency CPU */
+	PURPOSE_GENERAL = 0,   /*!< general purpose CPU */
+	PURPOSE_PERFORMANCE,   /*!< performance CPU */
+	PURPOSE_EFFICIENCY,    /*!< efficiency CPU */
+	PURPOSE_LP_EFFICIENCY, /*!< low-power efficiency CPU */
 
-	NUM_CPU_PURPOSES,     /*!< Valid CPU purpose ids: 0..NUM_CPU_PURPOSES - 1 */
+	NUM_CPU_PURPOSES,      /*!< Valid CPU purpose ids: 0..NUM_CPU_PURPOSES - 1 */
 } cpu_purpose_t;
 #define NUM_CPU_PURPOSES NUM_CPU_PURPOSES
 
diff --git a/libcpuid/recog_intel.c b/libcpuid/recog_intel.c
index 3cf56138..ea39b156 100644
--- a/libcpuid/recog_intel.c
+++ b/libcpuid/recog_intel.c
@@ -1145,9 +1145,16 @@ cpu_purpose_t cpuid_identify_purpose_intel(struct cpu_raw_data_t* raw)
 	if (EXTRACTS_BIT(raw->basic_cpuid[0x7][EDX], 15) == 0x1) {
 		debugf(3, "Detected Intel CPU hybrid architecture\n");
 		switch (EXTRACTS_BITS(raw->basic_cpuid[0x1a][EAX], 31, 24)) {
-			case 0x20: /* Atom */ return PURPOSE_EFFICIENCY;
-			case 0x40: /* Core */ return PURPOSE_PERFORMANCE;
-			default:              return PURPOSE_GENERAL;
+			case 0x20: /* Atom */
+				/* Acccording to Ramyer M. from Intel, LP E-Cores do not have a L3 cache
+				   https://community.intel.com/t5/Processors/Detecting-LP-E-Cores-on-Meteor-Lake-in-software/m-p/1584555/highlight/true#M70732
+				   If sub-leaf 3 is set, it is an E-Cores.
+				*/
+				return (EXTRACTS_BITS(raw->intel_fn4[3][EAX], 31, 0)) ? PURPOSE_EFFICIENCY : PURPOSE_LP_EFFICIENCY;
+			case 0x40: /* Core */
+				return PURPOSE_PERFORMANCE;
+			default:
+				return PURPOSE_GENERAL;
 		}
 	}