evkbimxrt1050_sdram_init.jlinkscript

/*
 * Copyright 2017 NXP
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * o Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
 *
 * o Redistributions in binary form must reproduce the above copyright notice, this
 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
 *
 * o Neither the name of the copyright holder nor the names of its
 *   contributors may be used to endorse or promote products derived from this
 *   software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
void Load_Dcdc_Trim()
{
  unsigned int ocotp_base;  
  unsigned int dcdc_base;  
  unsigned int ocotp_fuse_bank0_base;  
  unsigned int reg;
  unsigned int index;
  unsigned int trim_value;
  unsigned int dcdc_trim_loaded;
  ocotp_base = 0x401F4000;
  ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
  dcdc_base = 0x40080000;
  dcdc_trim_loaded = 0;
  reg = MEM_ReadU32(ocotp_fuse_bank0_base + 0x90);
  if (reg & (1<<10))
  {
      trim_value = (reg & (0x1F << 11)) >> 11;
      reg = (MEM_ReadU32(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
      MEM_WriteU32(dcdc_base + 0x4, reg);
      dcdc_trim_loaded = 1;
  }
  // DCDC_VOLT_CHANG_EN
  reg = MEM_ReadU32(ocotp_fuse_bank0_base + 0x80);
  if (reg & (1<<30))
  {
    index = (reg & (3 << 28)) >> 28;
    if (index < 4)
    {
      reg = (MEM_ReadU32(dcdc_base + 0xC) & ~(0x1F)) | (0xF + index);
      MEM_WriteU32(dcdc_base + 0xC, reg);
      dcdc_trim_loaded = 1;
    }
  }
  if (dcdc_trim_loaded)
  {
      // delay 1ms for dcdc to get stable
      SYS_Sleep(1);
      JLINK_SYS_Report("DCDC trim value loaded.");
  }
}
 
void Clock_Init() 
{
    //
  MEM_WriteU32(0x400FC068,0xffffffff);
  MEM_WriteU32(0x400FC06C,0xffffffff);

  MEM_WriteU32(0x400FC070,0xffffffff);
  MEM_WriteU32(0x400FC074,0xffffffff);
  MEM_WriteU32(0x400FC078,0xffffffff);
  MEM_WriteU32(0x400FC07C,0xffffffff);
  MEM_WriteU32(0x400FC080,0xffffffff);
  MEM_WriteU32(0x400D8030,0x00002001); // CCM_ANALOG_PLL_SYS
  MEM_WriteU32(0x400D8100,0x001d0000);  // CCM_ANALOG_PFD_528
  MEM_WriteU32(0x400FC014,0x00010D40); // CCM_CBCDR
  JLINK_SYS_Report("Clock Init Done");
}
void SDRAM_WaitIpCmdDone(void) 
{
  unsigned int reg;
  do
  {
      reg = MEM_ReadU32(0x402F003C);
  }while((reg & 0x3) == 0);
  
  MEM_WriteU32(0x402F003C,0x00000003); // clear IPCMDERR and IPCMDDONE bits
}
void SDRAM_Init() {
  // Config IOMUX for SDRAM
  MEM_WriteU32(0x401F8014,0x00000000); // EMC_00
  MEM_WriteU32(0x401F8018,0x00000000); // EMC_01
  MEM_WriteU32(0x401F801C,0x00000000); // EMC_02
  MEM_WriteU32(0x401F8020,0x00000000); // EMC_03
  MEM_WriteU32(0x401F8024,0x00000000); // EMC_04
  MEM_WriteU32(0x401F8028,0x00000000); // EMC_05
  MEM_WriteU32(0x401F802C,0x00000000); // EMC_06
  MEM_WriteU32(0x401F8030,0x00000000); // EMC_07
  MEM_WriteU32(0x401F8034,0x00000000); // EMC_08
  MEM_WriteU32(0x401F8038,0x00000000); // EMC_09
  MEM_WriteU32(0x401F803C,0x00000000); // EMC_10
  MEM_WriteU32(0x401F8040,0x00000000); // EMC_11
  MEM_WriteU32(0x401F8044,0x00000000); // EMC_12
  MEM_WriteU32(0x401F8048,0x00000000); // EMC_13
  MEM_WriteU32(0x401F804C,0x00000000); // EMC_14
  MEM_WriteU32(0x401F8050,0x00000000); // EMC_15
  MEM_WriteU32(0x401F8054,0x00000000); // EMC_16
  MEM_WriteU32(0x401F8058,0x00000000); // EMC_17
  MEM_WriteU32(0x401F805C,0x00000000); // EMC_18
  MEM_WriteU32(0x401F8060,0x00000000); // EMC_19
  MEM_WriteU32(0x401F8064,0x00000000); // EMC_20
  MEM_WriteU32(0x401F8068,0x00000000); // EMC_21
  MEM_WriteU32(0x401F806C,0x00000000); // EMC_22
  MEM_WriteU32(0x401F8070,0x00000000); // EMC_23
  MEM_WriteU32(0x401F8074,0x00000000); // EMC_24
  MEM_WriteU32(0x401F8078,0x00000000); // EMC_25
  MEM_WriteU32(0x401F807C,0x00000000); // EMC_26
  MEM_WriteU32(0x401F8080,0x00000000); // EMC_27
  MEM_WriteU32(0x401F8084,0x00000000); // EMC_28
  MEM_WriteU32(0x401F8088,0x00000000); // EMC_29
  MEM_WriteU32(0x401F808C,0x00000000); // EMC_30
  MEM_WriteU32(0x401F8090,0x00000000); // EMC_31
  MEM_WriteU32(0x401F8094,0x00000000); // EMC_32
  MEM_WriteU32(0x401F8098,0x00000000); // EMC_33
  MEM_WriteU32(0x401F809C,0x00000000); // EMC_34
  MEM_WriteU32(0x401F80A0,0x00000000); // EMC_35
  MEM_WriteU32(0x401F80A4,0x00000000); // EMC_36
  MEM_WriteU32(0x401F80A8,0x00000000); // EMC_37
  MEM_WriteU32(0x401F80AC,0x00000000); // EMC_38
  MEM_WriteU32(0x401F80B0,0x00000010); // EMC_39
  MEM_WriteU32(0x401F80B4,0x00000000); // EMC_40
  MEM_WriteU32(0x401F80B8,0x00000000); // EMC_41
  
  // PAD ctrl
  // drive strength = 0x7 to increase drive strength
  // otherwise the data7 bit may fail.
  MEM_WriteU32(0x401F8204,0x000110F9); // EMC_00
  MEM_WriteU32(0x401F8208,0x000110F9); // EMC_01
  MEM_WriteU32(0x401F820C,0x000110F9); // EMC_02
  MEM_WriteU32(0x401F8210,0x000110F9); // EMC_03
  MEM_WriteU32(0x401F8214,0x000110F9); // EMC_04
  MEM_WriteU32(0x401F8218,0x000110F9); // EMC_05
  MEM_WriteU32(0x401F821C,0x000110F9); // EMC_06
  MEM_WriteU32(0x401F8220,0x000110F9); // EMC_07
  MEM_WriteU32(0x401F8224,0x000110F9); // EMC_08
  MEM_WriteU32(0x401F8228,0x000110F9); // EMC_09
  MEM_WriteU32(0x401F822C,0x000110F9); // EMC_10
  MEM_WriteU32(0x401F8230,0x000110F9); // EMC_11
  MEM_WriteU32(0x401F8234,0x000110F9); // EMC_12
  MEM_WriteU32(0x401F8238,0x000110F9); // EMC_13
  MEM_WriteU32(0x401F823C,0x000110F9); // EMC_14
  MEM_WriteU32(0x401F8240,0x000110F9); // EMC_15
  MEM_WriteU32(0x401F8244,0x000110F9); // EMC_16
  MEM_WriteU32(0x401F8248,0x000110F9); // EMC_17
  MEM_WriteU32(0x401F824C,0x000110F9); // EMC_18
  MEM_WriteU32(0x401F8250,0x000110F9); // EMC_19
  MEM_WriteU32(0x401F8254,0x000110F9); // EMC_20
  MEM_WriteU32(0x401F8258,0x000110F9); // EMC_21
  MEM_WriteU32(0x401F825C,0x000110F9); // EMC_22
  MEM_WriteU32(0x401F8260,0x000110F9); // EMC_23
  MEM_WriteU32(0x401F8264,0x000110F9); // EMC_24
  MEM_WriteU32(0x401F8268,0x000110F9); // EMC_25
  MEM_WriteU32(0x401F826C,0x000110F9); // EMC_26
  MEM_WriteU32(0x401F8270,0x000110F9); // EMC_27
  MEM_WriteU32(0x401F8274,0x000110F9); // EMC_28
  MEM_WriteU32(0x401F8278,0x000110F9); // EMC_29
  MEM_WriteU32(0x401F827C,0x000110F9); // EMC_30
  MEM_WriteU32(0x401F8280,0x000110F9); // EMC_31
  MEM_WriteU32(0x401F8284,0x000110F9); // EMC_32
  MEM_WriteU32(0x401F8288,0x000110F9); // EMC_33
  MEM_WriteU32(0x401F828C,0x000110F9); // EMC_34
  MEM_WriteU32(0x401F8290,0x000110F9); // EMC_35
  MEM_WriteU32(0x401F8294,0x000110F9); // EMC_36
  MEM_WriteU32(0x401F8298,0x000110F9); // EMC_37
  MEM_WriteU32(0x401F829C,0x000110F9); // EMC_38
  MEM_WriteU32(0x401F82A0,0x000110F9); // EMC_39
  MEM_WriteU32(0x401F82A4,0x000110F9); // EMC_40
  MEM_WriteU32(0x401F82A8,0x000110F9); // EMC_41

  // Config SDR Controller Registers/
  MEM_WriteU32(0x402F0000,0x10000004); // MCR
  MEM_WriteU32(0x402F0008,0x00000081); // BMCR0
  MEM_WriteU32(0x402F000C,0x00000081); // BMCR1
  MEM_WriteU32(0x402F0010,0x8000001D); // BR0, 64MB OK
  MEM_WriteU32(0x402F0040,0x00000E31); // SDRAMCR0 OK
  MEM_WriteU32(0x402F0044,0x00774D22); // SDRAMCR1
  MEM_WriteU32(0x402F0048,0x000A0B0D); // SDRAMCR2
  MEM_WriteU32(0x402F004C,0x09090801); // SDRAMCR3
  MEM_WriteU32(0x402F0090,0x80000000); // IPCR0 OK
  MEM_WriteU32(0x402F0094,0x00000002); // IPCR1 OK
  MEM_WriteU32(0x402F0098,0x00000000); // IPCR2 OK
  MEM_WriteU32(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
  SDRAM_WaitIpCmdDone();
  MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF
  SDRAM_WaitIpCmdDone();
  MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF
  SDRAM_WaitIpCmdDone();
  MEM_WriteU32(0x402F00A0,0x00000033); // IPTXDAT OK
  MEM_WriteU32(0x402F009C,0xA55A000A); // SD_CC_IMS
  SDRAM_WaitIpCmdDone();
  MEM_WriteU32(0x402F004C,0x08080A01 ); // enable sdram self refresh again after initialization done.

  JLINK_SYS_Report("SDRAM Init Done");
}
void INTRAM_Init() {
    unsigned int gpr14_addr;
    unsigned int gpr16_addr;
    unsigned int gpr17_addr;
    unsigned int ret;
    
    gpr14_addr = 0x400AC038;
    gpr16_addr = 0x400AC040;
    gpr17_addr = 0x400AC044;
    ret = 0;
    
    // 448 KBytes of DTCM
    MEM_WriteU32(gpr17_addr,0x5AAAAAAA);
    
    
    ret = MEM_ReadU32(gpr16_addr);
    
    // Turn off DTCM
    //ret &= ~0x02;
    // Turn off ITCM
    ret &= ~0x01;
    MEM_WriteU32(gpr16_addr,ret);
    
    
    // Configure DTCM/ITCM size
    ret = MEM_ReadU32(gpr14_addr);
    // Mask ITCM/DTCM size bits
    ret &= ~0xFF0000;
    // Set DTCM size to 512KBytes
    ret |= 0xA00000;
    MEM_WriteU32(gpr14_addr,ret);
    
    ret = MEM_ReadU32(gpr16_addr);
    
    // FlexRAM_BANK_CFG_SEL
    ret &= ~0x04;
    ret |= 0x04;
    MEM_WriteU32(gpr16_addr,ret);
    JLINK_SYS_Report("INTRAM Init Done");
}

void WDOG_Disable(){
    unsigned int gpio_b1_13;

    gpio_b1_13 = 0x401F81B0;

    // Switch off WDOG1
    MEM_WriteU32(gpio_b1_13, 1);
}

/* SetupTarget */
int AfterResetTarget(void) {
  JLINK_SYS_Report("Enabling i.MXRT SDRAM");
  /*Load_Dcdc_Trim();*/
  WDOG_Disable();
  Clock_Init();
  SDRAM_Init();
  INTRAM_Init();
  JLINK_SYS_Report("Enable Power Switch On for debug");
  MEM_WriteU32(0x401BC000, 128);
}