diff --git a/passes/cmds/splitnetlist.cc b/passes/cmds/splitnetlist.cc
index 312834d40f6..42d45797c9b 100644
--- a/passes/cmds/splitnetlist.cc
+++ b/passes/cmds/splitnetlist.cc
@@ -161,10 +161,6 @@ struct SplitNetlist : public ScriptPass {
 		log("Running splitnetlist pass\n");
 		log_flush();
 
-		// Add buffers for pass-through and connections to constants
-		// so we can find cells that can be used by submod
-		Pass::call(design, "bufnorm -buf");
-
 		if (debug)
 			run_pass("write_rtlil post_buf.rtlil");
 
@@ -268,10 +264,6 @@ struct SplitNetlist : public ScriptPass {
 		// Execute the submod command
 		Pass::call(design, "submod");
 
-		// Remove buffers introduced by bufnorm
-		Pass::call(design, "techmap -D SIMLIB_NOCHECKS -map +/simlib.v t:$buf");
-		Pass::call(design, "clean");
-
 		log("End splitnetlist pass\n");
 		log_flush();
 	}
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 52fd59cf82a..f1541d65dc5 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -381,8 +381,8 @@ struct SubmodPass : public Pass {
 
 		if (opt_name.empty())
 		{
-			Pass::call(design, "opt_clean");
-			log_header(design, "Continuing SUBMOD pass.\n");
+			// Pass::call(design, "opt_clean");
+			// log_header(design, "Continuing SUBMOD pass.\n");
 
 			std::set<RTLIL::IdString> handled_modules;
 
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 55e155d3973..256eae8484e 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -601,7 +601,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool unusedbitsattr
 
 	std::vector<RTLIL::Cell*> delcells;
 	for (auto cell : module->cells())
-		if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) {
+		if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
 			bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
 			RTLIL::SigSpec a = cell->getPort(ID::A);
 			RTLIL::SigSpec y = cell->getPort(ID::Y);